1323497 九、發明說明： 【發明所屬之技術領域】 本發明提供一種製作銅雙鑲嵌結構之方法，尤指一種利 用原子化學氣相沉積方法形成阻障層以製作銅雙鑲嵌結構 之方法。 【先前技術】 隨著積體電路的積集度(integration)增加，多重金屬内連 線(multilevel interconnects)的製作便逐漸成為許多半導體 積體電路製程所必須採用的方式。而銅雙鑲嵌（dual damascene)技術搭配低介電常數材料所構成的金屬間介電 層（inter metal dielectric，IMD)是目前最受歡迎的金屬内連 線製程組合，尤其針對高積集度、高速(high-speed)邏輯積 體電路晶片製造以及0.18微米以下的深次微米（deep sub-micro)半導體製程，銅金屬雙鑲喪内連線技術在積體電 路製程中已曰益重要，而且勢必將成為下一世代半導體製 程的標準内連線技術。 請參閱第1圖，第1圖為習知一半導體晶片10的部份 剖面示意圖，其顯示一典型的雙鑲嵌結構11。如第1圖所 1323497 示，雙鑲嵌結構11係形成於一介電層20中，其包括有一 雙鑲嵌孔洞21以及填於其内之導電材料，分為一下部接觸 窗（via)結構22以及一上部溝渠結構23。一下層導線14係 形成於介電層12中，而一上層銅導線24係填入於上部溝 渠結構23中。上層銅導線24以及下層導線14可藉由接觸 插塞(via plug)22a穿過介電層12以及介電層20之間的保 護層18而互相連結。此外，銅雙鑲嵌結構u亦可應用於 用來電連接矽基底表面之電性元件以及其上之導線，在此 情況下，接觸插塞22a便會直接接觸矽基底之表面。 為了防止填入雙鑲嵌結構丨丨中的銅金屬發生遷移現象 而擴散至鄰近的介電層20中，導致漏電流(ieakage)情形， 一般係在將銅金屬填入雙鑲嵌孔洞21之前，先於雙鑲嵌孔 洞21表面形成一阻障層（barrier layer) 25。因此，為了有效 阻隔銅金屬擴散，阻障層h至少需具備有下列條件：〇) 良好的擴散阻絕特性；（2)對於銅金屬以及介電層有良好的 附著力，（3)電阻值不能過高；（4)良好的階梯覆蓋能力。常 用的阻障層材料包括找、氮化欽(TiN)L(TaN)、以 及氮化鶴卿)料。因此，崎鑲嵌結狀_技術之一 在於製作能有效防止銅原子向外擴散的阻障層。 習知製作銅雙鑲嵌結構以及改良阻障層之技術可參看 1323497 美國專利第6,403,465號「改善銅金屬阻障層性質之方法 (Method to Improve Copper Barrier Properties)」，其揭露在 形成銅金屬層之前，先於雙鑲嵌孔洞中進行一物理氣相沉 積(physical vapor deposition，PVD)製程或一化學氣相沉積 (chemical vapor deposition, CVD)製程形成一阻障層，並同 時（in-situ)利用一離子金屬電漿（ion-metal-plasma, IMP)沉 積製程形成一黏著（adhesion)層，以在雙鑲嵌孔洞表面形成 複合之黏著阻障層，其中阻障層的材料包含有氮化鈦 (titanium nitride)、氮化鎢（tungsten nitride)、氮矽化鎢 (tungsten silicon nitride)、氮矽化鈕（tantalum silicon nitride) 以及氮石夕化欽(titanium silicon nitride)等。在形成黏著阻障 層後，再於雙鑲嵌孔洞中形成金屬晶種層，以製作銅金屬 於雙鑲嵌孔洞中。 然而’隨著晶片積集度的提高，習知鋼雙鑲嵌結構的製 作技術已逐漸產生問題，例如當製程線寬小於65奈米 (nanometer，nm)時，利用傳統PVD或CVD製程製作阻障 層均會產生階梯覆蓋（step coverage)不良以及均勻度較差 的問題，導致對銅金屬沒有足夠的阻障效果，例如以傳統 PVD製程所形成的氮化鈦作為阻障層時，便無法有效阻絕 銅金屬擴散而容易產生漏電流。此外，由於均勾度差，阻 障層以及銅金屬亦可能無法完全填入雙鑲嵌孔洞中，造成 接觸插塞的缺陷。為克服上述問題，目前業界研發出以一 8 13234971323497 IX. Description of the Invention: [Technical Field] The present invention provides a method of fabricating a copper dual damascene structure, and more particularly to a method of forming a barrier layer by atomic chemical vapor deposition to form a copper dual damascene structure. [Prior Art] As the integration of integrated circuits increases, the fabrication of multiple metal interconnects has become a must for many semiconductor integrated circuit processes. The inter-metal dielectric (IMD) consisting of dual damascene technology combined with low dielectric constant materials is currently the most popular metal interconnect process combination, especially for high integration. High-speed logic integrated circuit chip fabrication and deep sub-micro semiconductor processes below 0.18 micron, copper metal double-inserted interconnect technology has been important in integrated circuit processes, and It is bound to become the standard interconnect technology for the next generation of semiconductor manufacturing. Referring to Figure 1, a first partial cross-sectional view of a conventional semiconductor wafer 10 shows a typical dual damascene structure 11. As shown in FIG. 11323497, the dual damascene structure 11 is formed in a dielectric layer 20, and includes a dual damascene hole 21 and a conductive material filled therein, which is divided into a lower via structure 22 and An upper trench structure 23. The lower layer conductors 14 are formed in the dielectric layer 12, and an upper layer copper conductor 24 is filled in the upper trench structure 23. The upper copper conductors 24 and the lower conductors 14 may be interconnected by a via plug 22a passing through the dielectric layer 12 and the protective layer 18 between the dielectric layers 20. In addition, the copper dual damascene structure u can also be applied to electrical components that are electrically connected to the surface of the substrate by wires and the wires thereon, in which case the contact plugs 22a directly contact the surface of the substrate. In order to prevent the copper metal filled in the dual damascene structure from migrating into the adjacent dielectric layer 20, the leakage current (ieakage) is generally caused before the copper metal is filled into the double damascene hole 21, A barrier layer 25 is formed on the surface of the dual damascene hole 21. Therefore, in order to effectively block the diffusion of copper metal, the barrier layer h must have at least the following conditions: 〇) good diffusion resistance; (2) good adhesion to copper metal and dielectric layer, (3) resistance value cannot Too high; (4) good step coverage. Common barrier materials include find, nitrided (TiN) L (TaN), and nitrided helium. Therefore, one of the techniques of the inlaid knot is to form a barrier layer that effectively prevents copper atoms from diffusing outward. For a technique for fabricating a copper dual damascene structure and an improved barrier layer, see 1,323,497 U.S. Patent No. 6,403,465, "Method to Improve Copper Barrier Properties," which discloses prior to forming a copper metal layer. Forming a barrier layer by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process in a dual damascene hole, and simultaneously utilizing a barrier layer in-situ An ion-metal-plasma (IM) deposition process forms an adhesion layer to form a composite adhesion barrier layer on the surface of the dual damascene cavity, wherein the barrier layer material comprises titanium nitride (titanium) Nitrile), tungsten nitride, tungsten silicon nitride, tantalum silicon nitride, and titanium silicon nitride. After the adhesion barrier layer is formed, a metal seed layer is formed in the dual damascene holes to form copper metal in the dual damascene holes. However, as the degree of wafer integration increases, the fabrication techniques of conventional steel dual damascene structures have gradually become problematic. For example, when the process line width is less than 65 nanometers (nm), the barrier layers are formed by conventional PVD or CVD processes. There will be problems with poor step coverage and poor uniformity, resulting in insufficient barrier effect on copper metal. For example, when titanium nitride formed by the conventional PVD process is used as a barrier layer, copper metal cannot be effectively blocked. Diffusion and easy to generate leakage current. In addition, due to the poor hook width, the barrier layer and the copper metal may not be completely filled in the double damascene holes, causing defects in the contact plug. In order to overcome the above problems, the current industry has developed an 8 1323497
種原子化學氣相沉積（atomic CVD)製程升彡成、 功效之氮化組(tanta丨um nitride)層作為阻障爲、有較佳阻障 銅金屬之擴散。然而，當銅雙鑲嵌結構係^，以有效阻擋 時，利用原子CVD製程形成氮化鈕阻障層時丨乍於矽基底上 月'J趨物（precursor)會造成石夕基底表面損壞或電性元件『、 疵。此外，銅金屬晶種層對原子CVD氮化鈕層的附著力不 佳’亦會造成後續形成銅金屬製程的困擾。 【發明内容】 因此，本發明之主要目的在於提供一種製作鋼雙鑲嵌結 構之方法’其係在形成阻障層之前先形成一基底保護層， 並利用特殊製程條件製程具有良好附著力的阻障層，以解 決上述習知銅雙鑲嵌結構的問題。 根據本發明之申請專利範圍，係揭露一種製作銅雙鑲嵌 結構之方法。首先提供一半導體基底，其上包含有至少一 介電層以及至少一雙鑲嵌孔洞設於該介電層中，且部分該 半導體基底係暴露於雙鑲嵌孔洞之底部。接著進行一物理 氣相沉積製程’於雙鑲嵌孔洞側壁以及暴露出之半導體基 底上形成一具導電性之基底保護層。然後進行一原子化學 氣相沉積（atomic CVD)製程，於基底保護層表面形成一氮 化I旦(tantalum nitride, TaN)層，作為一阻障層。最後於雙鑲 9 1323497 佚孔洞中形成一銅金屬層。 由於本發明係在利用原子CVD製程形成氮化鈕層之 前，先以PVD製程於暴露之半導體基底上形成一基底保護 層，因此可以有效避免形成氮化鈕層之前趨物傷害半導體 基底。此外，以原子CVD方法形成的氮化鈕層有較佳階梯 覆蓋能力以及阻障銅金屬擴散的功能，因此，另用本發明 ^ 方法製成之銅雙鑲嵌結構具有較佳電性效果。 _ 【實施方式】 請參考第2圖至第8圖，第2圖至第8圖為本發明製作 一銅雙鑲嵌結構方法之第一實施例的製程示意圖，其中本 實施例中之銅雙鑲嵌結構係直接製作於半導體基底上。如 第2圖所示，首先提供一半導體基底40，在半導體基底40 > 之表面上包含有至少一介電層42以及至少一雙鑲嵌孔洞 44設於該介電層42中。在第2圖中僅繪出一介電層42以 及一雙鑲嵌孔洞44作為說明，其中半導體基底40係為一 矽基底。值得注意的是，雙鑲嵌孔洞44的底部係暴露出部 分之半導體基底40，而暴露出的半導體基底40表面可另 包含有一導電層46,由金屬矽化物層或離子摻雜區所構成。 1323497 如第3圖所示，接著進行—pVD製程於雙鑲嵌孔洞 44側壁以及暴露出之半導體基底4()表面形成—基底保護 層48 ’其中基底保護層48係由具導電性之材料所形成， 其材料可包含有金屬欽(titanium，Ti)、金屬组(tantaium, Ta) 或氮化钽(tantalum nitride，TaN)，較佳為金屬鈕。由第3圖 可知’基底保護層48係完整覆蓋雙鑲嵌孔洞44底部之材料，例 如導電層104。在較佳實施例中，基底保護層48係由濺鍍方 式所製成，請參考第4圖，第4圖顯示以濺鍍方式形成基 底保護層48的反應室示意圖。半導體基底4〇(即晶圓）置於 晶圓架52上，而包含有基底保護層材料(例如金屬钽）的靶 材50設於晶圓架52的上方，在進行濺鍍時，靶材50與半 導體基底40的距離Hl大於5公分以上，以使形成的基底 保護層48有較佳階梯覆蓋能力，並維持良好的均勻度。 請參考第5圖，然後進行一原子CVD製程，於基底保 5蒦層表面形成一氣化组(tantalum nitride，TaN)層54，作為 銅金屬的阻障層。以原子CVD方法形成氮化鈕層54的前 趙物（precursor)包含有氨氣（ammonia，NH3)以及五二甲基 胺组（Ta(N(Me)2)5, pentakis(dimethylamido) tantalum， PDMAT)。其施行方式係在溫度範圍180〜400°C下先通入氨 氣數秒，然後將PDMAT通入反應室中，將其清除(purge) 11 1323497 後’再依序反覆通入氨氣以及PDMAT，利用氨氣將pdm AT 中的氬化钽置換出來沉積於介電層42以及雙鑲嵌孔洞44 表面上，如此在每一循環中形成0.5H埃細§也〇111，人），直 至達到預定的氮化鈕層54厚度。如第5圖所示，氮化鈕層54 在雙鑲嵌孔洞内44只與基底保護層48相接觸而不與半導體基底 40上之其他元件相接觸。 請參考第6圖，接著可選擇性以PVD製程在氮化鈕層 54表面形成一黏著（adhesion)層56,其材料較佳為金屬钽。 然後以IMP、PVD或CVD製程沉積一晶種層58於黏著層 56表面，以利後續形成銅金屬層。其中，黏著層56的作 用在於使晶種層58具有良好附著力，以沿著雙鑲嵌孔洞 44的侧壁及底部沉積。其中，在以PVD製程形成黏著層 56時，濺鍍反應室中的金屬靶材64與半導體基底4〇、晶 圓架68的距離H2範圍約為1 〇〜5〇公分，如第7圖所示， 以使黏著層56有較佳均勻度。 接著請參考第8圖，進行一電化學沉積製程 (electrochemical deposition，ECD)’在雙鑲嵌孔洞 44 中形成 銅金屬層60 ’此時，晶種層58已成為銅金屬層6〇的一部 份。最後進行一平坦化製程，例如化學機械研磨製程 12 1323497 (chemical mechanical polishing，CMP)，以介雷 电層42的表面 作為研磨停止層，使銅金屬層60之表面約略^ _ 子目同於介電層 42的表面’以完成半導體基底40表面上鋼雔 … 八鐵嵌結構62 的製作。 再 在本實施例中，利用原子CVD製成之氮# G起層54具有The atomic CVD process enhances the tantalum nitride layer as a barrier and has better barrier copper metal diffusion. However, when the copper dual damascene structure is used for effective blocking, the formation of a nitride button barrier layer by an atomic CVD process may cause damage to the surface of the stone substrate or electricity. Sexual components 『, 疵. In addition, the poor adhesion of the copper metal seed layer to the atomic CVD nitride button layer also causes problems in the subsequent formation of the copper metal process. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a method for fabricating a steel dual damascene structure which is formed by forming a base protective layer prior to forming a barrier layer and using a special process condition to have a good adhesion barrier. Layer to solve the above problems of the conventional copper dual damascene structure. In accordance with the scope of the patent application of the present invention, a method of making a copper dual damascene structure is disclosed. First, a semiconductor substrate is provided having at least one dielectric layer and at least one dual damascene hole disposed in the dielectric layer, and a portion of the semiconductor substrate is exposed to the bottom of the dual damascene hole. A physical vapor deposition process is then performed to form a conductive substrate protective layer on the sidewalls of the dual damascene holes and the exposed semiconductor substrate. Then, an atomic chemical vapor deposition (CVD) process is performed to form a tantalum nitride (TaN) layer on the surface of the underlayer protection layer as a barrier layer. Finally, a copper metal layer is formed in the double-inlaid 9 1323497 pupil hole. Since the present invention forms a base protective layer on the exposed semiconductor substrate by a PVD process before forming the nitride button layer by the atomic CVD process, it is possible to effectively prevent the semiconductor substrate from being damaged by the formation of the nitride button layer. In addition, the nitride button layer formed by the atomic CVD method has a function of better step coverage and barrier copper metal diffusion. Therefore, the copper dual damascene structure formed by the method of the present invention has a better electrical effect. _ [Embodiment] Please refer to FIG. 2 to FIG. 8 , FIG. 2 to FIG. 8 are schematic diagrams showing a process of fabricating a copper dual damascene structure according to a first embodiment of the present invention, wherein the copper dual damascene in the embodiment The structure is fabricated directly on a semiconductor substrate. As shown in FIG. 2, a semiconductor substrate 40 is first provided, and at least one dielectric layer 42 and at least one dual damascene hole 44 are provided in the dielectric layer 42 on the surface of the semiconductor substrate 40 > In Fig. 2, only a dielectric layer 42 and a dual damascene hole 44 are illustrated, wherein the semiconductor substrate 40 is a germanium substrate. It should be noted that the bottom of the dual damascene cavity 44 exposes a portion of the semiconductor substrate 40, and the exposed surface of the semiconductor substrate 40 may further include a conductive layer 46 composed of a metal telluride layer or an ion doped region. 1323497 As shown in FIG. 3, a -pVD process is then performed on the sidewalls of the dual damascene via 44 and the exposed semiconductor substrate 4() surface-substrate protective layer 48' wherein the base protective layer 48 is formed of a conductive material. The material may comprise a metal (titanium, Ti), a metal group (tantaium, Ta) or a tantalum nitride (TaN), preferably a metal button. As can be seen from Fig. 3, the base protective layer 48 is a material that completely covers the bottom of the dual damascene hole 44, such as the conductive layer 104. In the preferred embodiment, the substrate protective layer 48 is formed by sputtering, please refer to FIG. 4, which shows a schematic view of a reaction chamber in which a substrate protective layer 48 is formed by sputtering. A semiconductor substrate 4 (ie, a wafer) is placed on the wafer holder 52, and a target 50 including a base protective layer material (for example, a metal crucible) is disposed above the wafer holder 52, and the target is used for sputtering. The distance H1 from the semiconductor substrate 40 is greater than 5 cm or more so that the formed base protective layer 48 has a better step coverage and maintains good uniformity. Referring to Figure 5, an atomic CVD process is then performed to form a tantalum nitride (TaN) layer 54 on the surface of the substrate to serve as a barrier layer for copper metal. The precursor of the nitride button layer 54 formed by the atomic CVD method contains ammonia (NH3) and pentadimethylamine (Ta(N(Me)2)5, pentakis(dimethylamido) tantalum, PDMAT). The mode of operation is to introduce ammonia gas into the reaction chamber for a few seconds at a temperature range of 180 to 400 ° C. Then, the PDMAT is introduced into the reaction chamber, and it is purged 11 1323497, and then the ammonia gas and the PDMAT are repeatedly introduced in sequence. The argon arsenide in the pdm AT is displaced by ammonia gas and deposited on the surface of the dielectric layer 42 and the dual damascene holes 44, thus forming 0.5H Å, 〇111, in each cycle, until a predetermined The thickness of the nitride button layer 54. As shown in FIG. 5, the nitride button layer 54 is in contact with the base protective layer 48 in the dual damascene hole 44 and is not in contact with other components on the semiconductor substrate 40. Referring to FIG. 6, an adhesion layer 56 may be selectively formed on the surface of the nitride button layer 54 by a PVD process, and the material is preferably a metal crucible. A seed layer 58 is then deposited on the surface of the adhesive layer 56 by an IMP, PVD or CVD process to facilitate subsequent formation of a copper metal layer. Among other things, the adhesive layer 56 serves to provide the seed layer 58 with good adhesion to deposit along the sidewalls and bottom of the dual damascene holes 44. Wherein, when the adhesive layer 56 is formed by the PVD process, the distance H2 between the metal target 64 in the sputtering reaction chamber and the semiconductor substrate 4 and the wafer holder 68 is about 1 〇 5 5 cm, as shown in FIG. 7 . It is shown that the adhesive layer 56 has a better uniformity. Next, referring to FIG. 8, an electrochemical deposition process (ECD) is performed to form a copper metal layer 60 in the dual damascene hole 44. At this time, the seed layer 58 has become a part of the copper metal layer 6〇. . Finally, a planarization process, such as a chemical mechanical polishing process 12 1323497 (chemical mechanical polishing, CMP), is used, and the surface of the dielectric layer 42 is used as a polishing stop layer, so that the surface of the copper metal layer 60 is approximately the same as the dielectric. The surface ' of the layer 42' is used to complete the fabrication of the steel truss on the surface of the semiconductor substrate 40. Further in this embodiment, the nitrogen #G layer 54 made by atomic CVD has
良好的均勻度以及階梯覆蓋能力，且對於麵j金 ^ 果也非常良好，但由於銅雙鑲嵌結構62係制从 阻卩早效 11乍於半導I#其 底40表面，導致在以原子CVD製程形成氮彳 土 匕起層54 ， 前趨物氨氣會與半導體基底40表面的矽原子作_ ^ 半導體基底40的傷害，因此在形成氮化钽層54而&造成 先於暴露出的半導體基底40表面形成基底保$爲、、頁 護半導體基底40。同時，本發明提出使靶^ 9 48以保 1 與丰填^ _ 基底40之距離大於5公分以進行濺鍍製程 、]條件，可伸其 底保護層48在沉積時具有較佳的均勻度。 土 ,α ’在形成 黏著層56時’本發明亦提供了使金屬靶材 半^ 導 底40間之距離Η2有一相當長的距離範圍1〇〜5〇八、 使黏著層56有較佳的沉積效果。 請參考第9圖至第Η)圖，第9圖至第1〇圖為本發明第 二實施例的剖面示意圖。首先於第9圖所示，提供一基底 13 1323497 100,而基底100上包含有至少一導電層104以及至少一介 電層102，其中導電層104的材料包含有鋁、鋁銅合金、 銅、金屬矽化物或上述之組合。然後於介電層102中形成 至少一雙鑲嵌孔洞108，並暴露出部分導電層104。 接著，進行一原子CVD製程，於雙鑲嵌孔洞108側壁 以及暴露出之導電層104上形成一氮化鈕層110，作為一 第一阻障層。其中在以原子CVD製程製作氮化鈕層110 時，可選擇以氨氣以及PDMAT氣體作為前驅物。值得注 意的是，氮化姐層110的厚度約為8〜28埃(angstrom, A)。 請參考第10圖，接著進行一 PVD製程，於氮化钽層110 表面形成一钽金屬層112，且在進行PVD濺鍍製程時，含 有鈕金屬的靶材與基底1〇〇的距離約為10〜50公分，其中 钽金屬層112係作為第二阻障層，其對後續形成的金屬晶 種層有較佳附著力。最後，在基底100以及雙鑲嵌孔洞108 表面形成一金屬晶種層，再利用該金屬晶種層形成一銅金 屬層114，最後進行一化學機械研磨製程，以完成銅雙鑲 嵌結構120的製作。 相較於習知技術，本發明方法係在銅雙鑲嵌結構中利用 14 原子CVD製程形成具有良好阻障能力的氮她層作為鋼 金屬的阻障層，同時配合在特殊條件下形成的基底保護層 以及黏著層，例如㈣PVD録#材與半導縣底距曰 離’以使銅雙鑲嵌結構有較佳的效能j由本發明方法所 製作的銅雙職結構具有触㈣雜，且能有效改盖習 知技術中漏電流的問題’因此能使晶片有較佳性能/ 實施例，凡依本發明申請專 皆應屬本發明之涵蓋範圍。 以上所述僅為本發明之較佳 利範圍所做之均等變化與修飾， 【圖式簡單說明】 第1圖為習知一半導體晶片 第2圖至第8圖為本發明製 實施例的製程示意圖。 部份剖面示意圖。 一銅雙鑲嵌結構方法之第一 第9圖至第 10圖為本發明第 二實施例的剖面示意圖 【主要元件符號說明】 10 半導體晶片 11 12 介電層 14 18 保護層 20 21 雙鑲嵌孔洞 22 雙鑲嵌結構 導電層 介電層 接觸窗結構 1323497Good uniformity and step coverage, and also very good for the surface j gold, but because the copper dual damascene structure 62 system is from the obstruction, the effect is 11 乍 on the bottom surface of the semi-conductive I#, resulting in the atom The CVD process forms a yttrium-boring layer 54. The precursor gas ammonia and the germanium atoms on the surface of the semiconductor substrate 40 are damaged by the semiconductor substrate 40, and thus the tantalum nitride layer 54 is formed and & The surface of the semiconductor substrate 40 forms a substrate and a semiconductor substrate 40. At the same time, the present invention proposes that the target can be subjected to a sputtering process by a distance of more than 5 cm from the substrate 40, and the bottom protective layer 48 can have a better uniformity during deposition. . The soil, α 'in the formation of the adhesive layer 56 'the present invention also provides a distance Η 2 between the metal target half of the bottom 40 has a considerable distance range of 1 〇 ~ 5 〇 eight, so that the adhesive layer 56 is better Deposition effect. Referring to Figures 9 through Η, Figs. 9 through 1 are schematic cross-sectional views showing a second embodiment of the present invention. First, as shown in FIG. 9, a substrate 13 1323497 100 is provided, and the substrate 100 includes at least one conductive layer 104 and at least one dielectric layer 102. The material of the conductive layer 104 includes aluminum, aluminum-copper alloy, copper, Metal halide or a combination of the above. At least one dual damascene hole 108 is then formed in the dielectric layer 102 and a portion of the conductive layer 104 is exposed. Next, an atomic CVD process is performed to form a nitride button layer 110 on the sidewalls of the dual damascene holes 108 and the exposed conductive layer 104 as a first barrier layer. When the nitride button layer 110 is formed by an atomic CVD process, ammonia gas and PDMAT gas can be selected as precursors. It is worth noting that the thickness of the nitride layer 110 is about 8 to 28 angstroms (angstrom, A). Referring to FIG. 10, a PVD process is then performed to form a germanium metal layer 112 on the surface of the tantalum nitride layer 110. When the PVD sputtering process is performed, the distance between the target containing the button metal and the substrate 1 is approximately 10 to 50 cm, wherein the base metal layer 112 serves as a second barrier layer, which has better adhesion to the subsequently formed metal seed layer. Finally, a metal seed layer is formed on the surface of the substrate 100 and the dual damascene holes 108, and a copper metal layer 114 is formed by using the metal seed layer. Finally, a chemical mechanical polishing process is performed to complete the fabrication of the copper double damascene structure 120. Compared with the prior art, the method of the present invention uses a 14-atom CVD process to form a nitrogen barrier layer with good barrier capability as a barrier layer of steel metal in a copper dual damascene structure, and at the same time, a substrate protection formed under special conditions. The layer and the adhesive layer, for example, (4) PVD recording material and the semi-conducting bottom distance of the semiconductor to make the copper dual damascene structure have better performance. The copper double-position structure produced by the method of the invention has the touch (four) impurity and can be effectively modified. Covering the problem of leakage current in the prior art 'so that the wafer has better performance/embodiments, and all applications in accordance with the present invention should fall within the scope of the present invention. The above description is only for the uniform variation and modification of the preferred range of the present invention, [Simplified Description of the Drawings] FIG. 1 is a schematic view of a conventional semiconductor wafer according to a second embodiment of the present invention. schematic diagram. Partial cross-section diagram. A first through ninth to tenth embodiment of a copper dual damascene structure method is a schematic cross-sectional view of a second embodiment of the present invention. [Main element symbol description] 10 semiconductor wafer 11 12 dielectric layer 14 18 protective layer 20 21 dual damascene hole 22 Double damascene structure, conductive layer, dielectric layer contact window structure 1323497
22a 接觸插塞 23 24 上層銅導線 25 40 半導體基底 42 44 雙鑲嵌孔洞 46 48 基底保護層 50 52 晶圓架 54 56 黏著層 58 60 銅金屬層 62 64 靶材 68 100 基底 102 104 導電層 108 110 說化钽層 112 114 銅金屬層 120 導線槽結構 阻障層 介電層 導電層 靶材 氮化组層 晶種層 銅雙鑲嵌結構 晶圓架 介電層 雙鑲嵌孔洞 组金屬層 銅雙鑲嵌結構22a contact plug 23 24 upper copper wire 25 40 semiconductor substrate 42 44 dual damascene hole 46 48 base protective layer 50 52 wafer holder 54 56 adhesive layer 58 60 copper metal layer 62 64 target 68 100 substrate 102 104 conductive layer 108 110 Polysilicon layer 112 114 Copper metal layer 120 Conductor structure barrier layer Dielectric layer Conductive layer Target Nitriding Group layer Seed layer Copper Double damascene structure Wafer frame Dielectric layer Double damascene hole group Metal layer Copper double damascene structure
1616