TW464991B - Semiconductor chip resin-sealing method and adhesive tape for pasting lead frames - Google Patents

Semiconductor chip resin-sealing method and adhesive tape for pasting lead frames Download PDF

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Publication number
TW464991B
TW464991B TW089106803A TW89106803A TW464991B TW 464991 B TW464991 B TW 464991B TW 089106803 A TW089106803 A TW 089106803A TW 89106803 A TW89106803 A TW 89106803A TW 464991 B TW464991 B TW 464991B
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Taiwan
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adhesive tape
resin
lead frame
adhesive
semiconductor wafer
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TW089106803A
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English (en)
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Yoshihisa Furuta
Yoshinori Watanabe
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Nitto Denko Corp
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

464991 五、發明說明（1) [發明所屬之技術領域] 本發明係關於一種半導體晶片之樹脂密封方法及在該方 法中所使用之引線框架等貼合用黏著帶者。 [背景技術] 在製造QEP等之封裝半導體裝置時，對引線框架黏著半 導體晶片，接著在金屬壓模之模腔内收容半導體晶片，以 轉移注射成形法，用樹脂密封半導體晶片。 然而，為了要防止從金屬壓模與引線框架之間之接觸界 面之樹脂茂漏’需要相當地擴大其接觸面，必需要相當地 加大對模腔空間之其接觸面面積之比率，，在同一金屬壓 模尺寸之下，以一次注射所能密封之晶月數量變少，在作 對效率上非常不利。 士’對金屬壓模内注入之樹脂流’有使晶片移動而破損 黏著4位之可此性，為了要排除該危險性，金屬μ模造 之複雜化是無法避免的。 、 穷: t於提供一種可提高半導體晶片之樹脂 ^ " 可確實防止黏著部位之破損之半導體曰片 之樹脂密封方法者。 干导避曰日片 [發明之揭示] 有關本發明之半 或薄膜載體帶黏貼 黏著半導體晶片， 片，然後，剥離黏 時之熱收縮率為3 % 導體晶片之樹脂密 黏著帶，對該附有 接著，藉金屬壓模 著帶之方法；該黏 以下之黏著帶為其 封方法係對引線框架 黏著帶框架或载體帶 用樹脂密封半導體晶 著帶係使用樹脂密封 特徵之構成者。又，
89106803.ptd
464991 五、發明說明（2) 所謂”樹脂密封時之熱收縮率在3%以下”係指在密封溫度中 帶子之縱橫方向中之至少任一方向之熱收縮在3%以下而 言 ° [實施發明之最佳形態] 茲參考圖式，就本發明之實施形態說明如下》 圖1 A〜E係顯示有關本發明之半導體晶片之樹脂密封方 法之一例之圖。 圖1 A係附有黏著帶之引線框架a，其中1係引線框架，係 在裝置孔之内部，將設有多數條針腳11之單位群予以一體 化如圖2所示。2係黏著於引線框架1之黏著帶，將樹脂密 封時之熱收縮率抑制於3%以下，較宜是在2%以下，而丨％以 下為最宜。21係黏著劑層，22係基材。 用本發明製造樹脂密封半導體晶片時，如圖丨B所示，對 附有黏著帶之引線框架A之各裝置孔内配置半導體晶片3而 黏著固定，該晶體3與引線框架1之針腳〗丨之間予以引線接 合3 1，接著如圖丨c所示，在樹脂密封過程中把半導體晶片 3/欠，於金屬壓模4之各模腔41内，用轉移注射成形法實行 樹脂密封，然後，如圖丨D所示，從引線框架】剝離黏著帶 之後修整引線框架而製造如圖1E所示之樹脂密封半導體晶 加Γ:腳r金屬壓模與引線框架之接觸界面，有引線框 楔進黏著帶2之黏著劑層21使#著劑層21 腳11成同一平面，針腳間之黏著劑層21黏著於金屬壓模 ，黏者劑成為密封劑而作用的關係可呈現很高的密封
^ 6 4 99 1 五、發明說明（3) ' '' - 性。 —因此’增加黏著劑層21之厚度而可發揮密封效果。又， 密封樹脂充滿於針腳丨丨之橫方内深部時，也增加金屬壓模 壓力及黏著力之結果可發揮充分的密封效果，按用途而分 別使用之。 上述之樹脂密封時，因金屬壓模之熱度而同時加熱黏著 帶’使黏著帶熱收縮。由於該黏著帶之熱收縮之結果在附 有黏著帶引線框架與金屬壓模之接觸面發生剪斷應力，當 該煎斷應力變大時，由於剪斷滑動而有發生降低密封性之 可能性’然而’在本發明中’使用樹脂密封時之熱收縮率 在3%以下，較宜為2%，而最宜為1%，之黏著帶的關係，在 樹脂密封中也可维持上述之高度密封性。 因此’縮小金屬壓模與引線框架之接觸界面之面積時也 能夠充分地實行密封；縮小該接觸界面之面積而增多模腔 數量之結果’可增加注射一次樹脂所能密封之晶片數量。 又’由於黏著劑層黏著固定晶片的關係，對樹脂之注入流 能夠穩定地維持晶片之固定狀態，可防止黏著部位之破 損。 上述黏著帶之黏著力為，從金屬壓模與引線框架之間之 密封之點而言’儘量高為宜，然而，從樹脂密封後要從引 線框架剝離黏著帶之點而言，應儘量低為宜。因而，應使 用在樹脂密封後攝氏2 3度時之對引線框架之黏著力在 400gf/20mm 以下，較宜是 3〇〇gf/2〇mm 以下，而 5gf/20mm 以 上（未滿5gf/20 mm時，使用中容易剝離）之黏著帶為宜。
89106803.ptd 第6頁 4 64 99 1 五、發明說明（4) ---~- 上述樹脂密封時之加熱條件通常是攝氏丨8〇度左右，杂 然上述黏耆帶應具備有對該溫度之对熱性。 ° 上述黏著帶之支持基材為，可使用能夠滿足上述諸條件 之耐熱基材，例如聚亞胺膜，聚次苯基硫化物等之耐熱性 塑膠膜，玻璃布等。樹脂密封時之加熱條件為攝氏丨5〇度 以下時’也可以使用聚乙烯對苯二酸酯膜。 a 上述黏著帶之黏著劑為’只要能夠滿足上述諸條件者可 使用丙烯酸系黏著劑，矽系黏著劑之外，也可使用環氧系 黏著劑等’而使用耐熱性優良之矽系黏著劑為宜。為了要 滿足前述剝離力之要件，視其必要可以添加適當的填充劑 (例如，玻璃珠，各種無機填充劑，耐熱性有機填充劑 等）。樹脂密封時之加熱而發泡使剝離力成4〇〇gf /帶寬幅 2Omm以下之發泡性黏著劑也可使用之。 上述支持基材之厚度係以5〜250微米，而以5〜1〇〇微米 為宜（未滿5微米時容易發生折斷，龜裂及浮動等而降低作 業性。超過250微米時會降低金屬壓模至樹脂之導熱效 率）。 前述黏著劑層之厚度係2〜1 0 0微米’而以5〜7 5微米為 宜（未滿2微米時塗敷困難’容易發生接觸不良及浮動等。 超過1 0 0微米時塗敷困難，側面有接著劑溢出而使異物容 易附著，加熱時之氣體發生量變多）。 前述黏著劑層係可適當地予以交聯（br i dg i ng)以便避免 產生凝聚破壞所致之漿糊殘留之狀態下在界面破壞時可剝 離乾淨而不殘留漿糊，以及把黏著力調整為低。
89106803.ptd 第7頁 464991
為防止上述支持基材與黏著劑層之 時施以底塗或實行表面凹a #神π雕起見，必要 认一 卸凹凸處理’例如飛濺處理等。 為南上述樹脂密封日鼻夕A # 4 t 熱效率，對黏著劑層添加導 熱性粒子，例如鼠化哪也可以。. 在製造上述半導體裝置中會發生摩擦靜f。因此， ^心靜電衝擊所致之晶片之破壞時，以支持體作為導電有 材，以及添加導電性粒例如碳鎳或碳黑 劑層成為導電性。 考 本發明是也可以適用於TAB方式，其實施方法為，對膜 載體帶（例如聚亞胺膜設有銅箔指者）之背面黏貼黏著帶， 對該附有黏著帶之臈载體帶之各裝置孔内配置半導體晶片 而黏著固定，該晶片與膜載體帶之鋼羯指之間予以Au_Sn 共晶接合’接著，在樹脂密封過程中把半導體晶片收容於 金屬壓模之各模腔内’以轉移注射成形而實行樹脂密封， 然後，修整膜載體帶而製成樹脂密封半導體晶片者。 兹顯示實施例及比較例將本發明更詳細地說明如下，然 而本發明並非限定於該等實施例及比較例β [比較例1 ] 對未黏貼黏著帶之引線框架（Cu系統，針腳數1 〇 〇條）單 體黏接晶片，夾在金屬壓模内’用攝氏2〇〇度χ2〇 kg/平方 公分之條件下實行樹脂密封之結果，發生樹脂茂漏。 [實施例1 ] · 對矽系統黏著劑1 〇 〇重量分均勻地混合白金觸媒〇, 5重量 分，將其塗敷於厚度25微米之聚亞胺膜，以攝氏130度X5
89106S03.ptd 第8頁 464991 五 '發明說明（6) 條件下加熱乾燥，以製造黏著劑層厚度1。微米之黏 該黏著帶在攝氏200度時之熱收縮率係〇.5%以下 氏23度時之對引線框架之初期黏接力係，在 氏20 0度下而一小時後之黏接力係18〇gf/2〇mm，在攝氏 度下而五小時後之黏接力係2〇〇gf/2〇_。又，熱收縮率係 帶長300隨，寬幅19_，標線間距離2〇〇龍之樣品帶在攝 20 0度下，放置兩小時後，測定冷卻至攝氏23度後之標線 間JW，[(收縮剛之標線間隔_收縮後之標線間隔）/收縮前 之標線間隔]X 1 0 0 (% )來求得者。 將該黏著帶黏貼於在比較例1所使用者相同之引線框 架，與比較例1同樣方法實行樹脂密封，接著，剝離黏著 τ之結果’並無發生樹脂戌漏’又無引線框架之變形。 [實施例2 ] 黏著帶’使用在攝氏2 00度時之熱收縮率係〇, 5%以下， 在攝氏23度時之對引線框架之初期黏接力係5〇〇gf/2〇mm， 在攝氏200度下而一小時後之黏接力係55〇gf/2〇mm，在攝 氏200度下而五小時後之黏接力係550gf/20mm之既存之石少 黏著帶（黏接層厚3 0微米’基材厚度2 5微米）以外，其餘均 與實施例1同樣的條件及方法實行樹脂密封。 黏著帶之黏接力比實施例1較高，剝離黏著帶時引線框 架稍有變形，但未發生樹脂洩漏之現象。 從該實施例可確認’黏著帶使用樹脂密封後之黏接力在 400gf/20_以下之黏著帶為最有利。
酬
89106803,ptd 第9頁 464991 五、發明說明（7) [實施例3 ] 黏著帶，使用在攝氏200度時之熱收縮率係2%以下，在 攝氏23度時之對引線框架之初期黏接力係22〇gf/2〇mm，在 攝氏200度下而一小時後之黏接力係3〇〇gf/2〇mm，在攝氏 2 0 0度下而五小時後之黏接力係3〇〇gf/2〇mm之矽黏著帶（黏 接層厚1 0城米’基材厚度2 5微米）以外’其餘均與實施例1 同樣的條件及方法實行樹脂密封之結果，得到與實施例j 同樣的結果。 [比較例2 ] 黏著帶，使用在攝氏200度時之熱收縮率係7, 5%，在攝 氏23度時之對引線框架之初期黏接力係7〇〇gf/2〇mm，在攝 氏200度下而一小時後之黏接力係75〇gf/2〇mm，在攝氏2〇〇 度下而五小時後之黏接力係75〇gf/20mm之既存之♦黏著帶 (黏接層厚3 0微米’基材厚度2 5微米）以外，其餘均與實施 例1同樣的條件及方法實行樹脂密封之結果，發生樹脂茂 漏。又，在樹脂密封時引線框架發生變形。 從上述之結果’可確認在本發明中使用樹脂密封時之熱 收縮率為在3%以下之黏著帶之意義。 … [產業上之利用可能性] 根據本發明’將半導體晶片黏接於引線框架或臈載體 帶’其次’使用金屬壓模以樹脂密封半導體晶片時，可充 分地縮小引線框架等與金屬壓模之接觸界面而可增加模腔 數量的關係，可增多一次注射成形之密封晶片數量，可提 高樹脂密封效率。
464 99 1 五、發明說明（8) 又，可良好地防止樹脂密封中之黏接部位之破損，可以 優良的生產率來完成樹脂密封作業。 再者，可防止異物進入引線框架之針腳，可防止發生損 傷，以及防止樹脂洩漏所引起的塵埃之發生等而可提高樹 脂密封品質。 [元件編號之說明] 1 引線框架 2 黏著帶 3 半導體晶片 4 金屬壓模 11 針腳 21 黏著劑層 22 基材 31 引線接合 41 金屬模腔
39106803.ptd 第U頁 4 6^-991
89106803.ptd 第12頁

Claims (1)

  1. 464991 ^0. δ. 29 修正太 六、申請專利範圍 1 · 一種半導體晶片之樹脂密封方法，其特徵為： 對引線框架黏貼黏著帶’對該附有黏著帶框架黏貼半導 體a曰片’接著，藉金屬壓模用樹脂密封半導體晶片，然 後，剝離黏著帶之方法；而該黏著帶在使用樹脂密封時之 熱收縮率為在3%以下。 、2.如申請專利範圍第丨項之半導體晶片之樹脂密封方 法’其中，代替引線框架而使用膜載體帶。 、3 ‘種引線框架等黏貼用黏著帶’其特徵為：此黏著帶 為申請專利範圍第1或2項之半導體晶片之樹脂密封方法中 所使用之黏著帶，其中在樹脂密封時之熱收縮率為3%以 下。
    \\326\2d-\89-07\89106803.ptd 第13頁
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103064248A (zh) * 2011-10-21 2013-04-24 联胜（中国）科技有限公司 薄膜图案的制作方法及基板结构
CN103305138A (zh) * 2012-03-08 2013-09-18 日东电工株式会社 树脂密封用压敏粘合带和树脂密封型半导体器件的生产方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4703842B2 (ja) * 2000-11-30 2011-06-15 日東電工株式会社 堰材、及びこの堰材を用いた封止電子部品の製造方法
KR100709007B1 (ko) * 2001-04-13 2007-04-18 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법
JP2002343816A (ja) * 2001-05-18 2002-11-29 Lintec Corp 樹脂タイバー形成用テープ、樹脂タイバー、樹脂タイバー付リードフレーム、樹脂封止型半導体装置およびその製造方法
WO2003083940A1 (fr) * 2002-03-29 2003-10-09 Matsushita Electric Industrial Co., Ltd. Procede de fabrication d'un substrat thermoconducteur
US7061077B2 (en) 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
CN1698200A (zh) 2003-02-19 2005-11-16 日立化成工业株式会社 半导体用粘着薄膜 ,使用该粘着薄膜的附有粘着薄膜金属板 ,附有该粘着薄膜的配线电路及半导体装置 ,以及半导体装置的制造方法
JP4125668B2 (ja) 2003-12-19 2008-07-30 日東電工株式会社 半導体装置の製造方法
JP2005252142A (ja) * 2004-03-08 2005-09-15 Shin Etsu Polymer Co Ltd 薄型基板用固定治具
KR100635053B1 (ko) 2005-06-21 2006-10-16 도레이새한 주식회사 전자부품용 접착테이프
WO2006114825A1 (ja) * 2005-04-06 2006-11-02 Renesas Technology Corp. 半導体装置の製造方法
JP2008047558A (ja) * 2006-08-10 2008-02-28 Nitto Denko Corp 反り抑制ウエハ研削用粘着シート
JP2008207450A (ja) * 2007-02-27 2008-09-11 Towa Corp 発光素子の圧縮成形方法
JP5067927B2 (ja) * 2007-03-27 2012-11-07 日東電工株式会社 半導体装置製造用接着フィルム
JP5125702B2 (ja) * 2008-04-07 2013-01-23 株式会社デンソー 電子装置の製造方法
WO2012002446A1 (ja) * 2010-07-02 2012-01-05 独立行政法人産業技術総合研究所 微小機械システム
EP3040390B1 (en) * 2013-08-29 2019-07-17 Mitsui Chemicals Tohcello, Inc. Adhesive film and method for manufacturing seminconductor device
CN108831839B (zh) * 2018-06-22 2020-03-24 苏州震坤科技有限公司 一种去除半导体塑封制程中所产生毛边的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0210748A (ja) * 1988-06-29 1990-01-16 Toshiba Corp 電子部品の実装方法
US5366809A (en) * 1993-09-02 1994-11-22 Dow Corning Corporation Silicone pressure-sensitive adhesives
US5849397A (en) * 1995-10-03 1998-12-15 Ube Industries, Ltd. Aromatic polyimide film and polyimide/copper foil composite sheet
JPH10189626A (ja) * 1996-12-24 1998-07-21 Nippon Retsuku Kk 電子部品の製造方法
JP2971834B2 (ja) * 1997-06-27 1999-11-08 松下電子工業株式会社 樹脂封止型半導体装置の製造方法
JP3729992B2 (ja) * 1997-08-28 2005-12-21 株式会社ルネサステクノロジ 半導体装置の製造方法およびそれに使用されるテープキャリア

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103064248A (zh) * 2011-10-21 2013-04-24 联胜（中国）科技有限公司 薄膜图案的制作方法及基板结构
CN103305138A (zh) * 2012-03-08 2013-09-18 日东电工株式会社 树脂密封用压敏粘合带和树脂密封型半导体器件的生产方法

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