WO2000062338A1 - Procede permettant de sceller par une resine une plaquette a semi-conducteur et bande adhesive permettant de coller des reseaux de conducteurs ou similaires - Google Patents

Procede permettant de sceller par une resine une plaquette a semi-conducteur et bande adhesive permettant de coller des reseaux de conducteurs ou similaires Download PDF

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Publication number
WO2000062338A1
WO2000062338A1 PCT/JP1999/007387 JP9907387W WO0062338A1 WO 2000062338 A1 WO2000062338 A1 WO 2000062338A1 JP 9907387 W JP9907387 W JP 9907387W WO 0062338 A1 WO0062338 A1 WO 0062338A1
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WO
WIPO (PCT)
Prior art keywords
adhesive tape
resin
semiconductor chip
lead frame
sealing
Prior art date
Application number
PCT/JP1999/007387
Other languages
English (en)
French (fr)
Inventor
Yoshihisa Furuta
Yoshinori Watanabe
Original Assignee
Nitto Denko Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corporation filed Critical Nitto Denko Corporation
Priority to EP99961462A priority Critical patent/EP1094512A4/en
Publication of WO2000062338A1 publication Critical patent/WO2000062338A1/ja

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • H01L21/566Release layers for moulds, e.g. release layers, layers against residue during moulding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
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    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2924/01005Boron [B]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
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    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01067Holmium [Ho]
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    • H01L2924/01078Platinum [Pt]
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    • H01L2924/01079Gold [Au]
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    • H01L2924/01082Lead [Pb]
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    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Definitions

  • the present invention relates to a resin sealing method for a semiconductor chip and an adhesive tape for attaching a lead frame or the like used in the method.
  • semiconductor chips are bonded to lead frames, semiconductor chips are then placed in mold cavities, and the semiconductor chips are resin-sealed by transfer injection molding.
  • the contact surface needs to be considerably large, and the ratio of the area of the contact surface to the cavity space is considerably large. Therefore, the number of chips that can be sealed in one shot with the same mold size is reduced, which is disadvantageous in work efficiency.
  • the chip may be moved by the flow of the injected resin into the mold and the bonding portion may be damaged, and in order to eliminate this danger, complicated mold structure is inevitable.
  • An object of the present invention is to provide a resin sealing method for a semiconductor chip capable of improving the resin sealing efficiency of a semiconductor chip and reliably preventing breakage of a bonding portion.
  • the method of resin sealing a semiconductor chip comprises the steps of: adhering an adhesive tape to a lead frame or a film carrier tape; bonding the semiconductor chip to the frame or the carrier tape with the adhesive tape; and then sealing the semiconductor chip with a mold.
  • This is a method in which the adhesive tape is peeled off, and the adhesive tape has a heat shrinkage of 3% or less when sealing the resin.
  • the heat shrinkage rate at the time of resin sealing is 3% or less means that the tape is Thermal shrinkage in at least one of the directions is less than 3%.
  • FIG. 1A to 1E are views showing an example of a method for resin sealing a semiconductor chip according to the present invention.
  • FIG. 2 is a drawing showing the lead frame in FIGS. 1A to 1E.
  • FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 1C.
  • FIG. 1A to 1E are views showing an example of a method for resin sealing a semiconductor chip according to the present invention.
  • FIG. 1A shows a lead frame A with an adhesive tape
  • 1 is a lead frame.
  • a unit group having a large number of stitches 11 provided inside a device hole is integrated.
  • Reference numeral 2 denotes an adhesive tape adhered to the lead frame 1, and has a heat shrinkage rate at the time of resin sealing of 3% or less, preferably 2% or less, more preferably 1% or less.
  • Reference numeral 21 denotes an adhesive layer
  • reference numeral 22 denotes a substrate.
  • a semiconductor chip 3 is disposed in each device hole of a lead frame A with an adhesive tape, and adhesively fixed. Wire bonding 31 between the stitches 11 and then, as shown in FIG. 1C, the semiconductor chips 3 are housed in the cavities 41 of the mold 4 in the resin sealing step, and are resin-sealed by transfer injection molding. Thereafter, as shown in FIG. 1D, the adhesive tape is peeled off from the lead frame 1, and then the lead frame is trimmed to obtain a resin-sealed semiconductor chip shown in FIG. 1E.
  • Fig. 3 shows the contact interface between the mold and the lead frame.
  • the stitch 11 of the lead frame penetrates into the adhesive layer 21 of the adhesive tape 2, and the adhesive layer 21 and the stitch 11 become flat. Since the pressure-sensitive adhesive layer 21 is adhered to the mold 4 and the pressure-sensitive adhesive acts as a sealant, it exhibits high sealing properties. Therefore, it is necessary to make the pressure-sensitive adhesive layer With this, a sealing effect can be exhibited. Further, even when the sealing resin is filled to the depth of the side of the stitch 11, a sufficient sealing effect can be exerted by increasing the mold pressure and the adhesive force, and the sealing resin can be used properly depending on the application.
  • the heat of the mold also heats the adhesive tape, and the adhesive tape is heat shrunk. Due to the heat shrinkage of the pressure-sensitive adhesive tape, a shear stress is generated at the contact interface between the lead frame with the pressure-sensitive adhesive tape and the mold, and when the shear stress increases, there is a concern that the sealing property may be degraded due to shear slip.
  • the adhesive tape with a heat shrinkage of 3% or less, preferably 2% or less, and more preferably 1% or less at the time of resin sealing is used. Can be maintained.
  • the number of chips that can be sealed in one shot can be increased. Further, since the chip is fixed by the pressure-sensitive adhesive layer, the fixed state of the chip can be stably maintained with respect to the resin injection flow, and the bonding portion can be prevented from being damaged.
  • the adhesive strength of the adhesive tape be as high as possible from the viewpoint of sealing between the mold and the lead frame, but from the viewpoint of peeling of the adhesive tape from the lead frame after resin sealing. Is desired to be as low as possible. Therefore, the adhesive strength to the lead frame at 23 ° C after resin encapsulation is 400 gf / 20 or less, preferably SOOgf ⁇ Omm or less, and 5 gf / 20 thigh or more (under 5 gf / 20 thigh, It is preferable to use a pressure-sensitive adhesive tape (which makes it easy to peel off).
  • the heating condition at the time of the resin sealing is usually approximately 180 ° C. It goes without saying that the adhesive tape is required to have heat resistance to this temperature.
  • a heat-resistant base material capable of satisfying the above conditions, for example, a heat-resistant plastic film such as polyimide film or polyphenylene sulfide, or a glass cloth can be used. If the heating conditions during resin encapsulation are 150 ° C or less, a polyethylene terephthalate film can be used.
  • an acrylic-based pressure-sensitive adhesive, a silicone-based pressure-sensitive adhesive, or an epoxy-based pressure-sensitive adhesive can be used as long as the above conditions are satisfied. It is preferred to use Satisfies the peel force requirement If necessary, a heat-resistant filler (eg, glass beads, various inorganic fillers, heat-resistant organic fillers, etc.) can be added. It is also possible to use a foaming adhesive which foams by heating during resin sealing and has a peeling force of 400 gf / tape width of 20 or less.
  • the thickness of the supporting substrate is 5 to 250 zm, preferably 5 to 100 zm. (If it is less than 5 m, it is likely to break, tear, float, etc., and workability will be reduced. If it exceeds 25 ⁇ , a mold will be used. The efficiency of heat transfer from the resin to the resin).
  • the thickness of the pressure-sensitive adhesive layer is 2 to 100 ⁇ m, preferably 5 to 75 ⁇ m. (If the thickness is less than 2 ⁇ m, coating is difficult, and poor adhesion and floating are likely to occur. If it exceeds, the coating becomes difficult, glue protrudes on the side surface, foreign matter easily adheres, and the amount of gas generated during heating increases.
  • the pressure-sensitive adhesive layer can be appropriately cross-linked so that no adhesive residue due to cohesive failure occurs and no adhesive residue is peeled off due to interfacial destruction, and the adhesive strength is adjusted to be low.
  • an undercoat may be applied or a surface unevenness treatment, for example, a spatula treatment may be applied as necessary.
  • heat conductive particles such as boron nitride may be added to the pressure-sensitive adhesive layer.
  • the present invention can also be applied to the TAB method.
  • An adhesive tape is attached to the back side of a film carrier tape (for example, a polyimide film provided with a copper foil finger), and the film carrier tape with the adhesive tape is attached.
  • a semiconductor chip is arranged in each device hole and adhesively fixed. Au-Sn eutectic bonding is performed between the chip and a finger of a film carrier tape. Then, in a resin encapsulation process, a semiconductor is attached to each mold cavity. The chip is housed, resin-sealed by transfer injection molding, and then the film-carrying tape is trimmed to obtain a resin-sealed semiconductor chip. It can also be implemented by:
  • a platinum catalyst 0.5 part by weight is uniformly mixed with 100 parts by weight of a silicone-based adhesive, applied to a 25-m-thick polyimide film, and dried by heating at 130 ° C for 5 minutes.
  • An adhesive tape having a layer thickness of 10 ⁇ m was prepared.
  • the heat shrinkage of this adhesive tape at 200 ° C is 0.5% or less, 23.
  • the initial adhesive strength to the lead frame at ⁇ is SOgf / ⁇ O thigh, the adhesive strength after 1 hour at 200 ° C is 180gf / 20, and the adhesive strength after 5 hours at 200 ° C is 200g f / 20 there were.
  • the heat shrinkage was measured by measuring the interval between the marked lines after leaving the tape sample with a tape length of 300 thighs, a width of 19 wakes, a distance of 200 mm between the marked lines at 200 ° C for 2 hours, and returning to 23 ° C. Then, [(marker interval before shrinkage ⁇ marker interval after shrinkage) / marker interval before shrinkage] ⁇ 100 (%).
  • This adhesive tape was adhered to the same lead frame used in Comparative Example 1, sealed with a resin in the same manner as in Comparative Example 1, and then the adhesive tape was peeled off. No deformation of the lead frame was observed.
  • the adhesive tape has a heat shrinkage of 0.5% or less at 200 ° C, an initial adhesive strength to the lead frame at 23 ° C of 500gf / 20 thigh, and an adhesive strength after 1 hour at 200 ° C of 550gf.
  • Example 1 was the same as Example 1 except that the existing silicone adhesive tape (adhesive layer thickness 30 m, base material thickness 25 m) with an adhesive strength of 550 gf / 20 brain after 5 hours at 200 ° C / 20 thighs and 200 ° C was used. Resin sealing was performed in the same manner. Although the adhesive strength of the adhesive tape was higher than that of Example 1, the lead frame was slightly deformed when the adhesive tape was peeled off, but no resin leakage occurred.
  • the adhesive tape has a heat shrinkage of 2% or less at 200 ° C, an initial adhesive strength to the lead frame at 23 ° C of 220gf / 20 thigh, and an adhesive strength of 1 hour at 200 ° C for SOOgf ⁇ O.
  • Thigh the same as in Example 1 except that a silicone adhesive tape (adhesive layer thickness 10 ⁇ m, base material thickness 25zm) with an adhesive strength of 300gf / 20 after 5 hours at 200 ° C was used. After sealing with resin, the same results as in Example 1 were obtained.
  • the adhesive tape has a thermal shrinkage of 7.5% at 200 ° C s
  • the initial adhesive strength to the lead frame at 23 ° C is 700gf / 20 thigh, and the adhesive strength after one hour at 200 ° C is 750gfZ20 thigh
  • the resin sealing was carried out in the same manner as in Example 1, except that an existing silicone adhesive tape (adhesive layer thickness 30 m, base material thickness 25 m) with an adhesive strength of 750 gf / 20 mm after 5 hours at 200 ° C was used. When it stopped, resin dripping occurred. In addition, the lead frame was deformed during resin sealing. From this, it was confirmed that the adhesive tape used in the present invention had a heat shrinkage rate of 3% or less at the time of resin sealing.
  • the present invention when bonding a semiconductor chip to a lead frame or a film carrier tape and then sealing the semiconductor chip with a resin using a mold, the area of the contact interface between the lead frame or the like and the mold is reduced. Since the size can be made sufficiently small and the number of cavities can be increased accordingly, the number of sealing chips per shot can be increased and the resin sealing efficiency can be improved.
  • the quality of resin sealing can be improved by preventing the invasion of foreign matter into the stitches of the lead frame, preventing the generation of scratches, and preventing the generation of dust caused by resin leakage.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

明 細 書 半導体チップの樹脂封止方法及びリードフレーム等貼着用粘着テープ 技術分野
本発明は半導体チップの樹脂封止方法及びその方法において使用するリードフ レーム等貼着用粘着テープに関するものである。 背景技術
QFP 等のパッケージ半導体装置を製造する場合、 リードフレームに半導体チッ プをボンディングし、 次いで金型のキヤビティに半導体チップを納め、 トランス ファ一射出成形により半導体チップを樹脂封止している。
しかしながら、 金型とリードフレームとの間の接触界面からの樹脂漏れを防止 するためにその接触面をかなり広くする必要があり、 キヤビティスペースに対す るその接触面の面積の比率を相当に大きくしなければならず、 同一金型寸法のも とで 1ショッ 卜で封止できるチップ個数が少なくなり、 作業能率上不利である。 また、 金型内への注入樹脂の流れでチップが移動されてボンディング箇所が破 損される畏れがあり、 この危険性を排除するためには金型構造の複雑化が避けら れない。
本発明の目的は、 半導体チップの樹脂封止効率を高め、 しかもボンディング箇 所の破損を確実に防止できる半導体チップの樹脂封止方法を提供することにある 発明の開示
本発明に係る半導体チヅプの樹脂封止方法は、 リードフレームまたはフィルム キヤリャテープに粘着テープを貼着し、 この粘着テープ付きフレームまたはキヤ リャテープに半導体チップをボンディングし、 次いで半導体チップを金型により 樹脂封止し、 而るのち、 粘着テープを剥離する方法であり、 粘着テープに樹脂封 止時の熱収縮率が 3%以下の粘着テープを使用することを特徴とする構成である。 なお、 "樹脂封止時の熱収縮率が 3%以下" とは、 封止温度においてテープの縦横 方向の少なくともいづれかの方向で熱収縮が 3%以下ということである。 図面の簡単な説明
図 1A〜図 1 Eは、 本発明に係る半導体チップの樹脂封止方法の一例を示す図 面である。
図 2は、 図 1A〜図 1 Eにおけるリードフレームを示す図面である。
図 3は、 図 1 Cにおける I I I— I I I断面図である。 発明を実施するための最良の形態
以下、 図面を参照しつつ本発明の実施の形態について説明する。
図 1 A〜図 1 Eは本発明に係る半導体チップの樹脂封止方法の一例を示す図面 である。
図 1 Aは粘着テープ付きリードフレーム Aを示し、 1はリードフレームであり、 図 2に示すように、デバイスホールの内郭に多数本のステッチ 11を設けたュニッ ト群を一体化してある。 2はリードフレーム 1に貼着した粘着テープであり、 樹 脂封止時の熱収縮率を 3%以下、 好ましくは 2%以下、 より好ましくは 1%以下に 抑えてある。 21は粘着剤層を、 22は基材をそれぞれ示している。
本発明により樹脂封止半導体チップを製造するには、 図 1Bに示すように粘着 テープ付きリードフレーム Aの各デバイスホールに半導体チップ 3を配して粘着 固定し、このチップ 3とリードフレーム 1のステッチ 11との間をワイヤボンディ ング 31し、 次いで図 1 Cに示すように、樹脂封止工程において金型 4の各キヤビ ティ 41に半導体チップ 3を収容し、トランスファ一射出成形により樹脂封止を行 い、 而るのち、 図 1 Dに示すようにリードフレーム 1から粘着テープを剥離した うえでリードフレームをトリミングして図 1 Eに示す樹脂封止半導体チップを得 る。
図 3は、 金型とリードフレームとの接触界面を示し、 粘着テープ 2の粘着剤層 21にリードフレームのステッチ 11が食い込んで粘着剤層 21とステッチ 11とが 面—になり、ステッチ間の粘着剤層 21が金型 4に粘着しており、粘着剤がシール 剤として作用するから高いシール性を呈する。従って、粘着剤層 21を厚くするこ とによってシール効果を発揮させ得る。また、ステッチ 11の横の奥深くにまで封 止樹脂が満たされる場合でも、 金型圧力や接着力を高くすることにより充分なシ ール効果を発揮させ得、 用途により使い分けができる。
上記の樹脂封止時、 金型熱によって粘着テープも加熱され、 粘着テープが熱収 縮される。 この粘着テープの熱収縮により粘着テープ付きリードフレームと金型 との接触界面に剪断応力が発生し、 この剪断応力が大きくなると剪断すべりによ り封止性の低下が懸念されるが、本発明においては、樹脂封止時の熱収縮率が 3% 以下、好ましくは 2%以下、 更に好ましくは 1%以下、の粘着テープを使用してい るので、 樹脂封止中においても上記の高いシール性を維持できる。
従って、 金型とリードフレームとの接触界面の面積を小さくしても充分にシ一 ルでき、その接触界面の面積を小さくしてキヤビティ個数を多くすることにより、
1 ショットで封止できるチップ個数を多くできる。 また、 粘着剤層によるチヅプ の粘着固定のために、樹脂の注入流れに対しチップの固定状態を安定に維持でき、 ボンディング箇所の破損を防止できる。
上記粘着テープの粘着力は、 金型とリードフレームとの間の封止の点からはで きるだけ高くすることが望ましいが、 樹脂封止後でのリードフレームからの粘着 テープの剥離の点からはできるだけ低くすることが望まれる。 而して、 樹脂封止 後で 23°Cでのリードフレームに対する接着力が 400gf/20態以下、 好ましくは SOOgf ^Omm以下で、 5gf/20腿以上 (5gf/20腿未満では、 使用中に剥がれ易く なる) の粘着テープを使用することが好ましい。
上記樹脂封止時の加熱条件は通常ほぼ 180°Cであり、 上記粘着テープにはこの 温度に対する耐熱性が要求されることはいうまでもない。
上記粘着テープの支持基材には、 上記の諸条件を満たし得る耐熱基材、 例えば ポリイミ ドフィルム、 ポリフエ二レンスルフィ ド等の耐熱性プラスチックフィル ム、 ガラスクロス等を使用できる。樹脂封止時の加熱条件が 150°C以下であれば、 ポリエチレンテレフ夕レートフィルムの使用も可能である。
上記粘着テープの粘着剤には、 上記の諸条件を満たすものであれば、 アクリル 系粘着剤、 シリコーン系粘着剤の外、 エポキシ系等の使用も可能であるが、 耐熱 性に優れたシリコーン系を使用することが好ましい。 前記剥離力の要件を充足さ せるために必要に応じ耐熱性の充填剤 (例えば、 ガラスビーズ、 各種無機フイラ 一、 耐熱有機フイラ一等) を添加することができる。 樹脂封止時の加熱で発泡し て剥離力が 400gf /テ一プ巾 20腿以下になる発泡性粘着剤を使用することもでき る。
上記支持基材の厚みは 5〜250 zm、 好ましくは 5〜: lOO zmとされる (5 m未満 では折れや裂けや浮き等が発生し易く作業性が低下する。 25θ ίπιを越えると金型 から樹脂への熱伝達効率が低下する)。
前記粘着剤層の厚みは 2〜; I00〃m、好ましくは 5〜75〃mとされる(2〃m未満で は塗工が困難であり、 接着不良や浮きが発生し易い。 100 zmを越えると、 塗工が 困難であり、 側面に糊がはみ出し異物が付着し易くなり、 加熱時でのガス発生量 が多くなる)。
前記粘着剤層は、 凝集破壊による糊残りを生じさせることなく界面破壊で糊残 りなく剥離させるように、 また接着力を低く調整するために適宜架橋することが できる。
上記支持基材と粘着剤層との層間剥離を防止するために、 必要に応じ下塗を施 したり表面凹凸処理、 例えばスパッ夕処理を施すこともできる。
上記樹脂封止時の加熱効率を高めるために、 粘着剤層に熱伝導性粒子、 例えば チッ化ホウ素を添加することもできる。
上記半導体装置の製造中に摩擦静電気が発生するが、 静電気ショックによるチ ップの破壊が懸念される場合は、 支持体を導電材とし、 粘着剤層を導電性粒子、 例えばカーボニッケルやカーボンブラックの添加により導電性とすることができ る。
本発明は TAB方式にも適用でき、 フィルムキヤリャテープ (例えば、 ポリイミ ドフィルムに銅箔フィンガーを設けたもの) の裏面側に粘着テープを貼着し、 こ の粘着テープ付きフィルムキヤリャテープの各デバイスホールに半導体チップを 配して粘着固定し、 このチップとフィルムキヤリャテープのフィンガ一との間を Au— Sn共晶ボンディングし、 次いで、 樹脂封止工程において金型の各キヤビティ に半導体チップを収容し、 トランスファー射出成形により樹脂封止を行い、 而る のち、 フィルムキヤリャテープをトリミングして樹脂封止半導体チップを得るこ とにより実施することもできる。
以下、 実施例及び比較例を示し本発明をより詳細に説明するが、 本発明はこれ らに限定されるものではない。
比較例 1
粘着テープを貼着していないリードフレーム (Cu系, ステッチ数 100本)単体 にチップをボンディングし、金型に挟み 200°C x 20kg/cm2で樹脂封止を行ったと ころ、 樹脂漏れが発生した。
実施例 1
シリコ一ン系粘着剤 100重量部に白金触媒 0. 5重量部を均一に混合し、 これを 厚み 25 mのポリイミ ドフィルムに塗布し、 130°C x 5分にて加熱乾燥して粘着剤 層厚み 10〃mの粘着テープを作成した。
この粘着テープの 200°Cでの熱収縮率は 0.5%以下、23。〇でのリードフレームに 対する初期粘着力は SOgf/^O腿、 200°Cで 1時間後の粘着力は 180gf/20薩、 200°C で 5時間後の粘着力は 200g f/20醒であった。 なお、 熱収縮率はテープ長さ 300 腿、 幅 19醒、 標線間距離 200 mmのテ一プサンプルを 200°C、 2時間放置後、 23°C に戻した後の標線間隔を測定し、 [(収縮前の標線間隔-収縮後の標線間隔)/収縮 前の標線間隔] x lOO ( % ) として求めた。
この粘着テープを比較例 1で使用したものと同じリードフレームに貼着し、 比 較例 1と同様に樹^ ί封止し、 次いで粘着テープを剥離したところ、 樹脂滞れは無 く、 またリードフレームの変形も観られなかった。
実施例 2
粘着テープに、 200°Cでの熱収縮率が 0. 5%以下、 23°Cでのリードフレームに対 する初期粘着力が 500gf/20腿、 200°Cで 1時間後の粘着力が 550gf/20腿、 200°C で 5時間後の粘着力が 550gf/20腦の既存のシリコーン粘着テープ (粘着剤層厚 み 30〃m、基材厚み 25 m)を使用した以外、実施例 1と同様にして樹脂封止した。 粘着テープの粘着力が実施例 1に較べ高く粘着テープの剥離時リードフレーム がやや変形したが、 樹脂漏れは生じなかった。
この実施例から、 粘着テープに、 樹脂封止後での接着力が 400gf/20腿以下の ものを使用することの有利性が確認できる。 実施例 3
粘着テープに、 200°Cでの熱収縮率が 2%以下、 23°Cでのリードフレームに対す る初期粘着力が 220gf/20腿、 200°Cで 1時間後の粘着力が SOOgf ^O腿、 200°Cで 5時間後の粘着力が 300gf/20酬のシリコ一ン粘着テープ (粘着剤層厚み 10〃m、 基材厚み 25 zm) を使用した以外、 実施例 1 と同様にして樹脂封止したところ、 実施例 1と同様の結果が得られた。
比較例 2
粘着テープに、 200°Cでの熱収縮率が 7. 5%s 23°Cでのリードフレームに対す る初期粘着力が 700gf/20腿、 200°Cで 1時間後の粘着力が 750gfZ20腿、 200°Cで 5時間後の粘着力が 750gf/20mmの既存のシリコーン粘着テープ (粘着剤層厚み 30〃m、 基材厚み 25 m) を使用した以外、 実施例 1と同様にして樹脂封止したと ころ、樹脂滴れが発生した。 また、樹脂封止中にリードフレームに変形が生じた。 このことから、 本発明において粘着テープに、 樹脂封止時の熱収縮率が 3%以 下のものを使用することの意義が確認できた。 産業上の利用可能性
本発明によれば、 リードフレームまたはフィルムキヤリャテープに半導体チヅ プをボンディングし、 次いで半導体チップを金型を使用して樹脂封止する場合、 リードフレーム等と金型との接触界面の面積を充分に小さくでき、 それだけキヤ ビティ個数を多くできるから、 1 ショット当たりの封止チップ個数を多くでき、 樹脂封止効率を向上できる。
また、 樹脂封止でのボンディング箇所の破損をよく防止でき、 優れた歩留りで 樹脂封止できる。
更に、 リードフレームのステッチへの異物の侵入防止、 傷発生の防止、 樹脂漏 れに起因するダス卜の発生防止などにより樹脂封止品質を向上できる。

Claims

請 求 の 範 囲
1 . リードフレームに粘着テープを貼着し、 この粘着テープ付きフレームに半導 体チップをボンディングし、 次いで半導体チヅプを金型により樹脂封止し、 而る のち、 粘着テープを剥離する方法であり、 粘着テープの樹脂封止時の熱収縮率が
3%以下であることを特徴とする半導体チップの樹脂封止方法。
2 . 請求の範囲第 1項において、 リードフレームに代えテープキヤリャフィル ムを使用する半導体チップの樹脂封止方法。
3 . 請求の範囲第 1項 1または第 2項に記載の半導体チップの樹脂封止方法にお いて使用する粘着テープであり、 樹脂封止時の熱収縮率が 3%以下であるリード フレーム等貼着用粘着テープ。
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WO2015029871A1 (ja) * 2013-08-29 2015-03-05 三井化学東セロ株式会社 接着フィルムおよび半導体装置の製造方法
JPWO2015029871A1 (ja) * 2013-08-29 2017-03-02 三井化学東セロ株式会社 接着フィルムおよび半導体装置の製造方法
US9822284B2 (en) 2013-08-29 2017-11-21 Mitsui Chemicals Tohcello, Inc. Adhesive film and method for manufacturing semiconductor device

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JP2000294580A (ja) 2000-10-20
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KR20010052801A (ko) 2001-06-25
EP1094512A1 (en) 2001-04-25
KR100665441B1 (ko) 2007-01-04

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