CN102061136B - 树脂密封用粘合带及树脂密封型半导体装置的制造方法 - Google Patents

树脂密封用粘合带及树脂密封型半导体装置的制造方法 Download PDF

Info

Publication number
CN102061136B
CN102061136B CN201010544011.8A CN201010544011A CN102061136B CN 102061136 B CN102061136 B CN 102061136B CN 201010544011 A CN201010544011 A CN 201010544011A CN 102061136 B CN102061136 B CN 102061136B
Authority
CN
China
Prior art keywords
adhesive tape
resin
self adhesive
lead frame
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010544011.8A
Other languages
English (en)
Other versions
CN102061136A (zh
Inventor
柳雄一朗
近藤广行
星野晋史
下川大辅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Publication of CN102061136A publication Critical patent/CN102061136A/zh
Application granted granted Critical
Publication of CN102061136B publication Critical patent/CN102061136B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20105—Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20106—Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/14—Layer or component removable to expose adhesive
    • Y10T428/1476—Release layer

Abstract

本发明的目的是提供能够有效防止树脂密封时的树脂漏出的树脂密封用粘合带及树脂密封型半导体装置的制造方法。其解决方法包括：用于制造树脂密封型半导体装置的树脂密封用粘合带，其具有基材层和在该基材层上层叠的粘合剂层，且所述基材层与粘合剂层的总膜厚为25～40μm；以及，树脂密封型半导体装置的制造方法，包括下述工序：将该粘合带贴附于引线框的至少一个面，在所述引线框上搭载半导体芯片，通过密封树脂密封该半导体芯片侧，在密封后剥离所述粘合带。

Description

树脂密封用粘合带及树脂密封型半导体装置的制造方法
技术领域
本发明涉及树脂密封用粘合带以及使用其的树脂密封型半导体装置的制造方法。
背景技术
近年来，在LSI安装技术中，CSP(芯片尺寸封装)技术受到了关注。在该技术中，以QFN(方形扁平无引线封装)为代表的、使引线端子纳入封装内部的形态的封装在小型化和高集成化方面特别受到关注。
在这种QFN中，能够飞跃性提高引线框每单位面积的生产率的制造方法特别受到关注。作为该方法，可列举出包括以下工序的制造方法：将多个QFN用芯片排列于引线框的裸芯片连接盘(die pad)上，在模具的模腔内用密封树脂一起密封，此后，通过切断，分割为单个的QFN结构物。
在这种一起密封多个半导体芯片的QFN的制造方法中，树脂密封时的由塑封模具夹紧的引线框区域仅仅是完全包覆封装图案区域的树脂密封区域外侧的一部分。因此封装图案区域，尤其在其中央部不能将压引线框背面以充分的压力按压在塑封模具上、非常难以防止密封树脂漏出到引线框背面侧、容易出现QFN的端子等被树脂包覆的问题。
因此，针对这种QFN的制造方法，将粘合带贴附于引线框的背面侧、通过利用该粘合带的自粘性(遮蔽)的密封效果，从而防止树脂密封时树脂漏出到引线框背面侧的制造方法是有效的。
即，在半导体芯片搭载于引线框上后或者在实施引线接合之后将耐热性粘合带贴合于引线框背面，这从处理方面来看实质上是困难的，因此，理想的是，首先，将耐热性粘合带贴合于引线框的背面侧，此后，经过半导体芯片的搭载和引线接合，利用密封树脂进行密封，然后剥离耐热性粘合带。
作为这种方法，已经提出了下述方法：使用具有厚度10μm以下的粘合剂层的耐热性粘合带，在防止树脂漏出的同时，实施引线接合等一系列工序(例如专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2002-184801号公报
发明内容
发明要解决的问题
然而，在现有的半导体装置的制造方法中，在利用密封树脂的密封工序中，根据贴合有耐热性粘合带的引线框的精度、模具，尤其下模具的设计，有可能在它们之间存在间隙。
在这种情况下，由于在引线框与下模具之间产生的间隙，在耐热性粘合带与引线框架之间发生树脂漏出，或者，不能很好地夹紧塑封部分的外周部而发生树脂漏出。
本发明是鉴于所述问题而做出的，其目的是提供能够在树脂密封时有效防止树脂漏出的树脂密封用粘合带以及使用该粘合带的树脂密封型半导体装置的制造方法。
用于解决问题的方案
本发明的用于制造树脂密封型半导体装置的树脂密封用粘合带特征在于具有基材层和在该基材层上层叠的粘合剂层，所述基材层与粘合剂层的总膜厚为25～40μm。
这种粘合带的所述粘合剂层的厚度优选为2μm～25μm。
该粘合带优选用于在将搭载于引线框表面的半导体芯片进行树脂密封时贴附于所述引线框的至少一个面上，且在密封之后剥离。
所述粘合剂层优选仅层叠在所述基材层的一个面上。
该粘合带还优选具有与粘合剂层接触的剥离片，且该剥离片在剥离角度为90±15°时的剥离强度为1.5N/50mm宽度以下，在剥离角度为120±15°时的剥离强度为1.2N/50mm宽度以下，在剥离角度为150±15°时的剥离强度为1.0N/50mm宽度以下，或者在剥离角度为180+0°～180-15°时的剥离强度为1.0N/50mm宽度以下。
本发明的树脂密封型半导体装置的制造方法特征在于包括下述工序：将所述的粘合带贴附于引线框的至少一个面；在所述引线框上搭载半导体芯片；通过密封树脂密封该半导体芯片侧，在密封后剥离所述粘合带。
在这种方法中，优选的是，用具有0.8～2.0Pa·s粘度的密封树脂来进行所述密封、或者通过在160～190℃的树脂注射温度下的注射成型来进行所述密封、或者通过在150～220kN的树脂注射压力下的注射成型来进行所述密封、和/或在3～7kN的模具夹紧压力下进行所述密封。
进而优选的是，从粘合带的贴附到树脂密封为止的期间从引线框侧隔着该引线框对粘合带进行辐射线照射。
发明的效果
根据本发明的树脂密封用粘合带，可有效地防止树脂密封时的树脂漏出。
另外，根据本发明的树脂密封型半导体装置的制造方法，通过利用上述粘合带，可有效地防止树脂密封时的树脂漏出，可谋求提高成品率。
附图说明
图1为表示本发明的半导体装置的制造方法的一个例子的工序图。
图2为表示本发明的半导体装置的制造方法中使用的引线框的一个例子的平面图(a)和重要部位放大图(b)。
附图标记说明
10   封装图案区域
11   引线框
11a  开口
11b  引线端子
11c  裸芯片连接盘
15   半导体芯片
16   接合线
17   密封树脂
20   粘合带
21   半导体装置
具体实施方式
本发明的树脂密封用粘合带至少具有基材层和在其上层叠的粘合剂层。该树脂密封用粘合带在半导体制造方法的树脂密封时使用。
(基材层)
对基材层没有特别限制，只要是由本领域中作为粘合带的基材使用的材料构成，可以使用任何材料。
尤其，基材层适宜是对通常的半导体制造方法中使用的加热，特别是树脂密封时的加热具有耐性的层。例如，可列举出具有170℃以上、200℃以上、250℃以上、300℃以上的耐热性的层。由于一般赋予密封树脂175℃左右的温度，因此优选在这种温度条件下不发生显著的基材层收缩或基材本身的破坏等的物质。
另外，从其他观点来看，基材层优选在300℃以下不具有玻璃化转变温度(Tg)。通过使用这种基材层，在半导体装置的制造工序中，即使在超过基材层的Tg来加热粘合带时，也能防止粘合带的变形等，防止引线框的翘曲等。由此，可以可靠地实现树脂密封时的遮蔽功能，提高引线接合的成功率。
在此处，Tg是根据ASTM D696通过热机械分析装置(例如SIS Technology制造，TMA/SS 600)所求出的值。即，在19.6mN的负荷下，将基材层的样品(例如厚度1mm×宽度4mm)以10℃/分钟的速度从室温升温，通过热分析装置测定厚度方向的热膨胀量，绘制热膨胀量与温度的关系图，在预计为玻璃化转变温度的点前后的曲线上引出切线，由这些切线的交点求出的值。因此，在300℃以下没有玻璃化转变温度是指不能分辨出预计为玻璃化转变温度的温度，几乎看不出切线的交点。
从防止伴随该基材层收缩的引线框翘曲的观点来看，基材层在180℃下加热3小时之后的热收缩率优选为0.40％以下。
在这里，热收缩率表示将5cm见方的基材层在180℃加热3小时时相对于加热前尺寸(5cm)100％的尺寸变化的比例(％)。该热收缩率可以通过市售的投影机(Mitutoyo Corporation制投影机，PJ-H3000F)来测定。
基材层例如可以通过聚萘二甲酸乙二醇酯(PEN)、聚醚砜(PES)、聚醚酰亚胺(PEI)、聚砜(PSF)、聚苯硫醚(PPS)、聚醚醚酮(PEEK)、聚芳酯(PAR)、芳族聚酰胺、聚酰亚胺、聚对苯二甲酸乙二醇酯(PET)等树脂、液晶聚合物(LCP)、铝等金属箔、玻璃布等形成。尤其，线性热膨胀系数1.0×10-5～3.0×10-5/K左右的聚酰亚胺材料由于加工性、处理性高、耐热性和强度优异，因此是最优选的材料之一。
另外，基材层可以是单层结构，也可以是层叠结构。
从粘合带的处理性(例如难以发生粘合带的折断或破裂)的观点来看，基材层的厚度优选为5μm以上，更优选为10μm以上，另一方面，从粘合带的剥离性的观点来看，基材层的厚度优选为35μm以下，更优选为30μm以下。
另外，从其他观点来看，由于贴附本发明的粘合带的引线框如下所述是金属材料，因此线性热膨胀系数一般为1.8～1.9×10-5/K左右。因此，如果粘合带的线性热膨胀系数与引线框的线性热膨胀系数相差太大，在二者贴合的状态下加热时，由二者的热膨胀的差异产生变形，结果，在粘合带上造成皱纹、剥落。因此，构成粘合带基材层的线性热膨胀系数适于是接近引线框材料的1.0×10-5～3.0×10-5/K左右，优选是1.5×10-5～2.5×10-5/K以下。
在此处，线性热膨胀系数是根据ASTM D696通过TMA(热机械分析)测定的值。
(粘合剂层)
粘合剂层只要具有耐热性，就可以通过本领域常用的粘合剂来形成。该粘合剂可以是压敏型、热敏型、感光型的任何一种，但适合是通过能量射线照射而固化的类型的粘合剂。由此，在使用后，可以容易地从被加工物上剥离。另外，粘合剂层可以在基材层的两侧形成，但适宜仅仅在单侧上形成。
作为构成粘合剂层的粘合剂，例如，可列举出丙烯酸系粘合剂、硅酮系粘合剂、橡胶系粘合剂、环氧系粘合剂等各种粘合剂。
丙烯酸系粘合剂例如可列举出由含有(甲基)丙烯酸烷基酯的单体共聚合获得的丙烯酸系共聚物构成的粘合剂。另外，在本说明书中，(甲基)丙烯酸烷基酯是指丙烯酸烷基酯和/或甲基丙烯酸烷基酯。
作为(甲基)丙烯酸烷基酯，可列举出(甲基)丙烯酸甲酯、(甲基)丙烯酸乙酯、(甲基)丙烯酸丁酯、(甲基)丙烯酸异戊酯、(甲基)丙烯酸正己酯、(甲基)丙烯酸2-乙基己酯、(甲基)丙烯酸异辛酯、(甲基)丙烯酸异壬酯、(甲基)丙烯酸癸酯、(甲基)丙烯酸十二烷基酯等。其中，丙烯酸与(甲基)丙烯酸2-乙基己酯的共聚合、(甲基)丙烯酸甲酯和/或(甲基)丙烯酸乙酯与丙烯酸、(甲基)丙烯酸2-乙基己酯的共聚合是优选的。
粘合剂层，尤其是含有丙烯酸系粘合剂的粘合剂层中可以含有交联剂。
作为交联剂，例如可列举出异氰酸酯系交联剂、环氧系交联剂、氮杂环丙烷化合物、螯合物系交联剂等。
对交联剂的含量没有特别限制，相对于100重量份丙烯酸系聚合物，适合为0.1～15重量份，优选为0.5～10重量份。通过在该范围内使用交联剂，可以适度设定粘合剂层的粘弹性，且可以确保粘合剂层对导电性图案或密封树脂的适度粘合力。因此，在剥离粘合带时不会发生剥离或损坏密封树脂或者发生粘合剂层的一部分附着于导电性图案或密封树脂。此外，可以抑制粘合剂层的过度固化。
粘合剂层中可以进一步添加增塑剂、颜料、染料、抗老化剂、抗静电剂、弹性模量等用于改善粘合剂层物性的填充剂等本领域中通常使用的各种添加剂。
从粘合剂层与引线框的充分粘合力的观点来看，粘合剂层的厚度优选为2μm以上，更优选为3μm以上，进一步优选为4μm以上，另一方面，从充分的引线接合性的观点来看，优选为35μm以下，更优选为30μm以下。
(粘合带的制造)
粘合剂层可以通过配制粘合剂成分，使其在基材层上涂布/干燥来形成。作为粘合剂成分的涂布方法，可以采用棒涂布机涂布、气刀涂布、凹版涂布、反向式凹版涂布、逆辊涂布、模唇涂布、模头涂布、浸渍涂布、胶印印刷、胶版印刷、丝网印刷等各种方法。另外，还可以采用在剥离衬垫上形成粘合剂层之后再将其贴合到基材薄膜上的方法等。
(粘合带)
本发明的粘合带的基材层与粘合剂层的总膜厚适合为25～40μm，优选为25～35μm。
通过设定这种范围的总膜厚，如下所述，在贴合于引线框时，可以防止皱纹的发生，同时例如与在模具上夹持贴合有该粘合带的引线框时的夹紧压力等保持平衡，可以有效地防止树脂从模具之间漏出。
另外，从对引线框架充分(例如，工序中不发生带剥离)粘合力的观点来看，本发明的粘合带在粘合带对引线框架的剥离角度为180°时粘合力适宜为0.01N/19mm宽度以上，优选为0.05N/19mm宽度以上，更优选为0.10N/19mm宽度以上，进一步优选为0.15N/19mm宽度以上。另一方面，从防止粘合带粘附失败时粘合带剥离中的残胶和防止裸芯片连接盘部等变形的观点来看，该粘合力适宜为10.0N/19mm宽度以下，优选为6.0N/19mm宽度以下，更优选为5.0N/19mm宽度以下，进一步优选为4.0N/19mm宽度以下。
粘合带在密封树脂上的剥离角度为180°时的粘合力适宜为约10.0N/19mm宽度以下，优选为约6.0N/19mm宽度以下，更优选为约5.0N/19mm宽度以下。
在此处，该粘合力是在测定温度23±2℃、剥离角度180°、剥离速度为300mm/分钟(根据JIS Z0237)的条件下通过从引线框剥离来测定时的值。这种测定可以通过市售的测定装置(岛津制作所制造，Autograph AG-X等)来进行。
另一方面，首先，粘合带贴附于引线框上，可在任意阶段从引线框剥离，在具有太强的粘合力时，不仅剥离变得困难，而且，根据情况，由于用于剥离的应力，导致塑封的树脂的剥离、破损。因此，在抑制密封树脂溢出的粘合力以上的强粘合当然是不优选的。例如，在半导体装置的制造工序中，根据JISC2107的25℃时粘合力适宜为5～10000N/m左右。进而，在200℃下加热1小时之后的对引线框架的粘合力适宜为约0.05N/19mm宽度以上，优选为约0.1N/19mm宽度。另外，该粘合力适宜为约6N/19mm宽度以下，优选为约4N/19mm宽度以下。特别是约0.05～6.0N/19mm宽度，约0.1～4.0N/19mm宽度，进一步优选为约0.1～2.0N/19mm宽度。
本发明的粘合带优选进一步具有剥离片。剥离片是为了保护粘合剂层而与粘合剂层接触形成的薄片。该粘合带根据粘合剂层中含有的粘合剂的种类等优选具有特定值的剥离强度。剥离强度根据剥离粘合带时的角度可以适宜调整。例如，优选满足以下所示的剥离角度时的剥离强度的至少一个。这里的剥离强度是在测定温度23±2℃、剥离角度75～195°、优选90～180°、剥离速度300mm/分钟(根据TMA0001法)的条件下通过从本发明的粘合带上剥离而测定的值。
剥离片在剥离角度为90±15°时的剥离强度适宜为约1.5N/50mm宽度以下、约1.0N/50mm宽度以下、约0.5N/50mm宽度以下、约0.3N/50mm宽度以下、约0.2N/50mm宽度以下。
剥离片在剥离角度为120±15°时的剥离强度适宜为约1.2N/50mm宽度以下、约1.0N/50mm宽度以下、约0.8N/50mm宽度以下、约0.6N/50mm宽度以下、约0.3N/50mm宽度以下。
剥离片在剥离角度为150±15°时的剥离强度适宜为约1.0N/50mm宽度以下、约0.8N/50mm宽度以下、约0.6N/50mm宽度以下、约0.5N/50mm宽度以下、约0.3N/50mm宽度以下、约0.2N/50mm宽度以下。
剥离片在剥离角度为180+0°～180-15°时的剥离强度适宜为约1.0N/50mm宽度以下、约0.8N/50mm宽度以下、约0.6N/50mm宽度以下、约0.5N/50mm宽度以下、约0.3N/50mm宽度以下、约0.2N/50mm宽度以下。
通过将剥离强度设定在这种范围内，即使在使用通常利用的带贴附装置等的情况下，也不需要用于剥离该剥离片的过度的剥离强度，不发生粘合带的皱纹、贴附位置的偏移，可以防止在粘合带上负载有残留应力。由此，可以抑制引线框的翘曲、密封树脂的树脂漏出等发生。
剥离片包括使用本领域常用的材料，以单层或多层结构形成的剥离基材，所述材料例如是聚氯乙烯、聚偏二氯乙烯、聚对苯二甲酸乙二醇酯等聚酯、聚酰亚胺、聚醚醚酮；低密度聚乙烯、线性聚乙烯、中密度聚乙烯、高密度聚乙烯、超低密度聚乙烯、无规共聚合聚丙烯、嵌段共聚合聚丙烯、均聚丙烯、聚丁烯、聚甲基戊烯等聚烯烃；聚氨酯、乙烯-醋酸乙烯酯共聚物、离聚物树脂、乙烯-(甲基)丙烯酸共聚物、乙烯-(甲基)丙烯酸酯(无规、交替)共聚物、乙烯-丁烯共聚物、乙烯-己烯共聚物、氟树脂、纤维素系树脂以及它们的交联体等聚合物等。
另外，剥离片适宜为在剥离基材的至少与粘合剂层接触的面上实施脱模处理，使得实质上不与粘合剂层粘接。脱模处理可以采用本领域公知的方法和材料进行。例如可列举出利用硅酮树脂的处理、利用氟树脂的脱模处理等。具体而言，可例举出Cerapeel系列(Toray Advanced Film Co.，Ltd.)的轻剥离等级和中剥离等级等。
(树脂密封型半导体装置的制造方法以及防止树脂漏出方法)
本发明的树脂密封型半导体装置中，粘合带尤其在树脂密封时使用。即，本发明的粘合带用于在对搭载在引线框表面的半导体芯片进行树脂密封时，贴附在引线框的至少一个面，例如背面(与搭载有半导体芯片的面相反一侧的面，以下相同)，并在密封后剥离。
本发明的制造方法中，包含下述工序：
在引线框的至少一面例如背面上贴合本发明的粘合带，
在该裸芯片连接盘表面上搭载半导体芯片，
通过密封树脂密封半导体芯片侧，
在密封后剥离粘合带。
进一步，从粘合带的贴合到剥离之间，可以任意含有下述工序等：
进行等离子体处理的工序，
树脂密封后的密封树脂的切断工序，
从引线框侧隔着该引线框对粘合带进行辐射线照射的工序，
在裸芯片连接盘上搭载半导体芯片之后的接线工序。
在贴附粘合带之后、搭载芯片前/后、树脂密封前/后、的任何工序中进行至少一次辐射线照射。
这种半导体装置的制造方法中，本发明的粘合带主要用于防止树脂漏出。另外，粘合带可以贴合在引线框中用树脂密封的区域以外的表面和背面的所有区域。
具体而言，首先，如图1(a)所示，将本发明的粘合带20贴附在引线框11的一个面，即背面。
引线框11通常由Cu系材料(Cu-Fe-P等)、Fe系材料(Fe-Ni等)等的金属板形成。另外，可以雕刻QFN的端子图案。尤其优选在引线框内的电接点部分(与下述半导体芯片的连接部分)用银、镍、钯、金等包覆(镀敷)。引线框11的厚度通常被列举为100～300μm左右。
为了在后续切断工序中容易切开，引线框11优选由多个规定的配置图案(例如各QFN的配置图案)排列而成。具体而言，如图2(a)和(b)所示，在引线框11上，封装图案区域10以矩阵状排列而成的产品称为矩阵QFN、MAP-QFN等，是最优选的产品之一。
引线框11通常具有裸芯片连接盘11c和引线端子11b。它们可以分离地设置，但优选如图2(b)所示通过由邻接的多个开口11a规定的多个引线端子11b、在开口11a的中央排列的裸芯片连接盘11c、和任选的在开口11a的4个角处支撑裸芯片连接盘11c的连接杆(tie bar)11d一体化形成。另外，裸芯片连接盘11c和引线端子11b等可以设置为实现散热等其他功能。
粘合带20对引线框架11的贴附至少适合在引线框11的封装图案区域10上、在引线框11的比封装图案区域10外侧的区域，即包括了被树脂密封的树脂密封区域外侧四周的区域、或者在封装图案区域10和包括了封装图案区域10外侧四周的区域上进行。
在包括了树脂密封区域外侧四周的区域上贴附本发明的粘合带时，不仅在引线框的背面，还可以在表面贴附。在封装图案区域10和包括了封装图案区域10外侧四周的区域上进行贴附时，优选仅仅在引线框的背面进行贴附。
引线框架11由于通常在端边附近具有用于确定树脂密封时的位置的定位销用孔(例如图2(a)的13)，因此优选在不堵塞该孔的区域贴附粘合带。另外，由于在引线框11的纵向上配置有多个封装图案区域10，因此，优选连续地跨越这些的多个区域来贴附粘合带20。
接着，如图1(b)所示，在引线框11表面(没有贴附粘合带20的面)搭载半导体芯片15。
通常，如上所述，由于引线框架11设置有用于固定半导体芯片15的称为裸芯片连接盘11c的固定区域，因此半导体芯片15搭载在裸芯片连接盘11c上。
半导体芯片15往裸芯片连接盘11c上的搭载例如利用使用导电性糊19、粘接带、粘接剂(例如热固化性粘接剂)等各种方法。在使用导电性糊剂、粘接剂等搭载时，通常在150～200℃左右的温度下加热固化30分钟～90分钟左右。
在此处，为了使粘合带的粘合剂层固化且实现高弹性化，可以从引线框11侧对所得引线框11进行辐射线照射。
辐射线的种类没有特别限制，可以根据粘合剂层中含有的粘合剂种类而适当调整。例如，可列举出紫外线、电子束等。其中，紫外线是优选的。对紫外线的波长没有特别限制，适合选择用于普通光聚合的波长，例如250～400nm的波长的紫外线是适合的。
作为照射紫外线的方法，适合利用迄今公知的紫外线发生装置。具体而言，可列举出采用放电灯方式(弧光灯)、闪光方式、激光方式等的紫外线装置。其中，从工业生产方法的观点来看，利用放电灯方式的紫外线装置是优选的，此外，从辐射线的照射效率的观点来看，利用高压汞灯、金属卤化物灯的紫外线装置是优选的。
辐射线的照射量例如适宜为能够提高粘合剂层中含有的聚合引发剂等的效率的程度。具体而言，可列举出10～1000mJ/cm2左右，优选为50～600mJ/cm2左右。这是因为能够实现粘合剂层的适度硬化。
该辐射线照射可以在将粘合带20贴附于引线框11之后、在下述引线接合之前的任何阶段进行。例如，优选在从粘合带的贴附到树脂密封为止的期间进行。这是因为，在将粘合带20贴附于引线框11之前进行时，由于粘合剂层的固化导致粘合力降低，变得难以贴附。另外，有可能导致下述密封树脂的漏出。
接着，任选地，如图1(c)所示，将半导体芯片15表面的电极焊盘(electrode pad)(未图示)与引线框11进行引线接合(接线)。
引线接合通过接合线16例如金线或铝线等来进行。通常，在加热至150～250℃的状态下，通过并用超声波产生的振动能量和加压产生的压接能量来进行。此时，通过将贴附于引线框的粘合带面抽真空，可以可靠地固定于加热块(heat block)。
另外，作为半导体芯片15，在进行面向下(face down)实装时，能够适宜进行再流工序。
接着，对密封树脂17进行注射成型。即，将引线框11夹在上下模具(未图示)中，注射密封树脂17(例如环氧树脂等)，将半导体芯片15密封。从容易注射的观点考虑，此时的密封树脂例如具有约0.8～2.0Pa·s、优选约1.0～2.0Pa·s的粘度。另外，树脂粘度可以通过市售的树脂粘度测定装置(例如粘度计、毛细管流变仪等)测定。另外，密封优选在160～190℃的注射温度下进行注射。进而，树脂密封适宜在150～220kN的注射压力下来注射成型。此时的密封可以是单面密封和双面密封中的任何一种。在双面密封的情况下，如上所述，适合在包括了引线框的树脂密封区域外侧四周的区域上、引线框的表面和/或背面贴附粘合带。在封装图案区域10和包括了封装图案区域10外侧四周的区域的单面贴附粘合带时，优选进行单面密封。在进行这种密封时，尤其优选可以适宜地使用本发明的粘合带。
半导体芯片的密封是为了保护搭载在引线框11上的半导体芯片15和接合线16而进行。例如，使用环氧系树脂等，通过注射成型，在模具中成型的方法是代表性方法。在该情况下，优选使用具有多个模腔的由上模具和下模具构成的模具，将多个半导体芯片同时密封。此时的模具的夹紧压力适宜约为例如3～7kN。通常，树脂密封时的加热温度为170～180℃左右，在该温度下固化数分钟之后，进一步进行数小时的塑封后固化(postmold cure)。
此后，如图1(d)所示，从模具中取出包括密封树脂17的引线框11。
如图1(e)所示，剥离贴附于引线框11背面的粘合带20。
密封后的粘合带20的剥离优选在上述塑封后固化之前进行。
此后，如图1(f)所示，可以将包含密封树脂17的引线框11分割为各个半导体芯片15，获得半导体装置21。
各个半导体芯片15的分割可以使用切块机等旋转切断刃来进行。
另外，在半导体芯片的树脂密封时，本发明的粘合带只要在引线框的一个面，优选背面贴附即可，关于所述图1(a)～图1(c)的工序，可以在搭载半导体芯片之后贴附粘合带，也可以在将半导体芯片引线接合之后贴附粘合带。其中，优选按照上述的图1(a)～图1(c)的顺序进行。另外，根据半导体芯片的结构，可以不进行引线接合。
以下详细说明使用本发明的树脂密封用粘合带以及使用该粘合带的树脂密封型半导体装置的制造方法。
另外，在以下实施例中，除非另有规定，份和％等为质量基准。
实施例1
使用25μm厚的聚酰亚胺薄膜(DU PONT-TORAY CO.，LTD.，Kapton 100H，线性热膨胀系数2.7×10-5/K，Tg：402℃)作为基材层，在该基材层的单面涂布添加有2.5份铂催化剂的100份硅酮系粘合剂(Dow Corning Toray Silicone Co.，Ltd.制造，SD4584)，使之干燥，制作具有厚度约6μm的粘合剂层的耐热性粘合带(总膜厚：31μm)。
实施例2
使用12.5μm厚的聚酰亚胺薄膜(DU PONT-TORAY CO.，LTD.，Kapton 50H，线性热膨胀系数2.7×10-5/K，Tg：402℃)作为基材层，与实施例1同样地，使用硅酮系粘合剂，制作在该基材层的单面具有厚度约18μm的粘合剂层的耐热性粘合带(总膜厚：30.5μm)。
实施例3
使用25μm厚的聚对苯二甲酸乙二醇酯薄膜(TORAY制Lumirror S10，热线性热膨胀系数1.2×10-5/K，Tg：67℃)作为基材层。使用在100份的由丙烯酸丁酯-丙烯酸乙酯-丙烯酸(丙烯酸丁酯/丙烯酸乙酯/丙烯酸＝70份/30份/4份)构成的聚合物中均一混合3份异氰酸酯系交联剂(商品名“CORONATEL”日本聚氨酯工业株式会社制造)、2份环氧系交联剂(商品名“TETRAD-C”三菱瓦斯化学(株))和甲苯而形成的粘合剂，制作在该基材层的单面具有厚度约10μm的粘合剂层的耐热性粘合带(总膜厚：35μm)。
比较例1
除了将粘合剂层的厚度设定为约35μm以外，与实施例1同样地，制作耐热性粘合带(总膜厚：60μm)。
比较例2
使用12.5μm厚的聚酰亚胺薄膜(DU PONT-TORAY CO.，LTD.，Kapton 50H，线性热膨胀系数2.7×10-5/K，Tg：402℃)作为基材层，制作使与实施例3同样的丙烯酸系粘合剂为约6μm厚度的耐热性粘合带(总膜厚：18.5μm)。
<性能评价>
使用带层压装置PL-55TRM(日东电工制造)，将实施例和比较例中制造的粘合带以在常温下密合的方式平稳地贴合到铜制引线框背面的外焊盘(outer pad)侧，其中所述引线框是在端子部实施了镀银的单边16Pin型的QFN排列成4个×4个的铜制引线框。另外，该引线框的裸芯片连接盘使用搭载有半导体芯片、通过金线进行引线接合的裸芯片连接盘。
接着，通过环氧系密封树脂(日东电工制HC-300，例如，树脂粘度：0.8～2.0Pa·s)，使用塑封机(TOWA制Model-Y-Serise)，在175℃、预热40秒、注射时间11.5秒、注射压力为150～220kN、固化时间120秒的条件下塑封。此时，模具的夹紧压力约为3～7kN。
然后，剥离引线框背面贴附的粘合带。
进一步在175℃下进行3小时左右的塑封后固化，从而使树脂充分固化，然后，通过切块机切断，获得单个的QFN型半导体装置。这样，在制造QFN型半导体装置之后，目测确认树脂漏出。
结果，在实施例1～3中，确认没有树脂漏出。另一方面，在比较例1中，60％以上的端子上确认有树脂漏出。另外，比较例2中，80％以上的端子上确认有树脂漏出。
另外，对于实施例1～3的粘合带分别贴合厚度50μm的PET隔片(三菱化学聚酯薄膜公司制造，MRS-50S)和厚度38μm的PET隔片(Toray Advanced Film Co.，Ltd.制造，#38Cerapeel)，制作粘合带。
测定这些粘合带在剥离角度90°、120°、150°或180°时的隔片剥离力(单位：N/50mm)。隔片剥离力的评价结果在表1和表2中示出。
表1
表2
从表1和表2可以看出，粘合力均为0.3N/50mm宽度以下。另外，使用这些粘合带时，均没有发现粘合带的贴合位置的偏移、引线框的翘曲、密封树脂的漏出。
产业上的可利用性
本发明的粘合带可以广泛用于半导体装置的制造方法。

Claims (10)

1.一种用于制造树脂密封型半导体装置的树脂密封用粘合带，其特征在于，所述树脂密封用粘合带具有基材层、在该基材层上层叠的硅酮系粘合剂构成的粘合剂层，和与粘合剂层接触的剥离片，所述基材层与粘合剂层的总膜厚为25～40μm，所述剥离片
在剥离角度为90±15°时的剥离强度为1.0N/50mm宽度以下、
在剥离角度为120±15°时的剥离强度为1.0N/50mm宽度以下、
在剥离角度为150±15°时的剥离强度为0.8N/50mm宽度以下、或者
在剥离角度为180+0°～180-15°时的剥离强度为0.8N/50mm宽度以下，以及
所述基材层的线性热膨胀系数是1.0×10-5～3.0×10-5/K，
所述粘合带对引线框架的剥离角度为180°时粘合力为0.01N/19mm宽度以上，且为10.0N/19mm宽度以下。
2.根据权利要求1所述的粘合带，其中，所述粘合剂层的厚度为2μm～25μm。
3.根据权利要求1或2所述的粘合带，所述粘合带用于在将搭载于引线框表面的半导体芯片进行树脂密封时贴附于所述引线框的至少一个面上且在密封之后剥离该粘合带。
4.根据权利要求1或2所述的粘合带，其中，所述粘合剂层仅层叠在所述基材层的一个面上。
5.一种树脂密封型半导体装置的制造方法，其特征在于，所述制造方法包括下述工序：
将根据权利要求1～4中任一项所述的粘合带贴附于引线框的至少一个面；
在所述引线框上搭载半导体芯片；
通过密封树脂密封该半导体芯片侧；
在密封后剥离所述粘合带。
6.根据权利要求5所述的树脂密封型半导体装置的制造方法，其通过具有0.8～2.0Pa·s的粘度的密封树脂来进行所述密封。
7.根据权利要求5或6所述的树脂密封型半导体装置的制造方法，其通过在160～190℃的树脂注射温度下的注射成型来进行所述密封。
8.根据权利要求5或6所述的树脂密封型半导体装置的制造方法，其通过在150～220kN的树脂注射压力下的注射成型来进行所述密封。
9.根据权利要求5或6所述的树脂密封型半导体装置的制造方法，其在3～7kN的模具夹紧压力下进行所述密封。
10.根据权利要求5或6所述的树脂密封型半导体装置的制造方法，进一步在从粘合带的贴附到树脂密封为止的期间，从引线框侧隔着该引线框对粘合带进行辐射线照射。
CN201010544011.8A 2009-11-12 2010-11-11 树脂密封用粘合带及树脂密封型半导体装置的制造方法 Active CN102061136B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-258633 2009-11-12
JP2009258633 2009-11-12

Publications (2)

Publication Number Publication Date
CN102061136A CN102061136A (zh) 2011-05-18
CN102061136B true CN102061136B (zh) 2015-03-04

Family

ID=43974465

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010544011.8A Active CN102061136B (zh) 2009-11-12 2010-11-11 树脂密封用粘合带及树脂密封型半导体装置的制造方法

Country Status (4)

Country Link
US (1) US20110111563A1 (zh)
JP (1) JP5551568B2 (zh)
CN (1) CN102061136B (zh)
TW (1) TWI505416B (zh)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8936966B2 (en) 2012-02-08 2015-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
CN102074541B (zh) * 2010-11-26 2014-09-03 天水华天科技股份有限公司 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法
EP2658680B1 (en) 2010-12-31 2020-12-09 Saint-Gobain Ceramics & Plastics, Inc. Abrasive articles comprising abrasive particles having particular shapes and methods of forming such articles
JP5759729B2 (ja) * 2011-01-20 2015-08-05 日東電工株式会社 半導体部品の表面保護用粘着テープ
US8986409B2 (en) 2011-06-30 2015-03-24 Saint-Gobain Ceramics & Plastics, Inc. Abrasive articles including abrasive particles of silicon nitride
EP2726248B1 (en) 2011-06-30 2019-06-19 Saint-Gobain Ceramics & Plastics, Inc. Liquid phase sintered silicon carbide abrasive particles
TWI469231B (zh) * 2011-09-09 2015-01-11 Dawning Leading Technology Inc 晶片封裝結構之製造方法
BR112014007089A2 (pt) 2011-09-26 2017-03-28 Saint-Gobain Ceram & Plastics Inc artigos abrasivos incluindo materiais de partículas abrasivas, abrasivos revestidos usando os materiais de partículas abrasivas e os métodos de formação
JP5865044B2 (ja) * 2011-12-07 2016-02-17 リンテック株式会社 保護膜形成層付ダイシングシートおよびチップの製造方法
JP5865045B2 (ja) * 2011-12-07 2016-02-17 リンテック株式会社 保護膜形成層付ダイシングシートおよびチップの製造方法
JP5903502B2 (ja) 2011-12-30 2016-04-13 サン−ゴバン セラミックス アンド プラスティクス，インコーポレイティド 成形研磨粒子を備える粒子材料
RU2014130167A (ru) 2011-12-30 2016-02-27 Сэнт-Гобэйн Керамикс Энд Пластикс Инк. Получение формованных абразивных частиц
JP6033886B2 (ja) 2011-12-30 2016-11-30 サン−ゴバン セラミックス アンド プラスティクス，インコーポレイティド 成形研磨粒子および同粒子を形成する方法
US8840696B2 (en) 2012-01-10 2014-09-23 Saint-Gobain Ceramics & Plastics, Inc. Abrasive particles having particular shapes and methods of forming such particles
RU2602581C2 (ru) 2012-01-10 2016-11-20 Сэнт - Гобэйн Керамикс Энд Пластик,Инк. Абразивные частицы, имеющие сложные формы, и способы их формования
CN103305138A (zh) * 2012-03-08 2013-09-18 日东电工株式会社 树脂密封用压敏粘合带和树脂密封型半导体器件的生产方法
WO2013149209A1 (en) 2012-03-30 2013-10-03 Saint-Gobain Abrasives, Inc. Abrasive products having fibrillated fibers
KR101813466B1 (ko) 2012-05-23 2017-12-29 생-고뱅 세라믹스 앤드 플라스틱스, 인코포레이티드 형상화 연마입자들 및 이의 형성방법
KR20150023034A (ko) 2012-06-29 2015-03-04 생-고뱅 세라믹스 앤드 플라스틱스, 인코포레이티드 특정 형상을 가지는 연마입자들 및 이러한 입자들 형성방법
KR101736085B1 (ko) 2012-10-15 2017-05-16 생-고뱅 어브레이시브즈, 인코포레이티드 특정한 형태들을 가진 연마 입자들 및 이러한 입자들을 형성하는 방법들
US9074119B2 (en) 2012-12-31 2015-07-07 Saint-Gobain Ceramics & Plastics, Inc. Particulate materials and methods of forming same
MX2015013831A (es) 2013-03-29 2016-03-01 Saint Gobain Abrasives Inc Particulas abrasivas con formas particulares y metodos para elaborar las particulas.
TW201502263A (zh) 2013-06-28 2015-01-16 Saint Gobain Ceramics 包含成形研磨粒子之研磨物品
JP2016538149A (ja) 2013-09-30 2016-12-08 サン−ゴバン セラミックス アンド プラスティクス，インコーポレイティド 形状化研磨粒子及び形状化研磨粒子を形成する方法
KR101681360B1 (ko) * 2013-11-25 2016-11-30 삼성전기주식회사 전자부품 패키지의 제조방법
WO2015102992A1 (en) 2013-12-31 2015-07-09 Saint-Gobain Abrasives, Inc. Abrasive article including shaped abrasive particles
US9771507B2 (en) 2014-01-31 2017-09-26 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particle including dopant material and method of forming same
CA2945493C (en) 2014-04-14 2020-08-04 Saint-Gobain Ceramics & Plastics, Inc. Abrasive article including shaped abrasive particles
CN106457522B (zh) 2014-04-14 2020-03-24 圣戈本陶瓷及塑料股份有限公司 包括成形磨粒的研磨制品
US9902045B2 (en) 2014-05-30 2018-02-27 Saint-Gobain Abrasives, Inc. Method of using an abrasive article including shaped abrasive particles
JP6455127B2 (ja) * 2014-12-18 2019-01-23 三菱ケミカル株式会社 透明フィルムの製造方法
US9707529B2 (en) 2014-12-23 2017-07-18 Saint-Gobain Ceramics & Plastics, Inc. Composite shaped abrasive particles and method of forming same
US9914864B2 (en) 2014-12-23 2018-03-13 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particles and method of forming same
US9676981B2 (en) 2014-12-24 2017-06-13 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particle fractions and method of forming same
WO2016161157A1 (en) 2015-03-31 2016-10-06 Saint-Gobain Abrasives, Inc. Fixed abrasive articles and methods of forming same
TWI634200B (zh) 2015-03-31 2018-09-01 聖高拜磨料有限公司 固定磨料物品及其形成方法
CA3118239A1 (en) 2015-06-11 2016-12-15 Saint-Gobain Ceramics & Plastics, Inc. Abrasive article including shaped abrasive particles
US10727085B2 (en) * 2015-12-30 2020-07-28 Texas Instruments Incorporated Printed adhesion deposition to mitigate integrated circuit package delamination
SI3455321T1 (sl) 2016-05-10 2022-10-28 Saint-Gobain Ceramics & Plastics, Inc. Metode oblikovanja abrazivnih delcev
KR102313436B1 (ko) 2016-05-10 2021-10-19 생-고뱅 세라믹스 앤드 플라스틱스, 인코포레이티드 연마 입자들 및 그 형성 방법
US9972509B2 (en) * 2016-09-12 2018-05-15 Win Semiconductors Corp. Anti-plasma adhesive tape and manufacturing method
US11230653B2 (en) 2016-09-29 2022-01-25 Saint-Gobain Abrasives, Inc. Fixed abrasive articles and methods of forming same
WO2018101090A1 (ja) * 2016-11-29 2018-06-07 リンテック株式会社 両面粘着シートおよび半導体装置の製造方法
US10759024B2 (en) 2017-01-31 2020-09-01 Saint-Gobain Ceramics & Plastics, Inc. Abrasive article including shaped abrasive particles
US10563105B2 (en) 2017-01-31 2020-02-18 Saint-Gobain Ceramics & Plastics, Inc. Abrasive article including shaped abrasive particles
US10865148B2 (en) 2017-06-21 2020-12-15 Saint-Gobain Ceramics & Plastics, Inc. Particulate materials and methods of forming same
US9909035B1 (en) * 2017-09-29 2018-03-06 Mayapple Baby Llc Mountable articles, dual-adhesive-adhesive tape and mounting methods using them
CN108831839B (zh) * 2018-06-22 2020-03-24 苏州震坤科技有限公司 一种去除半导体塑封制程中所产生毛边的方法
KR20210089191A (ko) * 2018-11-09 2021-07-15 쇼와덴코머티리얼즈가부시끼가이샤 반도체 장치 제조용 가보호 필름, 릴체, 및 반도체 장치를 제조하는 방법
WO2021133901A1 (en) 2019-12-27 2021-07-01 Saint-Gobain Ceramics & Plastics, Inc. Abrasive articles and methods of forming same
KR20220160593A (ko) * 2020-03-30 2022-12-06 닛토덴코 가부시키가이샤 광 반도체 소자 밀봉용 시트

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1118608A (zh) * 1993-03-01 1996-03-13 美国3M公司 具有硬性边缘的遮蔽带和衬垫的遮蔽方法
CN1829783A (zh) * 2003-08-06 2006-09-06 3M创新有限公司 耐热遮蔽带
CN101454416A (zh) * 2006-04-04 2009-06-10 伊士曼化工公司 压敏粘合剂(psa)层压材料
CN101553547A (zh) * 2006-12-11 2009-10-07 3M创新有限公司 耐热遮蔽带及其用法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164203A (en) * 1985-02-13 1992-11-17 Mitsubishi Denki Kabushiki Kaisha Plastic molding device for a semiconductor element
JP2003086614A (ja) * 2001-09-12 2003-03-20 Hitachi Chem Co Ltd 半導体装置の製造方法、半導体用接着・剥離フィルム、これを用いたリードフレーム及び半導体装置
JP3849978B2 (ja) * 2002-06-10 2006-11-22 日東電工株式会社 半導体装置の製造方法及びこれに用いる耐熱性粘着テープ
JP4566568B2 (ja) * 2004-01-23 2010-10-20 日東電工株式会社 半導体装置の製造方法及びこれに用いる耐熱性粘着テープ
JP4679896B2 (ja) * 2004-12-20 2011-05-11 リンテック株式会社 半導体用耐熱性粘着テープ
JP4437442B2 (ja) * 2004-12-27 2010-03-24 日東電工株式会社 剥離ライナーおよび該剥離ライナーが用いられた両面粘着テープ又はシート
JP4654062B2 (ja) * 2005-03-30 2011-03-16 株式会社巴川製紙所 半導体装置製造用接着シート及び半導体装置の製造方法
JP4538398B2 (ja) * 2005-10-31 2010-09-08 株式会社巴川製紙所 半導体装置製造用接着シート及び半導体装置の製造方法
DE102005024431B4 (de) * 2005-05-24 2009-08-06 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterbauteilen unter Verwendung einer Trägerplatte mit doppelseitig klebender Klebstofffolie
JP5077980B2 (ja) * 2006-03-06 2012-11-21 日東電工株式会社 半導体装置の製造方法
US7595226B2 (en) * 2007-08-29 2009-09-29 Freescale Semiconductor, Inc. Method of packaging an integrated circuit die
US8841782B2 (en) * 2008-08-14 2014-09-23 Stats Chippac Ltd. Integrated circuit package system with mold gate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1118608A (zh) * 1993-03-01 1996-03-13 美国3M公司 具有硬性边缘的遮蔽带和衬垫的遮蔽方法
CN1829783A (zh) * 2003-08-06 2006-09-06 3M创新有限公司 耐热遮蔽带
CN101454416A (zh) * 2006-04-04 2009-06-10 伊士曼化工公司 压敏粘合剂(psa)层压材料
CN101553547A (zh) * 2006-12-11 2009-10-07 3M创新有限公司 耐热遮蔽带及其用法

Also Published As

Publication number Publication date
TW201125083A (en) 2011-07-16
CN102061136A (zh) 2011-05-18
JP5551568B2 (ja) 2014-07-16
TWI505416B (zh) 2015-10-21
US20110111563A1 (en) 2011-05-12
JP2011124558A (ja) 2011-06-23

Similar Documents

Publication Publication Date Title
CN102061136B (zh) 树脂密封用粘合带及树脂密封型半导体装置的制造方法
US7235888B2 (en) Method for manufacturing semiconductor device, adhesive sheet for use therein and semiconductor device
US7741161B2 (en) Method of making integrated circuit package with transparent encapsulant
CN203300631U (zh) 半导体器件
TWI281220B (en) Method for manufacturing semiconductor device and heat-resistant pressure-sensitive adhesive tape for use therein
TW200816420A (en) Sensor-type package structure and fabrication method thereof
KR20150117653A (ko) 반도체 소자용 봉지 시트, 반도체 장치 및 반도체 장치의 제조 방법
CN101186792A (zh) 半导体装置制造用耐热性胶粘带
JP5548077B2 (ja) 樹脂封止用粘着テープ及び樹脂封止型半導体装置の製造方法
JP5612403B2 (ja) 樹脂封止用粘着テープ及び樹脂封止型半導体装置の製造方法
KR20020021171A (ko) 리드 프레임 적층물 및 반도체 부품의 제조 방법
JP5077980B2 (ja) 半導体装置の製造方法
KR101763852B1 (ko) Qfn 반도체 패키지, 이의 제조방법 및 qfn 반도체 패키지 제조용 마스크 시트
JP2006318999A (ja) 半導体装置製造用接着フィルム
CN103305138A (zh) 树脂密封用压敏粘合带和树脂密封型半导体器件的生产方法
JP5588950B2 (ja) 耐熱性粘着テープ
JP2004186323A (ja) 半導体装置の製造方法及びこれに用いる耐熱性粘着テープ
US20130237017A1 (en) Pressure-sensitive adhesive tape for resin encapsulation and method for producing resin encapsulation type semiconductor device
WO2012099159A1 (ja) 半導体パッケージ製造工程用耐熱性粘着テープ
KR101923736B1 (ko) 수지 봉지용 점착 테이프 및 수지 봉지형 반도체 장치의 제조방법
JP2008189858A (ja) 感圧性粘着テープ
EP2636712A1 (en) Pressure-sensitive adhesive tape for resin encapsulation and method for producing resin encapsulation type semiconductor device
JP2002110884A (ja) リードフレーム積層物
KR102032767B1 (ko) Qfn 반도체 패키지, 이의 제조방법 및 qfn 반도체 패키지 제조용 마스크 시트
JP4526714B2 (ja) リードフレーム積層物および半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant