TW457602B - Flip chip metallization - Google Patents

Flip chip metallization Download PDF

Info

Publication number
TW457602B
TW457602B TW088114052A TW88114052A TW457602B TW 457602 B TW457602 B TW 457602B TW 088114052 A TW088114052 A TW 088114052A TW 88114052 A TW88114052 A TW 88114052A TW 457602 B TW457602 B TW 457602B
Authority
TW
Taiwan
Prior art keywords
metal layer
aluminum
patent application
copper
scope
Prior art date
Application number
TW088114052A
Other languages
English (en)
Inventor
Yinon Degani
Jeffrey Alan Gregus
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Application granted granted Critical
Publication of TW457602B publication Critical patent/TW457602B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

457 6 0 2 附件一：第88114052號專利申請案 中文說明書修正頁 民國90年8月呈
五、發明説明（1 ) 發明背景 I____ f請先閲讀背面之注意事項再填寫本頁} 用於電性接觸元件之封裝以及將其安裝在如印刷電路 板基底之焊接凸塊內接上的技術已廣泛的用於電子裝置的 製造產業》內接基底包括多種電子裝置的支持件，如矽及 陶瓷基底。爲了方便參考起見，在此將以通稱的印刷電路 板來表示此一支持件0 元件的封裝的形態既小且輕，並可利用焊接凸塊的精 細圖樣安裝在電路板上。一般而言，焊接凸塊或接觸墊以 鏡列的方式，形成在印刷電路板及元件封裝上，當適當的 放置元件.封裝時，印刷電路扳及元件封裝上的焊接凸塊或 焊墊相互的對齊。此技術用於倒裝片的技術中，其中元件 封裝之I c晶片的表面提供有接合的焊墊及凸塊，且I C 晶片係以倒置的方式安裝在印刷電路板上。 經濟部智葸財產局員工消費合作社印製 焊接凸塊於組裝前，形成在I / 0接觸墊的陣列上。 爲了利於局部的或者選擇性的將焊錫施加至接觸墊的陣列 上，接觸墊的表面需爲可沾附焊錫的*用於積體電路板或 卡的一般金屬內接線路系鋁製的材質》然而嘗試過直接焊 接至鋁金屬的技術後，一般均認爲鋁並非理想的焊接材料 。因此，在工業界的實務上，一般是施加一層金屬覆層至 鋁接觸墊上。此被覆一般稱之爲下凸塊金屬化技術（under bump metallization, UBM)。 用於U B M技術的金屬或合金必須相當完整的黏附在 鋁材上，且可沾附一般的焊錫等焊料，並具有很高的導電 性。一種符合此一需求的結構係鉻銅合金。首先，沈積鉻 -4 - 本紙浪尺度適用中.國國家揉準（CNS ) A4规格（210X 297公釐） 457602 Α7 Β7 五、發明說明（2 ) 金屬以黏附於鋁材上，接著將銅施加在鉻金屬上以提供 可沾附焊料的表面。鉻金屬可相當完好的黏附在多種金屬 以及有機及無機材料上。據此，其可完整的黏附至I C製 程中常見的 S i 02，SINCAPS,polymide， 附至銅或鋁的金屬上。因此 > 直接將銅薄 可溶至熔融的焊料內，且隨之焊料會從鉻 。爲了確保焊料及U B Μ間的界面整合性 材問使用鉻及銅的複合材料或合金層。 雖然此U Β Μ覆層的效果不錯，並成 界，然而此種多層被覆會增加I C封裝操 等介電材料或黏 層覆在鉻金屬上 杂屬層脫溼乾化 ，一般在銘及銅 功的使用於工業 作的複雜度及成 本。且此方式亦使系統增加一層新的金屬程序（鉻）。從 Β Μ被覆的材料 獲得更加的結果 相容性及及簡化程序的觀點，如果用於U 相同於被焊接的基材，亦即銅及鋁，則可 請ι 先 閲 讀 背 S} 之 注 意 事 項 % 1ί裝 本 . 頁 訂 ▲ 經濟部智慧財產局員工消費合作社印製 發明總結 本發明提供一種新而簡單的UBM，其僅使用鋁及銅 金屬。薄鋁層提供在I C的鋁接合位置上，並直接將一較 薄的銅金屬層黏附至鋁金屜層上•雖然就習知技術而言， 直接將銅接合至鋁金屬上並不易實施，但如果能適當的處 理鋁材的表面，則以濺鍍沈積製成便能輕易的實施該接合 〇接著，便可利用習知的方式將銅層焊接至下·-個內連接 層上。新的U Β Μ可用於任何包括表面安裝的內連接配置 中’並非常適合於倒裝片的組裝。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -5- 457602 Α7 Β7 五、發明說明（4 2 8 4 1 4 2 4 3 4 4 4 7 4 5 6 7 穿孔 導線 3 3及3 4接地內接 I C基底 氧化層 鋁接合位置 覆蓋層 下凸塊金屬化 基底 氧化層 覆層 鋁接合位置 下凸塊金屬化 銅金屬層 融刻光軍 焊接凸塊 先閱讀rvs-之注意事項"4寫本頁) 詳細描述 參考圖 印刷電路線 經濟部智慧財產局員工消費合作社印製 顯示一印刷電路板1 1的切開部位 > 其屮 將4 χ6焊接凸塊1 4與外側的I / 〇接觸 墊1 3陣列內接。圖中顯示一 ΰ金位置1 5 ，用以安裝倒 裝片的元件。依據組裝的尺寸及各種元件的大小，整個電 路板可包含許多倒裝片的安裝位置。在圖1的實施例中’ 倒裝片封裝1 5之外緣將近4 χ7 m m，而4 χ6的焊接凸塊 本紙張尺度適用令國國家標準（CNS) A4規格（21C X 297公釐〉 457602 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明p ) 1 4陣列則稍小一些。1 6標示一電容器。圖1的印刷電 路板係用於單內線記憶體模組（S I Μ Μ )，然而，此技 術及發明係涵括了焊錫安裝裝置的較廣領域，並應用於前 述的其他內接基底。
參考圖2，一凹槽式晶片（recessed-chip)模組包括 I C晶片2 1及中間的內接基底（I I S ) 22。I IS 可以是任何適當的材料|如環氧樹脂或陶瓷，但較佳的係 矽材料。晶片2 1以倒裝片的方式藉由內接2 3接合至 ί I S 1肉接2 3通常是焊錫，但亦可爲其他的導電金屬 如導電環氧樹脂等。用於倒裝片接合的技術並非本發明的 一部份，其接合可使用如焊接凸塊、球接合或導爾環氧樹 脂等。此I I S 22接著以焊料或導電環氧樹脂I/O 內接，倒裝地接合在印刷線路板（P W Β ) 2 4上。在凹 槽式的晶片M C Μ中，P W Β 2 4提供有凹部2 5 ，使 得晶片2 1可內凹於P W Β的下表面。如圖2所示’凹部 可延仲穿過P W Β的厚度方向，或僅部分的延仲。在所示 的配置中，P W Β爲單層板，並具有雙側的印刷電路11其 亦可爲多層P W Β。P W β可內接至系統印刷線路板上（ 未示）。P W Β的切除部位說明了所示的P W Β僅爲整· _ P W Β的一小部位，且整個p w β可容納許多的I 1 S S
Q IIS 2 2可以爲主勤裝置，如方形的封裝1站具 漸4窗 有大的I / 〇接合位置陣列’以方形或矩形的规劃’ . ‘. 1}\\ 於基底的周圍。替代的1 1 s可以是被動的內接基底’ 本紙張尺度適用中國國家標準<CNS)A4規格（2〗0 * 297公楚）
---------I I I < * I I-----訂---------線 C靖先閱讚背面乏注意事項為填寫本頁) 457602
五、發明説明（6 ) 矽，且具有單側或雙側的印刷電路。在圖2的內接配置中 錫球2 6安置於.PWB 1 4上的接合墊上，且接合墊經 由導線2 7而內接，導線2 7通過穿孔2 8而延伸，並經 過PWB底部的導線2 9而通置另一個接觸位置（未示） 。如果PWB上焊有另一片電路板，或是在PWB製作有 線接合，則另一個接觸位置可以是另一個接合墊。替代的 ，例如，如果PWB爲插裝式電路板，接觸位置可以是插 槽式內接。爲了達到所述的目的，內接26、27、28 及29爲電源內接，且包括31 、32、33及34的類 似內接爲接地內接。其他未顯示的I /〇接線爲習知者。 圖3顯示更詳細的I C晶片接合位置圖。此圖亦可表 示其他的內接基底，其在接合位置上具有鋁金屬。圖3中 ，1C基底4 1具有氧化層4 2及形成在氧化層窗口內的 鋁接合位置4 3。覆蓋層4 4爲聚醯亞胺或SINC APS。熟悉 相關技術之人應可了解，此圖並未按比例繪製。接合位置 4 3可以是內層金屬內接或是一基底，如源極汲極窗，的 接觸部。下部的半導體結構並非本發明的重點’因此不加 以顯示。.本發明的目的’在於以U B Μ覆層覆蓋鋁接合位 置4 3的表面，接著安置錫球或凸塊。據此，選擇性地施 加UMB 47至接觸區43上。 ； 習知的U Β Μ常是利用添加程序來施加1如提離光罩 (lift-off mask)的程序。然而，由於去除程序較簡單’並 提供較小的外型，而具有較佳的尺寸控制。本發明之 U BM的優點在於可由去除程序選擇性的施加’亦即’覆 ^^^^1 ^^^^1 am ^^^^1 m^i I (請先閲讀背面'之注意事項再填寫本頁) 、?τ 丨線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中固國家橾準（CNS>A4说格（2丨0乂297公釐.） -9- 4 57 60 2 A7 B7 五、發明說明《) 蓋沈積、微影蝕刻等製成° 本發明之覆有υ Β Μ的結構係由循序的濺鍍鋁及銅金 屬層來獲得。以下參考圖4 - 6將對此程序作一描述。 圖4中，顯示部分的基底5 1 ，並顯示有氧化層5 2 '覆層5 3及鋁接合位置5 4。此爲組裝倒裝片之前’ I C晶片封裝的一般結構。在施加U Β Μ層後，鋁接 觸部的表面先進行輕微的飩刻，或是藉由後濺鍍’以確保 鋁沈積的黏附。接著從鋁靶漉鍍來實施鋁υ Β Μ層5 5的 沈積°此層的厚度1合併有1 c上的鋁接觸墊厚度’應爲 ◦ . 5 — 2 . 0微米。目前I c技術的的鋁內接層厚度一 般小於0.5微米。而沈積的鋁金屬層約爲0·1至2微 米°參考圖5，接著直接將U B Μ的銅金屬層5 6 鍍至 鋁金屬層上。在不切斷真空的其情況下1直接於相同的製 置內依序的實施上述的沈稹是最有效的方式·否則’如果 以分離的裝置進行沈積，或將真空切斷’鋁層須再以後m 鍍的程序來移除本身的氧化層。因此，在較佳的實施例中 ，金屬層在包含有鋁靶及銅靶的濺鍍裝置內濺鍍u較佳的 ，此程序可由包含有鋁沈積站及銅沈積站的群組式裝置來 實施。並外，只要在沈積銅金屬層之前，適當的保護及淸 洗鋁金屬層的表面，亦可使用其他的金屬沈積技術’如蒸 鍍。 銅金屬層5 6較佳的具有0 · 5 0 - 2微米的厚度。 銅金屬層可沾附一般焊接凸塊的焊錫材料°此外銅與丨旱料 的共熔點較低，且在焊接溫度下，銅金屬層的表面會m於 請- 先 閱 讀 背· ϊι 之 注 t 事 項 再- 填 寫 本 頁 裝 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用ΐ國國家標準（CNS)A4規格（210 X 297公釐） -10 - 457 602
f 經濟部智慧財產局員工消費合作社印製 焊料內，而形成物理及電性的接合。即使所有的銅均溶於 焊錫的錫層內，由於鋁層的表面不會氧化，因此焊錫仍會 乾化而接合到鋁金屬層上。 如圖6所示，施以蝕刻光罩5 7以罩住焊料凸塊區。 蝕刻光罩較佳的是習知的光阻，且係藉由將光阻旋轉被覆 (spinning )於表層並以適當的反應性輻射來製作出光阻的 圖案。圖6顯示顯影後的光阻。以可使用其他的光罩技術 ，如氧化物硬式光罩。此外，亦可使用其他的微影製程， 如e —光束或X —射線。 將光.罩置放後，以習知的蝕刻溶液蝕刻銅金屬層5 6 及沈積的鋁金屬層5 5。銅金屬可由如氯化鐵、硫酸及鉻 酸甲或硫酸及過氧化氫的混合物來蝕刻。鋁金屬則可由稀 釋的H F或P A E的蝕刻溶劑來加以蝕刻。圖’7顯示蝕刻 後的結果。參考圖8 ，光阻5 7被移除|並以習知的方式 將焊接凸塊或錫球5 8加至UBM上。 以下的例子用來說明本發明的功效。 例子 金屬層5 5及5 6的沈積係以濺鍍薄膜公司（ Sputtered Film Inc)的 Endeavor cluster;設備所實施。在沈 積之前，將晶圓在1 0 5 °C下烘烤1小時，並將晶圓放入 裝置的匣具組件內。在群阻設備的蝕刻站中|以中度的乾 式蝕刻將晶圓預洗。蝕刻的條件爲3 5 0 W，1 2 0秒1 並通以6 s c cm的A r氣體。接著將晶圓移至鋁金屬的 本紙浪尺度逍用中困國家標準（CNS ) A4规格（210X 297公ϋΰ - Π - (請先Μ讀背面之注意事項再填寫本頁) -裝· -e .-線_ 457602 A7 B7 五、發明說明（10 ) 表丄 I II III Sn 5 63 95 Pb ^ 95 37 0 Sb _ 0 0 5 (請先閱讀背面之注意事項再填寫本頁) 利用此U B Μ焊接的I C元件可符合嚴格的測試及 ί C性能標準。 對於熟悉相關技術之人應可發現：如果IC製程提供 足夠厚度的鋁接合位置，則可去除鋁金屬層5 5的沈積。 因此，在本發明的實施中，由I C製程所產生之位於接合 位圄上的最後金屬層，或金屬墊可具有小於0 . 5 的 厚度'在此例中，僅需在沈積銅金屬前，將鋁金屬表面上 的氧化層移除。此程序可使用上述的乾式預洗。 經濟部智慧財產局員工消費合作社印製 鋁金屬層的預洗步驟是相當重要的程序，其中此鋁金 屬層在實施本發明的步驟前已暴露於外界空氣中較佳的 是將此層的表面進行乾式蝕刻，亦即，後濺鍍或R 1 E以 提供潔淨的鋁金屬表面來進一步的沈積銅金屬°至少從峩 而移除1 0 0 Angstroms，且較佳的是移除4 ◦ Q Angstroms ，而獲得期望的表面條件。爲了達成本發明的S的’此一 表面稱作初生表面。當在离空裝置中沈積鋁金屬層時’亦 提供-·-初生表面。 如上所述，上述程序的優點在於除去程序的使用1亦 即，可利用光罩及蝕刻來賞施U B Μ。其他已知的U B Μ 除去程序，如美國專利申請號第0 8 / 8_ 2 5 ’ 9 2 3 ’ 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） -13 - 457602 Α7 Β7 五、發明說喷〇1 ) 中請於〇 4 / 0 2 / 9 8。在此程序中，鉻金屬被用於 ϋ β μ中。用來將鉻金屬層圖案化的蝕刻劑侵蝕鋁金屬層 °因此，如果實施U Β Μ的表面含有暴露的鋁接合位置， 程序將會不理想。在一些封裝的應用中，此種情形更爲明 顯’如晶片-上-晶片的情形，其中，第二層晶片，亦即 ’支撐第一晶片的晶片，至少部分地線接合至下一層。此 晶片需耍U Β Μ接觸墊或鋁金屬墊。可先決定兩種內接形 式的鋁金屬墊，接者以上述的技術，簡單的將接收U Β Μ 的鋁金屬墊選擇性地以銅金屬被覆。在此情形下，線接合 位置之鋁金屬層的厚度至少須1 · 0微米爲佳，使得線接 合位置可承受U Β Μ的蝕刻程序。一般的鋁蝕刻步驟係可 加以控制，而能使其厚度達到上述的結果。 本發明之多種其他的改良將可由熟悉相關技術之人思 及。所有來自此說明書之具體技術的衍生係依據本發明的 原理及其等效物，藉此而開發出的技術將落在本發明及其 申請專利範圍內。 --------III — — --------訂·------1 ~ 線 I . 一. ^ (請先間讀背面-之注意事項再填寫本頁) 經濟部智慧財產局負工消費合作社印製 -14 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮）

Claims (1)

  1. 457802 附件二：第88114052號專利申請案 中文申請專利範圍修正本民國9〇年8月呈 六、申請專利範圍 1 . 一種將1C晶片接合至支持基底的製程，該1C 晶片具有鋁接合位置，包括步驟： (請先閱讀背面之注意事項再填窝本頁) a ·將1C晶片置放於真空室內， 中》(V. b .在該鋁接合的位置上提供一初生的鋁表面，· c ·在該初生的鋁表面上沈積一銅金屬層， d .將該銅金屬層焊接至該支持基底上。 2 .如申請專利範圍第1項的製程‘，其中銅金屬層係藉 由在I C晶片上沈積一覆蓋層來選擇性的施加至該初生的 鋁金屬表面，以光罩罩住部分該覆蓋層而留下部分暴露的 該覆蓋層.，並蝕刻該暴露的覆蓋層。 3 .如申請專利範圍第1項的製程，其中該初生的鋁金 屬表面係由乾式蝕刻該鋁接合位置的表面來提供。 4 _如申請專利範圍第3項的製程，其中乾式蝕刻該鋁 金屬層表面及沈積該銅金屬層的步驟係在不切斷真空的情 形下，於相..同的裝置中實施。 5 .如申請專利範圍第1項的製程，其中藉由在真空裝 經濟部智慧財產局員工消費合作杜印製 置中沈積該鋁金屬層，而提供初生的鋁金屬表面，且在不 切斷真空的情形下，於相同的裝置中將該銅金屬層沈積於 該鋁金屬層的表面。 胃 6 .如申請專利範圍第4項的製程λ.其中鋁金屬層具有 至少0 . 5 y m的厚度。 7 .如申請專利範圍第6項的製程，其中銅金屬層具有 至少0 . 5 y m的厚度。 8 .如申請專利範圍第5項的製程，其中鋁金屬層具有 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公梦） 457602 A8 BS C8 D8 六、申請專利靶圍 至少〇.5vm的厚度。 (請先聞讀背面-之注意事項再填寫本頁) 9 .如申請專利範圍第8項的製程，其中銅金屬層具有 至少〇.的厚度。 1 0 . —·種將I C晶片接合至支持基底的製程，該I c 晶片具有鋁接合位置，包括步驟： a .將I C晶片置放於真空室內， b .在該濺鍍裝置內建立一真空，i不切斷該真空： 1 在該鋁接合位置上沈積一鋁金屬層， 1 i .在該鋁金屬層上沈積一銅金屬層。 1 1 ，如申請專利範圍第1 0項的製程，其中藉由施加 光阻至該銅金屬層，而在該鋁金屬層及該銅金屬層上製作 圖案，在該光阻上製作圖案以暴露出該銅金屬層部分，並 將該銅金屬層部分及其下部的鋁金屬層蝕刻去除。 1 2 .如申請專利範圍第1 1項的製程，其中鋁金屬層 具有至少0 . 5 μιη的厚度，且銅金屬層具有至少〇 . 5 # m的厚度。 13. —種積體電路封裝，包括： 經濟部智慧財產局員工消費合作社印製 a .接附於一支持基底上的一積體電路晶片， b ·該I C晶片上的至少一鋁接合位ί， c .直接施加至該鋁接合位置上的_金屬層，及 d .自該銅金屬層至該支持基底的一焊料內接。 1 4 .如申請專利範圍第1 3項的積體電路封裝，其中 鋁金屬層具有至少0.5的厚度。 1 5 .如申請專利範圍第1 3項的積體電路封裝，其中 -2- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 457602 AS B8 C8 D8 、申請專利範圍 銅金屬層具有至少0.5的厚度》 (請先M讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐)
TW088114052A 1998-10-14 1999-08-17 Flip chip metallization TW457602B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/172,467 US6130141A (en) 1998-10-14 1998-10-14 Flip chip metallization

Publications (1)

Publication Number Publication Date
TW457602B true TW457602B (en) 2001-10-01

Family

ID=22627814

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088114052A TW457602B (en) 1998-10-14 1999-08-17 Flip chip metallization

Country Status (7)

Country Link
US (2) US6130141A (zh)
EP (1) EP0994507B1 (zh)
JP (1) JP3554685B2 (zh)
KR (1) KR100654823B1 (zh)
DE (1) DE69918631T2 (zh)
SG (1) SG93844A1 (zh)
TW (1) TW457602B (zh)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649533B1 (en) * 1999-05-05 2003-11-18 Advanced Micro Devices, Inc. Method and apparatus for forming an under bump metallurgy layer
US6544880B1 (en) * 1999-06-14 2003-04-08 Micron Technology, Inc. Method of improving copper interconnects of semiconductor devices for bonding
US6570251B1 (en) * 1999-09-02 2003-05-27 Micron Technology, Inc. Under bump metalization pad and solder bump connections
US6335226B1 (en) * 2000-02-09 2002-01-01 Texas Instruments Incorporated Digital signal processor/known good die packaging using rerouted existing package for test and burn-in carriers
KR100640576B1 (ko) * 2000-12-26 2006-10-31 삼성전자주식회사 유비엠의 형성방법 및 그에 의해 형성된 반도체 소자
TW508987B (en) * 2001-07-27 2002-11-01 Phoenix Prec Technology Corp Method of forming electroplated solder on organic printed circuit board
US6602775B1 (en) 2001-08-16 2003-08-05 Taiwan Semiconductor Manufacturing Company Method to improve reliability for flip-chip device for limiting pad design
US6756294B1 (en) * 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
US6930032B2 (en) * 2002-05-14 2005-08-16 Freescale Semiconductor, Inc. Under bump metallurgy structural design for high reliability bumped packages
US6596619B1 (en) 2002-05-17 2003-07-22 Taiwan Semiconductor Manufacturing Company Method for fabricating an under bump metallization structure
DE10238816B4 (de) * 2002-08-23 2008-01-10 Qimonda Ag Verfahren zur Herstellung von Anschlussbereichen einer integrierten Schaltung und integrierte Schaltung mit Anschlussbereichen
TW577158B (en) * 2002-11-29 2004-02-21 Advanced Semiconductor Eng Method for forming UBM pads and bumps on wafer
TWI233172B (en) * 2003-04-02 2005-05-21 Siliconware Precision Industries Co Ltd Non-leaded semiconductor package and method of fabricating the same
CN100426481C (zh) * 2003-04-15 2008-10-15 富士通株式会社 半导体装置及其制造方法
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7091124B2 (en) 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
WO2005059957A2 (en) * 2003-12-12 2005-06-30 Great Wall Semiconductor Corporation Metal interconnect system and method for direct die attachment
TWI254995B (en) * 2004-01-30 2006-05-11 Phoenix Prec Technology Corp Presolder structure formed on semiconductor package substrate and method for fabricating the same
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7429494B2 (en) * 2004-08-24 2008-09-30 Micron Technology, Inc. Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers
US7425499B2 (en) 2004-08-24 2008-09-16 Micron Technology, Inc. Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
SG120200A1 (en) 2004-08-27 2006-03-28 Micron Technology Inc Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7282433B2 (en) 2005-01-10 2007-10-16 Micron Technology, Inc. Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
US20060205200A1 (en) * 2005-03-08 2006-09-14 Dominick Richiuso Low capacitance solder bump interface structure
US7321140B2 (en) * 2005-03-11 2008-01-22 Applied Materials, Inc. Magnetron sputtered metallization of a nickel silicon alloy, especially useful as solder bump barrier
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7053490B1 (en) * 2005-07-27 2006-05-30 Semiconductor Manufacturing International (Shanghai) Corporation Planar bond pad design and method of making the same
US20070045812A1 (en) * 2005-08-31 2007-03-01 Micron Technology, Inc. Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
DE102006008261A1 (de) * 2006-02-22 2007-08-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Ätzlösung und Verfahren zur Strukturierung eines UBM-Schichtsystems
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
TW200926379A (en) * 2007-12-05 2009-06-16 Phoenix Prec Technology Corp Package substrate having electrical connecting structure and method of fabricating the same
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
CN102747326A (zh) * 2011-04-21 2012-10-24 鸿富锦精密工业（深圳）有限公司 镀膜件的制备方法及由该方法制得的镀膜件
CN102747332A (zh) * 2011-04-21 2012-10-24 鸿富锦精密工业（深圳）有限公司 镀膜件的制备方法及由该方法制得的镀膜件
CN102747333A (zh) * 2011-04-21 2012-10-24 鸿富锦精密工业（深圳）有限公司 镀膜件的制备方法及由该方法制得的镀膜件
US9768132B2 (en) * 2012-03-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US20150048502A1 (en) * 2013-08-14 2015-02-19 International Business Machines Corporation Preventing misshaped solder balls
TWI599276B (zh) * 2015-06-26 2017-09-11 矽創電子股份有限公司 電子元件與製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2095904B (en) * 1981-03-23 1985-11-27 Gen Electric Semiconductor device with built-up low resistance contact and laterally conducting second contact
JPH0344035A (ja) * 1989-07-11 1991-02-25 Seiko Instr Inc バンプ電極を有する半導体装置及びその実装方法
US5567981A (en) * 1993-03-31 1996-10-22 Intel Corporation Bonding pad structure having an interposed rigid layer
US5480835A (en) * 1993-05-06 1996-01-02 Motorola, Inc. Electrical interconnect and method for forming the same
KR950004464A (ko) * 1993-07-15 1995-02-18 김광호 칩 범프의 제조방법
US5773359A (en) * 1995-12-26 1998-06-30 Motorola, Inc. Interconnect system and method of fabrication
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
US5904859A (en) * 1997-04-02 1999-05-18 Lucent Technologies Inc. Flip chip metallization
US5985694A (en) * 1997-09-29 1999-11-16 Motorola, Inc. Semiconductor die bumping method utilizing vacuum stencil

Also Published As

Publication number Publication date
US6130141A (en) 2000-10-10
EP0994507A2 (en) 2000-04-19
DE69918631T2 (de) 2005-08-11
EP0994507A3 (en) 2000-08-16
DE69918631D1 (de) 2004-08-19
JP3554685B2 (ja) 2004-08-18
KR20000028968A (ko) 2000-05-25
JP2000124265A (ja) 2000-04-28
EP0994507B1 (en) 2004-07-14
KR100654823B1 (ko) 2006-12-08
SG93844A1 (en) 2003-01-21
US6597069B1 (en) 2003-07-22

Similar Documents

Publication Publication Date Title
TW457602B (en) Flip chip metallization
TW445554B (en) Flip chip bump bonding
US6940169B2 (en) Torch bump
US5904859A (en) Flip chip metallization
EP0411165B1 (en) Method of forming of an integrated circuit chip packaging structure
US5413964A (en) Photo-definable template for semiconductor chip alignment
EP0939436B1 (en) Manufacture of flip-chip devices
JP3224772B2 (ja) はんだマスクを含むフレキシブル薄膜ボール・グリッド・アレイ
USRE49286E1 (en) Method of making flip chip
JP2000349198A (ja) チップサイズパッケージ用インターポーザ及びその製造方法と中間部材
US6429046B1 (en) Flip chip device and method of manufacture
USRE48422E1 (en) Method of making flip chip
US4965700A (en) Thin film package for mixed bonding of chips
TWI235472B (en) A method of forming an integrated circuit substrate
JP3085283B2 (ja) 電子部品と基板との接続装置及びその接続方法
JPH03218644A (ja) 回路基板の接続構造
WO2000057469A1 (fr) Structure et procédé de montage de semi-conducteur
US7335591B2 (en) Method for forming three-dimensional structures on a substrate
JP2001148393A (ja) バンプの形成方法、半導体装置及びその製造方法、回路基板並びに電子機器
JP4938346B2 (ja) 半導体装置およびその製造方法
TWI286845B (en) Bumps and method for fabricating the same
JPH01307237A (ja) 薄い可撓性基板構造体
KR20020054886A (ko) 플립 칩의 범프 하부 다층 금속막의 식각액
JPH08162458A (ja) 電子部品の接続構造及び接続方法
JPH01128549A (ja) 半田バンプの製造方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent