1286845. 九、發明說明： 【發明所屬之技術領域】 本發明係提供一種形成鮮接凸塊的方、去 【先前技術】 覆晶接合(fHP_ehip)技術是目前廣為利用的電子構 仏。不同於傳統封裝技術的是，在覆晶接合技術中， =再是將銲墊經由打金線(wire b_ing)的方式來;性 ^接到-封裝該上，而是將其.轉過㈣轉接凸塊來 2連接並M(_nt)到封裝基板上。由於覆晶接合技術 不萬要金線的連接，故能大㈣切裝體的尺寸並增加曰 粒與封裝基板間電路傳遞的速度。 曰曰 請參考第1圖至第6圖，第丨圖至第6圖為習知形成鮮 接凸塊10的方法示意圖。如第丨圖所示，首先提供一基底 12,例如已完成内部元件及線路設置之晶圓。基底12之表 上匕έ有一圖案化之保護層14 (passivati〇I1 iayer)，且保 W蔓層14暴露出複數個銲墊16，而為了方便說明起見，故 在圖t僅顯示一銲墊16。其中銲墊16可由銅或鋁所構成， 藉以電性連接形成於基底12中之内部線路（圖中未顯示）與 封農基板上之外部線路(圖中未顯示）。 1286845 ★如第2圖所示，接著利用濺鍍、沉積與蝕刻等製程形成 複數層堆豐之凸塊下金屬層】8(under bump metaljurgy 父Γ) 並覆盍於母一鲜塾16及保護層14。其_凸塊下金 屬層18可依序由鋁/鎳釩/銅或鈦/鎳鈒/銅所構成。如第3 圖所示，然後於整個基底】2表面形成一光阻層2〇，覆蓋 ^保濩層14與凸塊下金屬層丨.8上方。其中光阻層％的材 料可為乾膜光阻或液態光阻。 加接者如帛4目所示，進行一曝光與顯影製程將光阻層 β案化以於光阻層2〇中形成複數個開口 22，並相對 戶路出各知墊16上方之凸塊下金屬㉟18。如第5圖 中不复然，用電鍍的方式將一銲料24填佈於各開口 22 後，鲜料％可為錫或銅等材料。在剝除光阻層20之 以著如第6圖所不’最後再進行—回銲_·)製程， =複數個銲接凸塊1G於各相對應之銲塾16上方，完 °形成銲接凸塊10的方法。 利用習4而/在進订更細線路製程或高電流密度應用時， 所需的；^作方法卿_銲接凸塊時常紐承受製程時 因此，^ ’進而影響整個製程的良率與穩定性。 受應力谁仏夠有放緩衝銲接凸塊於更細線路製程時之所 而提高銲接凸塊之穩定性即為當前重要的課題之-。 1286845 ^ 【發明内容】 ' 本發明之主要目的在於提供一種形成銲接凸塊的方 • 法，來解決上述習知之問題。 根據本發明之申請專利範圍，係提供一種形成銲接凸塊 的方法。首先提供一基底，且該基底表面形成有一凸塊下 金屬層（under bump metallurgy layer)。然後形成一光阻層於 該凸塊下金屬層表面，並圖案化該光阻層，以於該光阻層 攀 中形成至少一開口，用以暴露部分該凸塊下金屬層，且該 開口内包含有至少一柱狀結構。接著形成至少一金屬材料 於該開口中，並包覆該柱狀結構，最後進行一光阻剝離步 驟，以移除該圖案化光阻層。 由於本發明之形成銲接凸塊方法係於沈積一光阻層於 該凸塊下金屬層表面後，然後進行一曝光顯影製程以於該 • 光阻層中形成至少一開口以及至少一柱狀結構於該開口 内，因此能於細線路製程時增加銲接凸塊之高度與穩定 ^ 性。除此之外，形成於銲接凸塊内之柱狀結構亦可於細線 ^ 路製程時作為銲接凸塊之應力緩衝材料，進而減少填入金 屬材料時進行電鍍製程所耗費的製程時間以及增加晶圓之 產出量。 7 1286845 _ 【實施方式】 • 請參照第7圖至第13圖，第7圖至第13圖為本發明形 成I干接凸塊之較佳實施例的方法示意圖。如第7圖所 示，首先提供一基底3〇，例如一晶圓，且基底3〇表面形 成有複數個導體結構，例如銲墊Μ ,而其材f通常為銅或 鋁，藉以電性連接形成於基底3〇中之内部線路（圖中未顯 示）與封裝基板上之外部線路（圖中未顯示）。然後形成一圖 φ 案化保護層34覆蓋於基底30表面並分別暴露各銲墊32之 部分表面，用以保護基底.30中之内部線路（圖中未顯示）。 接著進行一濺鑛製程（sputtering)、沉積與姓刻等製程， 以形成袓數層堆$之凸塊下金屬層36(under bump metallurgy layer, UBM layer)並覆蓋於部分暴露出之銲塾32 與圖案化保護層34表面。其中，凸塊下金屬層36通常由 一黏著層（adhesion layer)、一 阻障層（barrier layer )、以及一 _ 潤濕層所組成。黏著層係用以提供銲墊32及圖案化保護層 34良好的黏著性，其材質可為鋁、鈦、鉻、鎢化鈦等。阻 . 障層係用以防止録球與銲墊之金屬互相擴散，其材質可為 . 鎳飢、鎳等。而潤濕層則係提供凸塊下金屬層36與銲球之 間良好之沾附性，其材質可為銅、鉬、鉑等。 ，如第8圖所不’隨後形成一圖案化遮罩。例如先於凸塊 下金屬層36表面形成一光阻層38，而光阻層38可選自由 1286845 環氧樹脂（epoxy)、聚亞醯胺(polyimide)、或乾膜（dry film) 所組成的群組，然後再進行一曝光顯影製程，以於光阻層 38中形成至少一開口 40·，並同時於開口 4〇内形成至少一 柱狀結構42。其中，開口 40係用以暴露部分凸塊下金屬 層36,且為後續填入之銲料與凸塊下金屬層36之結合區， 故其厚度係與後續將形成之録接凸塊的高度相關，而柱狀 、、、。構42則疋用來作為後續支撐銲接凸塊之緩衝材料。此 丨外，在本較佳實施例中，開口 40係位於銲墊32之正上方， 然而不侷限於本實施例，開口 4〇亦可形成於鄰近於焊塾 之凸塊下金屬層36上，以配合rdl製程中因接點配置 設计上的需要两需變更接點的位置。 如第9圖所示，接著進行一電鍍製程以填入一由銅所構 成之第一金屬層44於開口 40中，然後如第1〇圖所示，進 行另一電鍍製程或一印刷製程來填入一由銲錫所組成之第 丨二金屬層46於第一金屬層44上，且第二金屬層46的表面 係約略與光阻層38之表面齊平。然而，不受限於先前敘述 *之填入第一金屬層44與第二金屬層46之步驟，本發明又 •可於柱狀結構42形成後，直接進行一電鍍製程或一印刷製 程來填入一僅由銲錫所組成之金屬層（圖未示）於開口 40 中’且該金屬層係與光阻層38之表面齊平。 如第11圖所示，接著進行一回銲(reflow)製程，使填入 9 1286845 於開口 40内由銲錫所組成之第二金屬層46因表面張力而 變成球狀，並包覆柱狀結構42，以於所對應之銲墊32與 凸塊下金屬層36上形成一銲接凸塊48。如第12圖所示， 接著進行一光阻剝除步驊，以移除光阻層38。此外，不囿 限於前述之剝除光阻前便先進行一回銲製程的方式，本發 明又可於填入第二金屬層46之後，即先移除光阻層38， 然後再進行一回銲製程來使第二金屬層46形成銲接凸塊 48 〇 最後如第13圖所示，利用第二金屬層46以及第一金屬 層44當作遮罩來進行一蝕刻製程，用以去除部份之凸塊下 金屬層36直至圖案化保護層34表面。此外，本發明亦可 在開口 40中之第一金屬層44形成後，如第9圖所示，隨 即利用第一金屬層44當作遮罩來進行一姓刻製程，用以去 除部份之凸塊下金屬層36直至圖案化保護層34表面，然 後進行一印刷製程，以於第一金屬層44上形成一由銲錫所 組成之第二金屬層46。最後再進行一回銲(reflow)製程，使 第二金屬層46因表面張力而變成球狀，並包覆柱狀結構 42 〇 值得注意的是，由於第二金屬層46與第一金屬層44内 包含有先前於曝光顯影製程中所形成之柱狀結構42,因此 本發明除了可以.大幅減少習.知電鍍製程所耗費之製程時間 1286845 以及增加晶圓產出量（WPH)，並可利用最後形成於銲接凸 塊48中的柱狀結構42來強化銲接凸塊48的支撐結構，以 有效增加銲接凸塊48的高度，進而改善本發明在進行細線 路製程時之穩定性。 除此之外，本發明另揭露一種銲接凸塊結構50。如第 13圖所示，銲接凸塊結構50包含有一基底30，例如一晶 _ 圓、一設於基底30表面之銲墊32、一設於銲墊32及銲墊</ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Different from the traditional packaging technology, in the flip chip bonding technology, the solder pad is again connected to the wire b_ing; the ^ is connected to the package, but is turned over (4) The bumps are connected 2 and M(_nt) onto the package substrate. Since the flip chip bonding technique does not require a gold wire connection, it can enlarge the size of the body and increase the speed of circuit transfer between the particles and the package substrate.曰曰 Refer to FIGS. 1 to 6 , and FIGS. 6 to 6 are schematic views showing a conventional method of forming the fresh bumps 10 . As shown in the figure, a substrate 12 is first provided, such as a wafer that has completed internal components and line placement. A patterned protective layer 14 is formed on the surface of the substrate 12, and the protective layer 14 exposes a plurality of pads 16, and for convenience of explanation, only one solder is shown in FIG. Pad 16. The solder pad 16 may be made of copper or aluminum, and is electrically connected to an internal circuit (not shown) formed in the substrate 12 and an external circuit (not shown) on the agricultural substrate. 1286845 ★ As shown in Figure 2, the following steps are used to form a metal layer under the bumps of a plurality of layers by sputtering, deposition and etching. 8 (under bump metaljurgy father) and covered with a mother-in-law 16 and protection Layer 14. The under bump metal layer 18 may be composed of aluminum/nickel vanadium/copper or titanium/nickel germanium/copper in sequence. As shown in Fig. 3, a photoresist layer 2 is formed on the surface of the entire substrate 2, covering the top of the ^2 layer and the underlying metal layer 丨8. The material of the photoresist layer% may be a dry film photoresist or a liquid photoresist. As shown in FIG. 4, an exposure and development process is performed to form the photoresist layer β to form a plurality of openings 22 in the photoresist layer 2, and the bumps above the respective pads 16 are formed. Lower metal 3518. As is not the case in Fig. 5, a solder 24 is applied to each opening 22 by electroplating, and the fresh material % may be a material such as tin or copper. In the process of stripping the photoresist layer 20, as shown in FIG. 6, the process of "finishing again - reflowing _·), = a plurality of solder bumps 1G over the corresponding solder bumps 16 to form a solder bump The method of block 10. Utilize Xi 4 / when ordering a finer line process or high current density application, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ . It is currently an important issue to improve the stability of the solder bumps when the stress is sufficient to have the buffer bumps in the finer line process. 1286845 ^ [Summary of the Invention] The main object of the present invention is to provide a method of forming a solder bump to solve the above-mentioned problems. According to the scope of the invention, there is provided a method of forming a solder bump. First, a substrate is provided, and an under bump metallurgy layer is formed on the surface of the substrate. Forming a photoresist layer on the surface of the underlying metal layer, and patterning the photoresist layer to form at least one opening in the photoresist layer to expose a portion of the under bump metal layer, and the opening It contains at least one columnar structure. Then, at least one metal material is formed in the opening, and the columnar structure is covered, and finally a photoresist stripping step is performed to remove the patterned photoresist layer. The method for forming a solder bump of the present invention is after depositing a photoresist layer on the surface of the underlying metal layer, and then performing an exposure and development process to form at least one opening and at least one columnar structure in the photoresist layer. Within the opening, the height and stability of the solder bumps can be increased during the thin line process. In addition, the columnar structure formed in the solder bump can also be used as a stress buffering material for the solder bump during the thin-line process, thereby reducing the processing time and increasing the crystal cost of the electroplating process when filling the metal material. The output of the circle. 7 1286845 _ [Embodiment] Please refer to FIGS. 7 to 13 , and FIGS. 7 to 13 are schematic views showing a method of forming a preferred embodiment of the dry contact bump of the present invention. As shown in FIG. 7, a substrate 3, such as a wafer, is first provided, and a plurality of conductor structures, such as pad pads, are formed on the surface of the substrate 3, and the material f is usually copper or aluminum for electrical connection. An internal line (not shown) formed in the substrate 3A and an external line (not shown) on the package substrate. Then, a patterned protective layer 34 is formed over the surface of the substrate 30 and exposes a portion of the surface of each of the pads 32 to protect the internal wiring (not shown) in the substrate 30. Then, a process such as sputtering, deposition, and surname etching is performed to form an under bump metallurgy layer (UBM layer) and cover the partially exposed solder bumps 32. And patterning the surface of the protective layer 34. The under bump metal layer 36 is generally composed of an adhesion layer, a barrier layer, and a wetting layer. The adhesive layer is used to provide good adhesion of the bonding pad 32 and the patterned protective layer 34, and the material thereof may be aluminum, titanium, chromium, titanium tungsten or the like. The barrier layer is used to prevent the metal between the ball and the pad from interfering with each other. The material can be nickel hunger, nickel, etc. The wetting layer provides good adhesion between the under bump metal layer 36 and the solder balls, and the material thereof may be copper, molybdenum, platinum or the like. As shown in Fig. 8, a patterned mask is subsequently formed. For example, a photoresist layer 38 is formed on the surface of the under bump metal layer 36, and the photoresist layer 38 may be composed of 1286845 epoxy, polyimide, or dry film. The group is then subjected to an exposure development process to form at least one opening 40· in the photoresist layer 38 and simultaneously form at least one columnar structure 42 in the opening 4〇. The opening 40 is used to expose a portion of the under bump metal layer 36 and is a bonding region between the subsequently filled solder and the under bump metal layer 36, so the thickness is related to the height of the recording bump to be formed later. , and columnar, ,,. The structure 42 is used as a buffer material for subsequently supporting the solder bumps. In this preferred embodiment, the opening 40 is located directly above the bonding pad 32. However, the opening 4 is not limited to the embodiment, and the opening 4 is also formed on the under-metal layer 36 of the bump adjacent to the bonding pad. In order to meet the needs of the contact configuration in the rdl process, the position of the contact needs to be changed. As shown in FIG. 9, an electroplating process is then performed to fill a first metal layer 44 made of copper in the opening 40, and then another electroplating process or a printing process is performed as shown in FIG. A second metal layer 46 composed of solder is filled in the first metal layer 44, and the surface of the second metal layer 46 is approximately flush with the surface of the photoresist layer 38. However, the present invention is not limited to the steps of filling the first metal layer 44 and the second metal layer 46 as described above, and the present invention can be directly subjected to an electroplating process or a printing process after the columnar structure 42 is formed. A metal layer (not shown) consisting of only solder is placed in the opening 40 and the metal layer is flush with the surface of the photoresist layer 38. As shown in Fig. 11, a reflow process is then performed to fill the second metal layer 46 composed of solder in the opening 40 in the opening 40 to become spherical and to cover the columnar structure. 42. A solder bump 48 is formed on the corresponding pad 32 and the under bump metal layer 36. As shown in Fig. 12, a photoresist stripping step is then performed to remove the photoresist layer 38. In addition, the method is not limited to the foregoing method of performing a reflow process before stripping the photoresist, and the invention may further remove the photoresist layer 38 after filling the second metal layer 46, and then perform another process. The soldering process is used to form the second metal layer 46 to form the solder bumps 48. Finally, as shown in FIG. 13, the second metal layer 46 and the first metal layer 44 are used as masks to perform an etching process for removing portions. The under bump metal layer 36 is patterned to the surface of the patterned protective layer 34. In addition, the present invention can also be used after the first metal layer 44 in the opening 40 is formed, as shown in FIG. 9, and then the first metal layer 44 is used as a mask for the process of removing the portion. The under bump metal layer 36 is patterned to the surface of the protective layer 34, and then a printing process is performed to form a second metal layer 46 composed of solder on the first metal layer 44. Finally, a reflow process is performed to make the second metal layer 46 become spherical due to the surface tension and cover the columnar structure 42. It is noted that the second metal layer 46 and the first metal layer 44 are The columnar structure 42 formed in the prior exposure and development process is included, so that the invention can greatly reduce the processing time of 1286845 and increase the wafer throughput (WPH), and can be utilized. Finally, the columnar structure 42 formed in the solder bumps 48 strengthens the support structure of the solder bumps 48 to effectively increase the height of the solder bumps 48, thereby improving the stability of the present invention in the fine line process. In addition, the present invention further discloses a solder bump structure 50. As shown in FIG. 13, the solder bump structure 50 includes a substrate 30, such as a crystal _ circle, a pad 32 disposed on the surface of the substrate 30, a pad 32 and a pad.
W 32周圍之部份基底30上凸塊下金屬層36以及一設於凸塊 下金屬層36表面之銲接凸塊48，且銲接凸塊48内包含有 至少一柱狀結構42。其中，銲择凸塊48係為銅、銲錫或 銅/銲錫所組成之銲接凸塊，而柱狀結構42則係由環氧樹 脂、聚亞醯胺、或乾膜所組成，以作為支撐銲接凸塊48之 緩衝材料。 B 相較於習知技術，本#明之形成鮮接凸塊方法係先形成 一光阻層於該凸塊下金屬層表面，然後進行一曝光顯影製 . 程，以於該光阻層中形成至少一開口，用以暴露部分該凸 _ 塊下金屬層，且該開口内包含有至少一柱狀結構。然後填 入至少一金屬材料於該開口中，包覆該柱狀結構，並使該 金屬材料形成銲接凸塊。由於該銲接凸塊内包含有至少一 由曝光顯影步驟所形成之柱狀結構，因此能有效減少填入 金屬材料時電鑛製程中所耗費的製程時間並增加銲接凸塊 11 1286845 之高度與穩定性。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第6圖為習知形成銲接凸塊的方法示意圖。 第7圖至第13圖為本發明形.成銲接凸塊之較佳實施例的 方法示意圖。 【主要元件符號說明】 10 銲接凸塊 12 基底 14 保護層 16 銲墊 18 凸塊下金屬層 20 光阻層 22 開口 24 銲料 30 基底 32 銲墊 34 圖案化保護層 36 凸塊下金屬層 38 光阻層 40 開口 42 柱狀結構 44 第一金屬層 46 第二金屬層 48 銲接凸塊 50 銲接凸塊結構A portion of the base 30 around the W 32 has a lower bump metal layer 36 and a solder bump 48 disposed on the surface of the under bump metal layer 36, and the solder bump 48 includes at least one pillar structure 42 therein. Wherein, the solder bumps 48 are solder bumps composed of copper, solder or copper/solder, and the pillar structures 42 are composed of epoxy resin, polyamine, or dry film to serve as a support solder. The buffer material of the bumps 48. Compared with the prior art, the method of forming a fresh bump is to form a photoresist layer on the surface of the underlying metal layer of the bump, and then performing an exposure and development process to form in the photoresist layer. At least one opening for exposing a portion of the underlying metal layer, and the opening includes at least one columnar structure. At least one metal material is then filled in the opening to coat the columnar structure and form the metal material into a solder bump. Since the solder bump includes at least one columnar structure formed by the exposure and development step, the processing time consumed in the process of filling the metal material can be effectively reduced and the height and stability of the solder bump 11 1286845 can be increased. Sex. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 6 are schematic views showing a conventional method of forming a solder bump. Fig. 7 through Fig. 13 are schematic views showing the method of forming a solder bump according to a preferred embodiment of the present invention. [Main component symbol description] 10 solder bump 12 substrate 14 protective layer 16 pad 18 under bump metal layer 20 photoresist layer 22 opening 24 solder 30 substrate 32 pad 34 patterned protective layer 36 under bump metal layer 38 light Resistor layer 40 opening 42 columnar structure 44 first metal layer 46 second metal layer 48 solder bump 50 solder bump structure