CN100533698C - Method for making embedded resistor in semiconductor wafer - Google Patents
Method for making embedded resistor in semiconductor wafer Download PDFInfo
- Publication number
- CN100533698C CN100533698C CNB200610029515XA CN200610029515A CN100533698C CN 100533698 C CN100533698 C CN 100533698C CN B200610029515X A CNB200610029515X A CN B200610029515XA CN 200610029515 A CN200610029515 A CN 200610029515A CN 100533698 C CN100533698 C CN 100533698C
- Authority
- CN
- China
- Prior art keywords
- metal
- resistor
- layer
- embedded
- salient point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing method for the embedding resistor in the semiconductor wafer, in particular to manufacturing the embedding resistor in the process of forming the conductive convex point on the semiconductor wafer. In the process an etching step of the top sub-metal layer of the multi-conductive layer in the area forming the embedding resistor is added, and the resistivity of the metal layer after removing the top sub-metal layer is more than that of the metal layer with the top sub-metal layer, and then the resistor which is covered by a passive layer in the later steps is formed in the semiconductor wafer, thus forming the embedding resistor which replaces the terminal resistor arranged on the package printed circuit board of semiconductor devices, increasing the packaging density and ensuring no damage to the properties of high speed semiconductor devices.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, particularly relate to the manufacture method of embedded-resistor in the semiconductor wafer.
Background technology
In current semi-conductor industry, need on substrate, form conductive salient point, specifically be on semiconductor device, to form solder bump.Solder bump is formed on the integrated circuit (IC) chip usually, form thus can flip chip bonding semiconductor chip (Flip chip), and current general semiconductor chip face-down bonding technique has promptly replaced chip and has faced up with traditional wire bond technology of each pad on the conductive filament connection chip.
But, when high-speed semiconductor device is installed in the printed circuit board (PCB) (PCB), need (Input Output be provided with a large amount of resistors as terminating resistor near IO), forms the filter structure that prevents that the semiconductor device speed of service from postponing thus in input and output.Along with the increase of IO quantity, just there are not enough spaces that a large amount of terminating resistor near IO is installed more on the printed circuit board (PCB).Thereby cause IO speed to postpone, thereby damaged the performance of whole semiconductor chip.
Summary of the invention
Existingly on printed circuit board (PCB), not have enough spaces that difficulty near a large amount of terminating resistor of IO is installed more in order overcoming, to propose the present invention.
The objective of the invention is, on semiconductor wafer, form conductive salient point with a large amount of embedded-resistors that limited, replacement is gone up a large amount of terminating resistor be provided with at grid array of solder balls semiconductor die package printed circuit board (PCB) (BGP) near IO, a large amount of embedded-resistors is to form in the technical process of conductive salient point to form on semiconductor wafer.
The invention provides the manufacture method of a large amount of embedded-resistors in the technical process that on semiconductor wafer, forms conductive salient point, according to the inventive method, only need on semiconductor wafer, form photoetching of increase in the technological process of conductive salient point, etch step, just can form embedded-resistor.
The manufacture method of embedded-resistor comprises the steps: in the semiconductor wafer of the present invention
Order is carried out on the semiconductor wafer that is formed with semiconductor device structure and pad:
1) apply first passivation layer, order is developed, exposes, is solidified then;
2) sputtering deposit multiple layer metal rete;
3) apply first photoresist layer, exposure imaging, firm rete;
4) electroplated metal layer on the position that is not covered by photoresist;
5) the laggard row of stripping photolithography glue-line forms the etching first time that embedded-resistor carries out, and the multiple layer metal rete that etching was once protected by photoresist layer forms the metallic conduction band;
6) apply second photoresist layer, determine to want the zone of etching formation embedded-resistor, etching will form the top layer plated metal in the metal level in the embedded-resistor zone, determines embedded-resistor;
7) apply second passivation layer and cover resistor;
8) the splash-proofing sputtering metal layer forms the lower metal layer of solder bump as metal under the salient point;
9) apply the 3rd photoresist layer, exposure imaging, firm rete, for next processing step forms the photoresist mask;
10) electroplate salient point metal, stripping photoresist;
11) carry out metal etch under the salient point;
Form solder bump and embedded-resistor.
Be aluminium forming the pad that forms on the semiconductor device among the present invention.
According to the present invention, described first and second passivation material are benzocyclobutene (hereinafter to be referred as BCB), or polyimides (hereinafter to be referred as PI).
According to the present invention, when described salient point metal was gold, described sputter multiple layer metal rete was titanium tungsten/gold (TiW/Au), and described multiple layer metal rete is to form with the physical vapor deposition method.
According to the present invention, when described salient point was solder metal, described multiple layer metal rete was chromium/copper (Cr/Cu), and described multiple layer metal rete is to form with the physical vapor deposition method.And preferably also comprise backflow salient point metal and remove the step of scaling powder.
According to the present invention, described electroplated metal layer is titanium tungsten/gold or chromium/copper, and metal is TiW/Au or Cr/Cu under the described salient point.
According to the present invention, metal is (TiW/Au or Cr/Cu) under the described salient point.
See that from above-mentioned technical scheme of the present invention the major technique measure that forms embedded-resistor on semiconductor wafer is to remove one in etching to form the top layer copper layer among multiple layer metal layer Cr/Cu in the zone of embedded-resistor or the TiW/Au or the Cu film or gold (Au) film of top layer gold (Au) layer.Because the resistivity of multiple layer metal layer Cr/Cu is less than the resistivity of Cr metal level, the resistivity of multiple layer metal layer TiW/Au is less than the resistivity of multiple layer metal layer TiW, therefore in semiconductor wafer, formed resistor, formed resistor is passivated film and buries in step subsequently, thereby produces embedded-resistor in semiconductor wafer.
Embedded-resistor of the present invention is according to the design principle design of the sheet resistance device in the integrated circuit, that is, resistance value equals the sheet resistance value R of a square conductive layer
(length of Ω/) and the conductive strips that constitute resistor is divided by the product of the square that width obtained () quantity of conductive strips, i.e. " R
(quantity of Ω/) * ".Constitute the sheet resistance value R of the conductive strips of embedded-resistor
(Ω/) depends on the constituent material and the thicknesses of layers of conductive strips.
Scope by the resistance value of embedded-resistor of the present invention is 50～75 Ω (ohms).Constitute width 12～20 μ m of the conductive strips of embedded-resistor.The length that constitutes the conductive strips of embedded-resistor is 240～600 μ m.
Just on semiconductor wafer, increase an etching in the technical process of the requisite conductive salient point of formation with the inventive method and removed the step of the top layer sublayer of the multiple layer metal layer in the zone that will form embedded-resistor, i.e. step 6.Used lithographic method is the general lithographic method of the industry, and increasing a cost that processing step caused increases few.But use the inventive method, the terminating resistor that will be installed on the encapsulation printed circuit board (PCB) is fabricated directly in the semiconductor wafer, reduced the space that high-speed semiconductor device occupies on the encapsulation printed circuit board (PCB), improved packaging density, prevent to postpone the speed of service of high-speed semiconductor device, can guarantee that the performance of high-speed semiconductor device is not damaged.
Description of drawings
The following description of carrying out in conjunction with the drawings the present invention may be better understood purpose and advantage of the present invention, accompanying drawing is a part of specification, accompanying drawing illustrates principle of the present invention and feature with the word segment of specification, demonstrates the embodiment that represents the principle of the invention and feature in the accompanying drawing.In the accompanying drawing:
Fig. 1 is according to the first embodiment of the present invention, is being formed with the cutaway view that forms the semiconductor chip structure of passivation layer on the wafer of aluminum pad;
Fig. 2 is according to the first embodiment of the present invention, has formed the cutaway view of the semiconductor chip structure of Cr/Cu layer on passivation layer;
Fig. 3 is according to the first embodiment of the present invention, forms the cutaway view of the semiconductor chip structure behind the first photoresist pattern;
Fig. 4 is according to the first embodiment of the present invention, the cutaway view of the semiconductor chip structure behind the regional plated metal that does not have the photoresist protection;
Fig. 5 is according to the first embodiment of the present invention, the cutaway view of the semiconductor chip structure behind the metal level that etching was once protected by photoresist behind the stripping photoresist;
Fig. 6 A is according to the first embodiment of the present invention, and etching forms the cutaway view of the semiconductor chip structure behind the resistor;
Fig. 6 B is according to the first embodiment of the present invention, the partial view of the conductive strips structure on the semiconductor wafer of manufacturing;
Fig. 6 C is according to the first embodiment of the present invention, the partial view of the embedded-resistor structure on the semiconductor wafer of manufacturing;
Fig. 7 is according to the first embodiment of the present invention, and resistor is passivated the cutaway view of the semiconductor chip structure of layer covering;
Fig. 8 is according to the first embodiment of the present invention, the cutaway view of the semiconductor chip structure under the sputter salient point behind the metal;
Fig. 9 is according to the first embodiment of the present invention, forms the cutaway view of the semiconductor chip structure behind the 3rd photoresist pattern;
Figure 10 A is according to the first embodiment of the present invention, and plating forms the structure cutaway view behind the solder bump metal;
Figure 10 B is according to the first embodiment of the present invention, stripping photoresist and carry out the structure cutaway view behind the metal etch under the salient point;
Figure 10 C is according to the first embodiment of the present invention, refluxes and removes the solder bump that forms behind the scaling powder and the structure cutaway view of embedded-resistor;
Figure 11 A is according to a second embodiment of the present invention, the structure cutaway view in the semiconductor wafer of manufacturing behind the plating formation au bump;
Figure 11 B is according to a second embodiment of the present invention, stripping photoresist and the au bump that carries out forming behind the metal etch under the salient point and the structure cutaway view of embedded-resistor;
Figure 12 is the plane graph of the resistor that forms in forming the technology of solder bump according to the first embodiment of the present invention;
Figure 13 A is the plane design drawing of embedded-resistor according to another embodiment of the present invention; With
Figure 13 B is the schematic diagram of embedded-resistor in circuit diagram according to another embodiment of the present invention.
Description of reference numerals
1 wafer
2 pads
3 passivation layers
4 first chromium-coppers (Cr/Cu) layer
41 chromium layers
42 bronze medal layers
5 photoresist patterns
6 electroplated metal layers
7 resistors
71 resistors
72 resistors
8 passivation layers
9 second chromium-coppers (Cr/Cu) layer
10 the 3rd photoresists
11 electro-copperings
12 electronickellings
13 solder bump metals
4 ' the first titaniums tungsten/gold (TiW/Au) layer
4 " multiple layer metal layer
9 ' the second titaniums tungsten/gold (TiW/Au) layer
11 ' electrogilding
13 ' au bump metal
Embodiment
Below with the specific embodiment explanation method of in semiconductor wafer, making embedded-resistor of the present invention.The inventive method is to form in the technical process of conductive salient point to make embedded-resistor on semiconductor wafer.
In the present embodiment, be on semiconductor wafer, to form in the technical process of solder bump in semiconductor wafer, to make embedded-resistor.Its manufacturing process is as follows:
Order is carried out on the semiconductor wafer 1 that is formed with semiconductor device structure and aluminum pad 2:
1) as shown in Figure 1, apply the benzocyclobutene material as passivation layer 3, order is exposed, develops, is solidified then;
2) as shown in Figure 2, use the physical vapor deposition method, sputtering deposit multiple layer metal rete chromium/copper (Cr/Cu) layer 4, wherein, and first deposit chromium layer 41, the cement copper layer 42 then;
3) as shown in Figure 3, applying first photoresist layer 5, expose, development, firm rete, is that next processing step forms the photoresist pattern;
4) as shown in Figure 4, plating rete 6 on the position that is not covered (copper layer) by photoresist, other parts are protected by photoresist layer;
5) as shown in Figure 5, peel off first photoresist layer 5 after, form the etching first time that embedded-resistor carries out, etching sheet metal 4 once by the part of first photoresist layer 5 protection, form the metallic conduction band, see also 6 among Fig. 6 B;
6) as shown in Figure 6A, carry out another photoetching process, determine to want etching to form the zone of embedded-resistor, etching will form the top layer copper in the metal level Cr/Cu layer 4 in the embedded-resistor zone, remove the copper thin metal film in copper (Cu) layer in the Cr/Cu multiple layer metal layer, determine that through this step the shape of embedded-resistor determines embedded-resistor 7, please be simultaneously referring to 7 among Fig. 6 C;
7) as shown in Figure 7, apply the benzocyclobutene material again, cover resistor 7, form embedded-resistor as second passivation layer 8;
8) as shown in Figure 8, splash-proofing sputtering metal (Cr/Cu) forms the lower metal layer of solder bump as ubm layer 9 again;
9) as shown in Figure 9, applying the 3rd photoresist layer 10, expose, development, firm rete, is that next processing step forms the photoresist mask;
10) shown in Figure 10 A, electroplate scolder 13 and the scaling powder when needing after, stripping photoresist, and metal under the salient point 9 carried out etching is shown in Figure 10 B;
11) solder bump is refluxed and remove scaling powder, form solder bump and embedded-resistor thus.
The scope of the resistance value of the embedded-resistor of making by present embodiment is 50～75 Ω (ohms).Constitute width 12～20 μ m of the conductive strips of embedded-resistor.The length that constitutes the conductive strips of embedded-resistor is 240～600 μ m.
In the present embodiment, be to form in the technical process of au bump on semiconductor wafer, make embedded-resistor in semiconductor wafer, its manufacturing process is as follows:
Order is carried out on the semiconductor wafer 1 that is formed with semiconductor device structure and aluminum pad 2:
1) can reference example 1 shown in Figure 1, apply benzocyclobutene or polyimide material as passivation layer 3, order is exposed, develops, is solidified then;
2) can reference example 1 shown in Figure 2, just different with the material of the deposit of embodiment 1, present embodiment is use the physical vapor deposition method, sputtering deposit multiple layer metal rete titanium tungsten/gold (TiW/Au) layers 4 ', wherein, first deposit titanium tungsten, deposit gold then;
3) reference example 1 is shown in Figure 3, applies first photoresist layer 5, expose, development, firm rete, and be that next processing step forms the photoresist pattern;
4) reference example 1 is shown in Figure 4, electrogilding on the position that is not covered (Au) rete 6 by photoresist ' and, other parts are protected by photoresist layer;
5) reference example 1 is shown in Figure 5, peel off first photoresist layer 5 after, form the etching first time that embedded-resistor carries out, etching sheet metal 4 ' once by the part of first photoresist layer 5 protection, form the metallic conduction band, also can be with reference to 6 among the figure 6B;
6) shown in Fig. 6 A of reference example 1, carry out another photoetching process, determine to want etching to form the zone of embedded-resistor, etching to form metal level TiW/Au layer 4 in the embedded-resistor zone ' in the top layer gold, remove the golden thin metal film in gold (Au) layer in the TiW/Au multiple layer metal layer, determine that through this step the shape of embedded-resistor determines embedded-resistor 7, also can be with reference to 7 among the figure 6C;
7) reference example 1 is shown in Figure 7, applies benzocyclobutene or polyimide material again as second passivation layer 8, covers resistor 7, forms embedded-resistor;
8) reference example 1 is shown in Figure 8, material therefor difference just, in the present embodiment, splash-proofing sputtering metal Au/TiW as ubm layer 9 ', form the lower metal layer of solder bump;
9) reference example 1 is shown in Figure 9, applies the 3rd photoresist layer 10, expose, development, firm rete, and be that next processing step forms the photoresist mask;
10) shown in Figure 11 A, electrogilding material 13 ' after, stripping photoresist 10, and to metal 9 under the salient point that is not covered by au bump ' carry out etching, shown in Figure 11 B;
Form au bump and embedded-resistor thus.
The scope of the resistance value of the embedded-resistor of making by present embodiment is that 50 Ω (ohm) are to 75 Ω (ohm).The width 12 μ m of the conductive strips of formation embedded-resistor are to 20 μ m.The length that constitutes the conductive strips of embedded-resistor is that 240 μ m are to 600 μ m.
Other embodiment
Can design the figure of the conductive strips that constitute embedded-resistor according to specific requirement to the resistance value of embedded-resistor, shown in Figure 13 A and Figure 13 B, be the result of other two embodiment, wherein embedded- resistor 71,72 all is a bending shape, can obtain having the embedded-resistor of high electrical resistance value in this way.
More than be used in the method that forms embedded-resistor in the technical process that forms solder bump and au bump on the semiconductor wafer method of making embedded-resistor in semiconductor wafer has been described.But the invention is not restricted to detailed description herein.The technical staff of the industry should be appreciated that under the premise without departing from the spirit and scope of the present invention, the present invention can implement with other form, and the present invention can also have various improvement and variation, and these improvement and variation all fall in the scope of protection of present invention.Therefore, by whole technical schemes of the present invention, cited execution mode just is used to illustrate the present invention rather than restriction the present invention, and the present invention is not limited to the details of describing herein.The scope of protection of present invention is defined by appending claims.
Claims (12)
1. the manufacture method of embedded-resistor in the semiconductor wafer comprises the steps:
Order is carried out on the semiconductor wafer that is formed with semiconductor device structure and pad:
1) apply first passivation material, order is developed, exposes, is solidified then;
2) sputtering deposit multiple layer metal rete;
3) apply first photoresist layer, exposure imaging, firm rete;
4) electroplated metal layer on the position that is not covered by photoresist;
5) the laggard row of stripping photolithography glue-line forms the etching first time that embedded-resistor carries out, and the multiple layer metal rete that etching was once protected by photoresist layer forms the metallic conduction band;
6) apply second photoresist layer, determine to want the zone of etching formation embedded-resistor, etching will form the top layer plated metal in the metal level in the embedded-resistor zone, determines embedded-resistor;
7) apply second passivation layer and cover resistor;
8) the splash-proofing sputtering metal layer forms the solder bump lower metal layer as metal under the salient point;
9) apply the 3rd photoresist layer, exposure imaging, firm rete, for next processing step forms the photoresist mask;
10) electroplate salient point metal, stripping photoresist;
11) carry out metal etch under the salient point;
Form solder bump and embedded-resistor.
2. method according to claim 1 is characterized in that described pad is an aluminium.
3. method according to claim 1 is characterized in that, described first and second passivation material are benzocyclobutene or polyimides.
4. method according to claim 1 is characterized in that, described salient point metal is a gold, and described multiple layer metal rete is titanium tungsten/gold (TiW/Au).
5. method according to claim 1 is characterized in that, described salient point metal is a solder metal, and described multiple layer metal rete is chromium/copper (Cr/Cu).
6. method according to claim 1 is characterized in that, when described salient point metal was solder metal, described method further comprised: carry out the solder bump backflow at last and remove the scaling powder step.
7. according to claim 4 or 5 described methods, it is characterized in that described multiple layer metal rete is to form with the physical vapor deposition method.
8. method according to claim 1 is characterized in that, described electroplated metal layer is titanium tungsten/gold or chromium/copper.
9. method according to claim 1 is characterized in that, when the salient point metal was gold, metal was titanium tungsten/gold under the described salient point.
10. method according to claim 1 is characterized in that, when the salient point metal was solder metal, metal was chromium/copper under the described salient point.
11. method according to claim 1 is characterized in that, the conductive strips length of the embedded-resistor of formation is 240～600 μ m, and width is 12～20 μ m.
12. method according to claim 1 is characterized in that, the resistance of the embedded-resistor of formation is 50～75 Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610029515XA CN100533698C (en) | 2006-07-28 | 2006-07-28 | Method for making embedded resistor in semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610029515XA CN100533698C (en) | 2006-07-28 | 2006-07-28 | Method for making embedded resistor in semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101114599A CN101114599A (en) | 2008-01-30 |
| CN100533698C true CN100533698C (en) | 2009-08-26 |
Family
ID=39022837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200610029515XA Active CN100533698C (en) | 2006-07-28 | 2006-07-28 | Method for making embedded resistor in semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100533698C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9953917B1 (en) | 2016-12-12 | 2018-04-24 | General Electric Company | Electronics package with embedded through-connect and resistor structure and method of manufacturing thereof |
| US9953913B1 (en) | 2016-12-12 | 2018-04-24 | General Electric Company | Electronics package with embedded through-connect structure and method of manufacturing thereof |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8368214B2 (en) * | 2008-12-09 | 2013-02-05 | Marvell World Trade Ltd. | Alpha shielding techniques and configurations |
| CN102026489B (en) * | 2009-09-23 | 2012-10-17 | 富葵精密组件(深圳)有限公司 | Method for manufacturing circuit board |
| CN102677114B (en) * | 2012-04-16 | 2015-08-19 | 深圳君泽电子有限公司 | High corrosion-resistant electroplating process and high corrosion-resistant electroplating process for electronic components |
| CN104576587A (en) * | 2015-01-22 | 2015-04-29 | 中国电子科技集团公司第四十三研究所 | Packaging convex point structure |
| CN107697880B (en) * | 2017-09-21 | 2019-06-07 | 华中科技大学 | A kind of temperature control vibration-isolating platform and system based on SOI-MEMS |
-
2006
- 2006-07-28 CN CNB200610029515XA patent/CN100533698C/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9953917B1 (en) | 2016-12-12 | 2018-04-24 | General Electric Company | Electronics package with embedded through-connect and resistor structure and method of manufacturing thereof |
| US9953913B1 (en) | 2016-12-12 | 2018-04-24 | General Electric Company | Electronics package with embedded through-connect structure and method of manufacturing thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101114599A (en) | 2008-01-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6455408B1 (en) | Method for manufacturing semiconductor devices having redistribution patterns with a concave pattern in a bump pad area | |
| US5418186A (en) | Method for manufacturing a bump on a semiconductor chip | |
| US6762117B2 (en) | Method of fabricating metal redistribution layer having solderable pads and wire bondable pads | |
| US7122458B2 (en) | Method for fabricating pad redistribution layer | |
| CN100533698C (en) | Method for making embedded resistor in semiconductor wafer | |
| US8211789B2 (en) | Manufacturing method of a bump structure having a reinforcement member | |
| US9219010B2 (en) | Method of manufacturing a semiconductor component | |
| US20020014705A1 (en) | Semiconductor device and manufacturing method of same | |
| JP2012054359A (en) | Semiconductor device and manufacturing method of semiconductor device | |
| US8568822B2 (en) | Apparatus and method incorporating discrete passive components in an electronic package | |
| US7420274B2 (en) | Method for forming a redistribution layer in a wafer structure | |
| US6268656B1 (en) | Method and structure for uniform height solder bumps on a semiconductor wafer | |
| US7115496B2 (en) | Method for protecting the redistribution layer on wafers/chips | |
| US20030155662A1 (en) | Semiconductor device and fabrication method therefor | |
| US20060244109A1 (en) | Method for fabricating connection regions of an integrated circuit, and integrated circuit having connection regions | |
| JP2012074406A (en) | Semiconductor device and method of manufacturing the semiconductor device | |
| EP1003209A1 (en) | Process for manufacturing semiconductor device | |
| US6919264B2 (en) | Method for the solder-stop structuring of elevations on wafers | |
| US20120261812A1 (en) | Semiconductor chip with patterned underbump metallization | |
| US9761555B2 (en) | Passive component structure and manufacturing method thereof | |
| US7056817B2 (en) | Forming a cap above a metal layer | |
| US7541273B2 (en) | Method for forming bumps | |
| JP2005129862A (en) | Semiconductor package and method for manufacturing the same | |
| US9859239B1 (en) | Re-distribution layer structure and manufacturing method thereof | |
| TWI286845B (en) | Bumps and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111130 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111130 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |