TWI599276B - 電子元件與製造方法 - Google Patents
電子元件與製造方法 Download PDFInfo
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Description
本發明係指一種電子元件與製造方法,尤指一種提高抗剪應力之電子元件與製造方法。
常見的各類型電子裝置,其內部係透過多種電子元件的適性組裝與連接設置,來實現不同電子裝置的操作。其中,現有技術常透過至少一凸塊(Bump),來做為電子元件中一驅動晶片與其周邊多個組成元件間之訊號傳導材料。
然而,受限於驅動晶片追求小尺寸的設計規格,此種設計規格將導致驅動晶片所用凸塊的相關尺寸也需對應減少,據此,凸塊減少後之尺寸將造成凸塊設置於驅動晶片的接觸面積與其對應之貼合強度下降,一旦出現外力作用於凸塊上,其將造成部分或全部的凸塊容易剝離驅動晶片之接觸面積,而產生電子元件的損壞與相關修補成本的增加。
因此,於現有電子產品與電子元件追求小尺寸設計之概念下,提供另一種具備改良結構設計之電子元件與製造方法,以對應提高電子元件之抗剪應力能力,已成為本領域之重要課題。
因此,本發明之主要目的即在於提供一種改良結構設計之電子元件與製造方法,以對應提高電子元件的抗剪應力能力。
本發明揭露一種電子元件,用於一電子產品,該電子元件包含有一基板;一凸塊,設置於該基板上,用以電性連接該電子產品;以及至少一凸塊底層金屬(Under bump metal,UBM)層,設置於該凸塊與該基板間來讓該凸塊貼合於該基板;其中,該凸塊底層金屬層形成一缺口結構。
本發明另外揭露一種製造方法,用於一電子產品之一電子元件,其中該電子元件包含有一基板、一凸塊以及至少一凸塊底層金屬(Under bump metal,UBM)層,該製造方法包含有依序於該基板上設置該凸塊底層金屬層與該凸塊;以及於該凸塊底層金屬層進行一蝕刻操作來形成一缺口結構。
10、12‧‧‧電子元件
100、120‧‧‧基板
102、122‧‧‧凸塊
104、124、126‧‧‧凸塊底層金屬層
300、302、304、306、308、310、500、502、504、506‧‧‧步驟
31‧‧‧光阻層
32‧‧‧鈍化層
50‧‧‧製造流程
BB‧‧‧凸塊連接底部
a1‧‧‧第一面積
a2‧‧‧第二面積
A1‧‧‧第一凹槽截面積
A2‧‧‧第二凹槽截面積
C1‧‧‧放大圖
L1‧‧‧第一長度
L2‧‧‧第二長度
m‧‧‧長度
n‧‧‧厚度
第1A圖為本發明實施例一電子元件之局部示意圖。
第1B圖為本發明實施例另一電子元件之局部示意圖。
第2圖為第1A圖中一電子元件之俯視截面示意圖。
第3A圖為第1A圖中一電子元件產生缺口結構之流程圖。
第3B圖為第3A圖中步驟310完成後電子元件12之詳細示意圖。
第3C圖為第3A圖中步驟310完成後電子元件12之俯視截面示意圖。
第4圖為本發明實施例中一電子元件產生缺口結構前或後所進行一剪應力
試驗之比較圖。
第5圖為本發明實施例一之製造流程之流程圖。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解,製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區別元件的方式,而是以元件在功能上的差異來作為區別的基準。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語,故應解釋成「包含但不限定於」。此外,「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此,若文中描述一第一裝置耦接於一第二裝置,則代表該第一裝置可直接連接於該第二裝置,或透過其他裝置或連接手段間接地連接至該第二裝置。
針對習知技術中遭遇外力時,凸塊恐無法有效貼合於驅動晶片上或產生容易剝離之情形,本發明實施例係於凸塊與驅動晶片間之單一或複數個凸塊底層金屬層的結構進行進行改良,且為了方便說明,以下實施例僅適性繪出部分的凸塊與凸塊底層金屬層之結構特徵。
請參考第1A圖,第1A圖為本發明實施例一電子元件12之局部示意圖。如第1A圖所示,本實施例中的電子元件12係設置於一電子產品中,而本實施例中電子產品例如可為一手機、一平板裝置、一穿戴式電子產品或一筆記型電腦等,而電子元件12可為電子產品中的一驅動晶片等,但不限於此。電子元件12包含有一基板120、一凸塊122以及凸塊底層金屬(Under bump metal,UBM)層124、126,其中,基板120可為驅動晶片之一電路板,凸塊122設置於基板120
上來電性連接電子產品之相關傳輸線或操作元件/模組,而凸塊底層金屬層124、126係依序設置於凸塊122與基板120間,以讓凸塊122可適性地貼合於基板120上。當然,於其他實施例中,凸塊與基板間亦可設置兩個以上之凸塊底層金屬層,而非用以限制本發明的範疇。
進一步,本實施例並未限制凸塊與凸塊底層金屬層的材質為何,即考量不同電子產品或電子元件的生產成本與訊號傳輸之導通效率,本實施例可適性挑選各類型金屬或半導體來做為凸塊與凸塊底層金屬層的材質。舉例來說,於一實施例中,凸塊可以選擇一第一材質(例如為金),而多個凸塊底層金屬層可間隔選擇相異於第一材質的一第二材質(例如為銅)與一第三材質(例如為銀),即類似於第1A圖所繪之實施例的結構特徵,其中凸塊與凸塊底層金屬層124、126將形成依序堆疊設置之一金屬鍵結合體,且金屬鍵結合體還耦接至基板,以提供更強之貼合效果來讓凸塊可穩固於基板上。當然,於另一實施例中,若凸塊已選擇為一第一材質,緊鄰之凸塊底層金屬層選擇相異之第二材質,而另一凸塊底層金屬層亦選擇相同之第一材質,則此實施例也將形成類似於第1A圖中的結構特徵,即凸塊與凸塊底層金屬層形成堆疊設置之金屬鍵結合體,並讓凸塊穩固於基板上。
進一步,於另一實施例中,假定凸塊的材質已選擇第一材質,緊鄰凸塊之凸塊底層金屬層的材質選擇相同之第一材質,而另一凸塊底層金屬層的材質選擇相異之第二材質。據此,由於凸塊與緊鄰之凸塊底層金屬層皆為第一材質,將不易區別凸塊與其相緊鄰之凸塊底層金屬層間的差異,在此情況下,可將緊鄰於凸塊之凸塊底層金屬層視為凸塊之一部分,即形成一凸塊連接底部。請再參考第1B圖,第1B圖為本發明實施例另一電子元件10之局部示意圖。
類似於第1A圖電子元件12的結構特徵,第1B圖中的電子元件10也包含有一基板100、一凸塊102、一凸塊底層金屬層104,且凸塊102與凸塊底層金屬層104之間還連接一凸塊連接底部BB(即箭頭所指處),據此,本實施例亦可僅包含單一的凸塊底層金屬層,而非用以限制本發明的範疇。
據此,針對不同電子產品或電子元件的實際需要,本實施例可適性選擇凸塊與至少一凸塊底層金屬層的材質,且設置於凸塊與基板間之凸塊底層金屬層的數量也可對應調整,以利後續之產品製造。
請繼續參考第1A圖與第1B圖,不論凸塊底層金屬層的數量多寡,本發明實施例係於緊鄰於凸塊的凸塊底層金屬層(或凸塊連接底部)形成一缺口結構,如第1A圖與第1B圖實施例中所圈之處。較佳地,本發明的缺口結構可用來提高凸塊與基板間之抗剪應力能力,以穩固凸塊與基板之耦接關係。再者,形成缺口結構之處亦可不限於緊鄰於凸塊的凸塊底層金屬層,將缺口結構形成緊鄰於凸塊的凸塊底層金屬層僅為較佳之實施例。相較於習知技術凸塊無法有效貼合或設置於驅動晶片上,本發明可改良凸塊與驅動晶片間之緊鄰凸塊底層金屬層(或凸塊連接底部BB)的結構設計,對應形成缺口結構,以大幅提高凸塊抵抗外來剪應力之抵抗能力。
請參考第2圖,第2圖為第1A圖中一電子元件12之俯視截面示意圖。如第2圖所示,本實施例中的缺口結構位於凸塊122貼合凸塊底層金屬層124之一平面上,即缺口結構位於與凸塊122相互緊鄰之凸塊底層金屬層124上。較佳地,從一俯視角度看去,凸塊122可投影於一平面上來形成一第一截面積,凸塊底層金屬層124可投影於該平面上來形成一第二截面積,而另一凸塊底層金屬層126
可投影於該平面上來形成一第三截面積,據此,凸塊122之第一截面積大於凸塊底層金屬層124之第二截面積,而另一凸塊底層金屬層126之第三截面積亦大於凸塊底層金屬層124之第二截面積。在此情況下,本實施例中的凸塊底層金屬層124所對應之截面積為最小,而凸塊122的截面積或凸塊底層金屬層126的截面積皆大於凸塊底層金屬層124之截面積,使得凸塊底層金屬層124投影的截面積都被凸塊122(或凸塊底層金屬層126)投影的截面積所包覆/圍繞;如果從單一維度來看,凸塊122之第一截面積包含有一第一長度與一第一寬度,凸塊底層金屬層124之第二截面積包含有一第二長度與一第二寬度,而凸塊底層金屬層126之第三截面積包含有一第三長度與一第三寬度,在此情況下,本實施例中凸塊底層金屬層124所對應之第二長度將小於凸塊122所對應之第一長度(或凸塊底層金屬層126所對應之第三長度),且凸塊底層金屬層124所對應之第二寬度也小於凸塊122所對應之第一寬度(或凸塊底層金屬層126所對應之第三寬度)。至於凸塊122之截面積與凸塊底層金屬層126之截面積(或第一截面積與第三截面積所對應之長度/寬度)的大小關係,可根據不同實施例來對應調整,非用以限制本發明的範疇。
再者,本實施例可透過一蝕刻操作來對應產生缺口結構,換言之,本實施例可對緊鄰凸塊之凸塊底層金屬層(或凸塊連接底部)進行一結構破壞程序,以對應於凸塊貼合於凸塊底層金屬層之一平面上形成缺口結構。請參考第3圖,第3圖為第1A圖中電子元件12產生缺口結構之流程圖。如第3圖所示,於步驟300到步驟308中,電子元件12的凸塊122以及凸塊底層金屬層124、126透過一系列的製造程序,對應形成且設置於基板120上,例如步驟300可設置一光阻層31與一鈍化層32,以對應於基板120上生成凸塊底層金屬層124、126;步驟302可進行一電鍍操作,以產生凸塊122;步驟304到步驟308可進行一連串之蝕刻/
剝離操作,以讓凸塊122以及凸塊底層金屬層124、126對應成型,且符合一預設產品之設計規格。
除此之外,為了加強電子元件12之抗剪應力能力,步驟310之蝕刻操作係於緊鄰凸塊122之凸塊底層金屬層124上進行結構破壞程序,並對應形成缺口結構。較佳地,本實施例可利用一濕蝕刻操作,以將電子元件12浸至一反應溶劑中來進行氧化還原反應,進而於緊鄰凸塊122之凸塊底層金屬層124上形成缺口結構。相較於步驟308中凸塊底層金屬層124的外觀結構,本實施例中完成步驟310濕蝕刻操作之凸塊底層金屬層124可對應於每一邊上後退至少0.5微米到1微米的距離,使得凸塊底層金屬層124所對應之截面積小於凸塊122與凸塊底層金屬層126之截面積,而形成所謂的缺口結構。當然,本領域具通常知識者亦可適性組合/替換本實施例中所舉例的濕蝕刻操作為其他類型的蝕刻操作,以對應於緊鄰凸塊之凸塊底層金屬層形成缺口結構者,皆屬於本發明的範疇;再者,缺口結構亦不限於形成於第3A圖的凸塊底層金屬層124處,通常之知識者亦能理解,缺口結構也能夠形成於第3A圖中的凸塊底層金屬層126處(圖中未示),換句話說,於另一實施例中,步驟310亦可對凸塊底層金屬層126進行蝕刻操作,以對應於凸塊底層金屬層126形成缺口結構,據此,凸塊底層金屬層126所對應的投影截面積(或投影截面積所對應之長度/寬度)將小於凸塊122與凸塊底層金屬層124所對應的投影截面積(或投影截面積所對應之長度/寬度),此皆屬於本發明的範疇。
請再參考第3B圖與第3C圖,其中第3B圖為第3A圖中步驟310完成後電子元件12之詳細示意圖,而第3C圖為第3A圖中步驟310完成後電子元件12之俯視截面示意圖。如第3B圖所示,若凸塊122沿一x軸方向有一第一長度L1(即凸
塊122投影之一最長寬度)且投影至第3C圖上可對應為一第一面積a1,而凸塊底層金屬層126貼附/接觸基板120之部分沿x軸方向有一第二長度L2(即凸塊底層金屬層126貼附/接觸基板120之部分所投影之一寬度)且投影至第3C圖上可對應為一第二面積a2。另外,第3B圖還包含有一放大圖C1,其可進一步顯示凸塊122、凸塊底層金屬層124與凸塊底層金屬層126間的設置方式,較佳地,沿x軸方向來看,凸塊底層金屬層124相較於凸塊122(或凸塊底層金屬層126)將內縮一長度m(即沿x軸方向,缺口結構所對應之長度),而沿一y軸軸方向來看,凸塊底層金屬層126包含有一厚度n。再者,如第3C圖所示,本實施例係類似於第2圖的俯視截面示意圖,兩者的差異在於第3C圖還示範性繪出完成後電子元件12的一凹槽結構,例如凸塊底層金屬層126還包含有一第一凹槽截面積A1,凸塊底層金屬層124還包含有一第二凹槽截面積A2,且第3C圖亦符合第2圖的實施方式,即第二凹槽截面積A2也可被第一凹槽截面積A1所包覆/圍繞,在此情況下,本實施例中凸塊底層金屬層124所對應之截面積(或凹槽截面積、截面積的長度與寬度)相對於凸塊122或凸塊底層金屬層126所對應之截面積(長度或寬度)為最小,進而提供凸塊相對於基板的較佳抗剪應力能力。
請參考第4圖,第4圖為本發明實施例中一電子元件產生缺口結構前或後所進行一剪應力試驗之比較圖。如第4圖所示,相較於未形成缺口結構之電子元件所進行的剪應力試驗,其所得到的剪應力大小為一第一剪應力,本實施例係於緊鄰凸塊之凸塊底層金屬層形成缺口結構,且其進行剪應力試驗後得到的剪應力大小為一第二剪應力,據此,由第4圖的比較圖可知第一剪應力將普遍小於第二剪應力,即本實施例所提供已形成缺口結構之電子元件將可承受較大的外來剪應力,具備有較強的抗剪應力能力,而不致使凸塊輕易剝離於基板。
進一步地,本實施例電子元件所適用之製造方法可歸納為一製造流
程50,且被編譯為程式碼而儲存於一製造機台之一儲存裝置中,以於電子元件製造過程中對應形成缺口結構且提高其抗剪應力能力,如第5圖所示,製造流程50包含以下步驟。
步驟500:開始。
步驟502:依序於基板上設置凸塊底層金屬層與凸塊。
步驟504:於凸塊底層金屬層進行蝕刻操作來形成缺口結構。
步驟506:結束。
簡言之,配合不同電子產品或電子元件之製造流程,本實施例中製造流程50所對應的程式碼可儲存於各類型製造機台的儲存裝置內,進一步,於完成步驟502之操作後(或者根據不同電子產品或電子元件所對應之各種複雜操作完成後),再額外進行步驟504的蝕刻操作,以於緊貼於凸塊之凸塊底層金屬層(或凸塊連接底部)形成缺口結構,進而加強各類型電子元件的抗剪應力能力。據此,已具備有缺口結構之電子元件可於後續切割、研磨或封包壓合操作中,提供較高的製造良率,且對應降低凸塊剝離基板(或驅動晶片)之可能。同時,對於驅動晶片縮小化之設計規格下,本實施例也能對應提供更彈性的布局設計,以於相同基板面積上容納/設置更多的佈線。至於缺口結構所對應之尺寸大小,本實施例可再搭配一操作者介面,並於步驟504進行前讓使用者進行一操作時間之設定,以對應調整蝕刻操作所對應之操作時間長短,亦屬於本發明的範疇。
當然,根據不同電子產品/元件之實際需求,凸塊底層金屬層的材質選擇與數量多寡可適性地進行調整,並讓凸塊與基板間多個凸塊底層金屬層堆疊形成一階梯狀結構,且由緊鄰凸塊之至少一凸塊底層金屬層設置有缺口結
構,即至少維持緊鄰凸塊之凸塊底層金屬層的截面積最小,至於其他凸塊底層金屬層或凸塊之截面積大小可適性地根據電子產品或電子元件來進行調整與修飾,非用以限制本發明的範疇。
綜上所述,本發明實施例係提供一種改良結構設計之電子元件與製造方法,於緊鄰凸塊之凸塊底層金屬層形成一缺口結構,以對應提高電子元件的抗剪應力能力,進而降低製造電子元件或相關切割、研磨或封包壓合操作的成本,同時提高製造電子元件的生產良率。以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
12‧‧‧電子元件
120‧‧‧基板
122‧‧‧凸塊
124、126‧‧‧凸塊底層金屬層
Claims (10)
- 一種電子元件,用於一電子產品,該電子元件包含有:一基板;一凸塊,設置於該基板上,用以電性連接該電子產品;以及至少一凸塊底層金屬(Under bump metal,UBM)層,設置於該凸塊與該基板間來讓該凸塊貼合於該基板;其中,該凸塊底層金屬層形成一缺口結構,該缺口結構位於該凸塊貼合該凸塊底層金屬層之一平面上,且從一俯視角度看去,該凸塊投影之一第一截面積大於該凸塊底層金屬層投影之一第二截面積。
- 如請求項1所述之電子元件,其中該凸塊之材質與該凸塊底層金屬層之材質為相同時,該凸塊底層金屬層形成該凸塊之一部分,或該凸塊之材質與該凸塊底層金屬層之材質為不相同時,該凸塊與該凸塊底層金屬層為堆疊設置之一金屬鍵結合體。
- 如請求項1所述之電子元件,其中於一蝕刻操作中,該凸塊底層金屬層進行一結構破壞程序,以對應於該凸塊貼合於該凸塊底層金屬層之一平面上形成該缺口結構。
- 如請求項1所述之電子元件,其包含另一凸塊底層金屬層,設置於該凸塊底層金屬與該基板間,且從一俯視角度看去,該另一凸塊底層金屬層投影之一第三截面積大於該凸塊底層金屬層投影之該第二截面積。
- 如請求項4所述之電子元件,其中該凸塊底層金屬層與該另一凸塊 底層金屬層係堆疊形成一階梯狀結構。
- 一種製造方法,用於一電子產品之一電子元件,其中該電子元件包含有一基板、一凸塊以及至少一凸塊底層金屬(Under bump metal,UBM)層,該製造方法包含有:依序於該基板上設置該凸塊底層金屬層與該凸塊;以及於該凸塊底層金屬層進行一蝕刻操作來形成一缺口結構,其中該缺口結構係位於該凸塊貼合該凸塊底層金屬層之一平面上,且從一俯視角度看去,該凸塊投影之一第一截面積大於該凸塊底層金屬層投影之一第二截面積。
- 如請求項6所述之製造方法,其中該凸塊之材質與該凸塊底層金屬層之材質為相同時,該凸塊底層金屬層形成該凸塊之一部分,或該凸塊之材質與該凸塊底層金屬層之材質為不相同時,該凸塊與該凸塊底層金屬層為堆疊設置之一金屬鍵結合體。
- 如請求項6所述之製造方法,其中該蝕刻操作對該凸塊底層金屬層進行一結構破壞程序,以對應於該凸塊貼合於該凸塊底層金屬層之一平面上形成該缺口結構。
- 如請求項6所述之製造方法,其還包含於該凸塊底層金屬與該基板間形成另一凸塊底層金屬層,且從一俯視角度看去,該另一凸塊底層金屬層投影之一第三截面積大於該凸塊底層金屬層投影之該第二截面積。
- 如請求項9所述之製造方法,其中該凸塊底層金屬層與該另一凸塊底層金屬層堆疊形成一階梯狀結構。
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US (2) | US9773746B2 (zh) |
JP (1) | JP6324361B2 (zh) |
KR (1) | KR101702975B1 (zh) |
CN (2) | CN106298711A (zh) |
TW (1) | TWI599276B (zh) |
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TWI599276B (zh) * | 2015-06-26 | 2017-09-11 | 矽創電子股份有限公司 | 電子元件與製造方法 |
CN110634828B (zh) * | 2018-06-21 | 2021-11-16 | 矽创电子股份有限公司 | 凸块结构 |
KR102617086B1 (ko) | 2018-11-15 | 2023-12-26 | 삼성전자주식회사 | Ubm을 포함하는 웨이퍼-레벨 반도체 패키지 |
US11410947B2 (en) * | 2019-12-19 | 2022-08-09 | Texas Instruments Incorporated | Brass-coated metals in flip-chip redistribution layers |
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JPS61141158A (ja) * | 1984-12-13 | 1986-06-28 | Fuji Electric Co Ltd | バンプ電極形成方法 |
JPH06177136A (ja) * | 1992-10-09 | 1994-06-24 | Nippondenso Co Ltd | バンプ電極をもつ回路装置 |
US6130141A (en) * | 1998-10-14 | 2000-10-10 | Lucent Technologies Inc. | Flip chip metallization |
US6570251B1 (en) * | 1999-09-02 | 2003-05-27 | Micron Technology, Inc. | Under bump metalization pad and solder bump connections |
US6258705B1 (en) * | 2000-08-21 | 2001-07-10 | Siliconeware Precision Industries Co., Ltd. | Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip |
TW560018B (en) | 2001-10-30 | 2003-11-01 | Asia Pacific Microsystems Inc | A wafer level packaged structure and method for manufacturing the same |
CN1437232A (zh) | 2002-02-05 | 2003-08-20 | 亚太优势微系统股份有限公司 | 晶片级封装的结构及其制作方法 |
TWI244184B (en) * | 2002-11-12 | 2005-11-21 | Siliconware Precision Industries Co Ltd | Semiconductor device with under bump metallurgy and method for fabricating the same |
TW577158B (en) * | 2002-11-29 | 2004-02-21 | Advanced Semiconductor Eng | Method for forming UBM pads and bumps on wafer |
JP2004235420A (ja) * | 2003-01-30 | 2004-08-19 | Seiko Epson Corp | 電子素子、電子素子の製造方法、回路基板、回路基板の製造方法、電子装置及び電子装置の製造方法 |
US7946331B2 (en) | 2005-06-14 | 2011-05-24 | Cufer Asset Ltd. L.L.C. | Pin-type chip tooling |
US7053490B1 (en) * | 2005-07-27 | 2006-05-30 | Semiconductor Manufacturing International (Shanghai) Corporation | Planar bond pad design and method of making the same |
TWI302370B (en) | 2006-05-24 | 2008-10-21 | Int Semiconductor Tech Ltd | Package structure for flip-chip compression |
JP2007317979A (ja) | 2006-05-29 | 2007-12-06 | Toshiba Corp | 半導体装置の製造方法 |
JP2009231681A (ja) * | 2008-03-25 | 2009-10-08 | Citizen Watch Co Ltd | 半導体装置およびその製造方法 |
KR20090106913A (ko) * | 2008-04-07 | 2009-10-12 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
TWI599276B (zh) * | 2015-06-26 | 2017-09-11 | 矽創電子股份有限公司 | 電子元件與製造方法 |
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KR101702975B1 (ko) | 2017-02-06 |
JP6324361B2 (ja) | 2018-05-16 |
US20160379949A1 (en) | 2016-12-29 |
CN114373730A (zh) | 2022-04-19 |
US20170345784A1 (en) | 2017-11-30 |
JP2017017302A (ja) | 2017-01-19 |
TW201701733A (zh) | 2017-01-01 |
US9773746B2 (en) | 2017-09-26 |
CN106298711A (zh) | 2017-01-04 |
KR20170001541A (ko) | 2017-01-04 |
US10163769B2 (en) | 2018-12-25 |
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