1302370 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種覆晶壓合封裝構造，特別係有關 於一種利用粗糙面增加抗剪強度及適用於超音波壓合之 覆晶壓合封裝構造。 【先前技術】 如第1圖所示，習知熱壓合封裝構造10係主要包含 一晶片11以及一基板12。該晶片11係具有一主動面110、 複數個銲墊111、複數個凸塊下金屬承座112 (UBM Pad) 以及複數個凸塊11 3，該些銲墊111係設置於該晶片11之 該主動面110，該些凸塊下金屬承座112係形成於該些銲 墊111上，而該些凸塊113係形成於該些凸塊下金屬承座 112上’該基板12係具有一上表面120、複數個連接墊121 以及複數個錫層122，該些連接塾121係設置於該基板11 之該上表面120 ’該些錫層122係形成於該些連接塾121 上。請參閱第2圖’該晶片11係與該基板12進行熱壓合， 該晶片11之該些凸塊113係與該基板12之該些錫層ι22 反應生成為一共晶接合層13，由於該些凸塊η]與該些錫 層122係分別形成於具有光滑表面之該些凸塊下金屬承座 112與該些連接墊丨21，故導致該些共晶接合層13形成後 係無法緊密連接該些凸塊下金屬承座112與該些連接墊 121，大幅降低該熱壓合封裝構造1〇之抗剪強度。此外， 該熱壓合封裝構造10因採用熱壓合方式連接該晶片^與 該基板12,故難以實現如超音波壓合方式所能達到之高精 1302370 度及細間距（Fine Pitch)之覆晶封裝。 【發明内容】. 本發明之主要目的係在於提供一種覆晶壓合封裝構 造’一壓合晶片係包含一晶片、複數個銲墊以及複數個凸 塊’該些銲墊係設置於該晶片之一主動面，且該些銲墊係 具有一第一粗糙面，該些凸塊係設置於該些銲墊之該些第 一粗糙面上，一壓合基板係包含一基板、複數個連接墊以 及複數個錫層，該些連接墊係設置於該基板之一上表面， 且該些連接塾係具有一第二粗糙:面，該些錫層係設置於該 些連接塾之该些第二粗糙面上，複數個接合層係連接該壓 合晶片之該些凸塊與該壓合基板之該些錫層。藉由該些第 一粗糙面與該些第二粗糙面可增加該覆晶壓合封裝構造 之抗剪強度及可靠度，而利用該接合層可實現以超音波壓 合連接該壓合晶片與該壓合基板，達到高精度及細間距 (Fine Pitch)之覆晶封裝。 本發明之次一目的係在於提供一種覆晶壓合封裝構 造’其中該些銲㈣該些凸塊之間係形成有複數個金屬承 座’該些金屬承座係、形成於該些銲墊之該些第—粗輪面 上’使該些金屬承座藉由該些第—粗糙面與該些鮮塾緊密 連接’該些金屬承座亦形成有—粗M表面，該些粗糖表面 係有助於該些凸塊與該些金屬承座之間的緊密連接。 依據本發明’一種覆晶壓合封裝構造主要包含一壓人 晶片、-壓合基板以及複數個接合層，該壓合晶片係包： -晶片、複數個銲墊及複數個凸塊，該些銲墊係設置於該 7 !3〇2370 晶片之一表面，且該些銲墊係具有一第一粗糙面，該些凸 塊係設置於該些銲墊之該些第一粗糙面上，該壓合基板係 包含一基板、複數個連接墊及複數個錫層，該些連接墊係 設置於該基板之一表面，該些錫層係設置於該些連接墊 上，該些接合層係連接該壓合晶片之該些凸塊與該壓合基 板之該些錫層。 【實施方式】 請參閱第3 Α及3Β圖，其係本發明之一具體實施例， 一種覆晶壓合封裝構造2〇主要包含一壓合晶片21、一壓 合基板22以及複數個接合層23。該壓合晶片21係包含一 晶片210、複數個銲墊211以及複數個凸塊212，該晶片 2 1 〇係具有一主動面210 A，該些銲墊2 11係設置於該晶片 210之該主動面210A，且該些銲墊211係具有一第一粗糖 面211A’該些凸塊212係設置於該些銲墊211之該些第一 粗糙面211A上，其中該些凸塊212係可為具有導電性之 金凸塊。在本實施例中，該些銲墊211與該些凸塊212之 間係形成有複數個金屬承座2 13，該些金屬承座2 1 3係形 成於該些銲墊211之該些第一粗糙面211A上，使該些金 屬承座213藉由該些第一粗糙面211A與該些銲塾211緊 选連接。較佳地，該些第一粗链面2 11A之平均粗縫度 (Average Roughness; Ra)係大於該些金屬承座213之厚 度，以使該些金屬承座213於該些第一粗糙面211A上形 成後，該些金屬承座213能對應該些銲墊211之該些第一 粗糙面211A而形成有一粗糙表面213A，該些粗糙表面 8 1302370 2 13A係有助於該些凸塊212與該些金屬承座' 213之間的 緊密連接。1302370 IX. Description of the Invention: [Technical Field] The present invention relates to a flip chip package structure, and more particularly to a flip chip for increasing the shear strength by using a rough surface and for supersonic pressing. Package construction. [Prior Art] As shown in Fig. 1, a conventional thermocompression package structure 10 mainly includes a wafer 11 and a substrate 12. The wafer 11 has an active surface 110, a plurality of pads 111, a plurality of under bump metal pads 112 (UBM Pad), and a plurality of bumps 113. The pads 111 are disposed on the wafer 11. The active surface 110, the under bump metal sockets 112 are formed on the pads 111, and the bumps 113 are formed on the under bump metal sockets 112. The substrate 12 has an upper surface. The surface 120, the plurality of connection pads 121, and the plurality of tin layers 122 are disposed on the upper surface 120 of the substrate 11. The tin layers 122 are formed on the connection pads 121. Referring to FIG. 2, the wafer 11 is thermally bonded to the substrate 12, and the bumps 113 of the wafer 11 are reacted with the tin layers ι 22 of the substrate 12 to form a eutectic bonding layer 13. The bumps η] and the tin layers 122 are respectively formed on the under bump metal sockets 112 and the connection pads 21 having a smooth surface, so that the eutectic bonding layers 13 are not formed tightly after being formed. Connecting the under bump metal sockets 112 and the connection pads 121 substantially reduces the shear strength of the thermocompression package structure. In addition, since the thermocompression package structure 10 is connected to the substrate 12 and the substrate 12 by thermocompression bonding, it is difficult to achieve a high precision of 1302370 degrees and a fine pitch (Fine Pitch) which can be achieved by the ultrasonic wave bonding method. Crystal package. SUMMARY OF THE INVENTION The main object of the present invention is to provide a flip-chip package structure [a press-fit wafer system comprising a wafer, a plurality of pads, and a plurality of bumps" disposed on the wafer. An active surface, and the pads have a first rough surface, the bumps are disposed on the first rough surfaces of the solder pads, and the pressed substrate comprises a substrate and a plurality of connecting pads And a plurality of tin layers, the connection pads are disposed on an upper surface of the substrate, and the connection lines have a second roughness: a surface, and the tin layers are disposed on the second portions of the connection ports On the rough surface, a plurality of bonding layers are connected to the bumps of the pressed wafer and the tin layers of the pressed substrate. The first rough surface and the second rough surfaces can increase the shear strength and reliability of the flip chip package structure, and the bonding layer can be used to ultrasonically connect the press wafer and The laminated substrate is a flip chip package with high precision and fine pitch (Fine Pitch). A second object of the present invention is to provide a flip-chip package structure in which a plurality of metal sockets are formed between the bumps, and the metal sockets are formed on the pads. The first-thickness of the first wheel surface causes the metal sockets to be tightly connected to the fresh shovel by the first rough surface. The metal sockets are also formed with a thick M surface, the coarse sugar surface system It facilitates the tight connection between the bumps and the metal sockets. According to the present invention, a flip chip package structure mainly comprises a stamper wafer, a press-bonded substrate and a plurality of bonding layers, the press wafer package: a wafer, a plurality of pads and a plurality of bumps, The pads are disposed on one surface of the 7·3〇2370 wafer, and the pads have a first rough surface, and the bumps are disposed on the first rough surfaces of the pads, The bonding substrate includes a substrate, a plurality of connection pads, and a plurality of tin layers. The connection pads are disposed on a surface of the substrate, and the tin layers are disposed on the connection pads, and the bonding layers are connected to the bonding layer The bumps of the wafer are pressed against the tin layers of the press substrate. [Embodiment] Please refer to Figures 3 and 3, which are a specific embodiment of the present invention. A flip-chip package structure 2A mainly comprises a press-bonded wafer 21, a laminated substrate 22 and a plurality of bonding layers. twenty three. The embossed wafer 21 includes a wafer 210, a plurality of pads 211, and a plurality of bumps 212. The wafer 2 1 has an active surface 210 A. The pads 2 11 are disposed on the wafer 210. The active surface 210A, and the solder pads 211 have a first rough surface 211A. The bumps 212 are disposed on the first rough surfaces 211A of the solder pads 211, wherein the bumps 212 are It is a gold bump with conductivity. In this embodiment, a plurality of metal sockets 2 are formed between the pads 211 and the bumps 212. The metal sockets 2 1 3 are formed on the pads 211. A rough surface 211A is used to connect the metal sockets 213 to the solder pads 211 by the first rough surfaces 211A. Preferably, the average roughness (Ra) of the first thick chain faces 2 11A is greater than the thickness of the metal sockets 213 such that the metal sockets 213 are on the first rough faces. After the 211A is formed, the metal holders 213 can form a rough surface 213A corresponding to the first rough surfaces 211A of the pads 211. The rough surfaces 8 1302370 2 13A contribute to the bumps 212. A tight connection with the metal sockets '213.
該壓合基板22係包含一基板220、複數個連接墊221 以及複數個錫層222,該基板220係具有一上表面220入， 該些連接墊221係設置於該基板220之該上表面220A， 且該些連接墊221係具有一第二粗糙面221A，該些錫層 222係設置於該些連接墊221之該些第二粗糙面221A上。 ^ 在本實施例中，該些連接墊221之該些第二粗糙面221A 與該些銲墊211之該些第一粗糙面211A係以研磨或蝕刻 方式製作，且該些錫層222係藉由該些第二粗糙面22 i a 與該些連接墊221緊密連接。請參閱第4圖，以超音波壓 合方式藉由該些接合層23連接該壓合晶片21之該些凸塊 212與該壓合基板22之該些錫層222，其中該些接合層23 係可形成於該壓合晶片21之該些凸塊212上（如第3A圖 所示）或形成於該壓合基板22之該些錫層222上（如第3B 私 圖所示）。 本發明係藉由該些銲墊2 11之該些第一粗糙面 211A’增加該些銲墊211與該些凸塊212之接合表面積， 以及藉由該些連接墊221之該些第二粗糙面221A，增加 。亥些連接墊221與該些錫層222之接合表面積，以提升該 壓合晶片21與該壓合基板22之間的接合強度，因此，可 增加該覆晶壓合封裝構造20之抗剪強度及可靠度。此外， w亥覆θ曰壓合封裝構造2 0亦藉由該接合層2 3實現以超音波 壓合方式連接該壓合晶片21之該些凸塊212與該壓合基 9 1302370 板22之該些錫層 之覆晶封裝。 222,以達到高精度及細 間距（Fine Pitch) 本發明之保護範圍當 者AM心 耗圓田視後附之申請專利範圍所界定 準，任何熟知此項技藝者，在不脫離本發明之精神和 乾圍内所作之任何變化與修改月之精神和 圍。 9屬於本發明之保護範 【圖式簡單說明】 第1圖：習知熱壓合封裝構造之截面示意圖。 圖· I知一晶片與一基板熱壓合後之截面示意 圖。 第3A至3B圖：依據本發明之一具體實施例，一種覆晶壓 合封裝構造之截面示意圖。 4 圖：依據本發明之一具體實施例，一壓合晶片 與一壓合基板超音波壓合後之截面示意 圖。 【主要元件符號說明】The laminated substrate 22 includes a substrate 220, a plurality of connection pads 221, and a plurality of tin layers 222. The substrate 220 has an upper surface 220. The connection pads 221 are disposed on the upper surface 220A of the substrate 220. The connection pads 221 have a second rough surface 221A, and the tin layers 222 are disposed on the second rough surfaces 221A of the connection pads 221 . In the embodiment, the second rough surfaces 221A of the connection pads 221 and the first rough surfaces 211A of the pads 211 are formed by grinding or etching, and the tin layers 222 are borrowed. The second rough surfaces 22 ia are tightly connected to the connection pads 221 . Referring to FIG. 4 , the bumps 212 of the pressed wafer 21 and the tin layers 222 of the pressed substrate 22 are connected by the bonding layer 23 in an ultrasonic bonding manner, wherein the bonding layers 23 The bumps 212 of the press-bonded wafer 21 (as shown in FIG. 3A) or the tin layers 222 of the press-bonded substrate 22 (as shown in FIG. 3B) may be formed. The first rough surface 211A of the solder pads 2 11 increases the bonding surface area of the solder pads 211 and the bumps 212, and the second roughness of the connecting pads 221 Face 221A, increase. The bonding surface area of the connection pads 221 and the tin layers 222 is increased to increase the bonding strength between the bonding wafer 21 and the pressing substrate 22, thereby increasing the shear strength of the flip chip bonding structure 20. And reliability. In addition, the w θ 曰 曰 封装 package structure 20 is also connected to the embossed wafers 21 and the embossed substrates 9 130 2 370 22 by ultrasonic bonding. The tin layers are packaged in a flip chip. 222, in order to achieve high precision and fine pitch (Fine Pitch) The scope of protection of the present invention is defined by the scope of the patent application of the AM heart consumption, and anyone skilled in the art can not deviate from the spirit of the present invention. And any changes made in the Wai Wai and the spirit and circumference of the month. 9 is a protection model of the present invention [Simplified description of the drawings] Fig. 1 is a schematic cross-sectional view of a conventional thermocompression package structure. Figure I shows a cross-sectional schematic view of a wafer and a substrate after thermocompression bonding. 3A-3B are schematic cross-sectional views of a flip chip package structure in accordance with an embodiment of the present invention. 4 is a cross-sectional schematic view of a press-fit wafer superimposed with a press-fit substrate in accordance with an embodiment of the present invention. [Main component symbol description]
10 熱壓合封裝構造 11 晶片 110 112 凸塊下金屬 承座 12 基板 120 122 錫層 13 20 覆晶壓合封裝構造 21 壓合晶片 210 211 銲墊 211A 主動面 111 銲墊 113 凸塊 上表面 121 連接墊 共晶接合層 晶片 210A 主動面 第一粗糙面 212 凸塊 1302370 213 金屬承座 213A 粗糙表面 22 壓合基板 220 基板 220A上表面 221 連接墊 221A 第二粗链面 222 錫層 23 接合層10 thermocompression package structure 11 wafer 110 112 under bump metal socket 12 substrate 120 122 tin layer 13 20 flip chip package structure 21 press wafer 210 211 pad 211A active surface 111 pad 113 bump upper surface 121 Connection pad eutectic bonding layer wafer 210A active surface first rough surface 212 bump 1302370 213 metal socket 213A rough surface 22 laminated substrate 220 substrate 220A upper surface 221 connection pad 221A second thick chain surface 222 tin layer 23 bonding layer
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