本發明是有關於一種覆 一種覆晶封裝結構，其利用 底膠材料之流速，因而減少 晶封裝結構，且特別是有關於 擾流凸條來降低晶片之周緣的 空孔（void)產生的機率。 ^ 覆晶接合技術（Flip Chip Bonding Technology，簡 稱FC)是一種將晶片（die)連接至承載器（carrier)二 封哀技術，其主要是利用面陣列（a r e a a r r a y )的方式， 將多個晶片墊（die pad )配置於晶片之主動表面 (active surface)上，並在晶片墊上形成凸塊（bump _ )’接著將晶片翻覆（f 1 i p )之後，再經由這些凸塊，將 晶片之這些晶片墊分別電性（e i eC t r } ca J i y )及機械性 (mechanically)連接至承載器上的接點（contact)， 使得晶片可經由凸塊而電性連接至承載器，再經由承栽器 之内部線路而電性連接至外界之電子裝置。由於覆晶接合 技術（FC )可適用於高腳數（High Pin Count )之晶片封 裝結構，並同時具有縮小晶片封裝面積及縮短訊號傳輪路 徑等諸多優點，使得覆晶接合技術目前已經廣泛地應用於 晶片封裝領域。. _ 就覆晶接合技術（F C )而言，當承載器係採用以有機 材質（organic material)作為介電層之載板 (substrate )時，由於晶片與載板之間熱膨脹係數 (Coefficient of Thermal Expansion，CTE)略有差 異，所以晶片在經由多個凸塊連接至載板之表面以後，更The invention relates to a chip-on-chip packaging structure, which uses the flow rate of the primer material, thereby reducing the chip packaging structure, and particularly relates to a spoiler rib to reduce the probability of voids generated on the periphery of the wafer. . ^ Flip Chip Bonding Technology (FC) is a two-sealing technology that connects a die to a carrier. It mainly uses an area array to place multiple wafer pads. (Die pad) is disposed on the active surface of the wafer, and bumps (bump_) 'are formed on the wafer pad. After the wafer is overturned (f 1 ip), the wafers are passed through the bumps. The pads are electrically (ei eC tr} ca J iy) and mechanically connected to the contacts on the carrier, so that the chip can be electrically connected to the carrier through the bump, and then through the carrier. The internal circuit is electrically connected to the external electronic device. As the flip chip bonding technology (FC) can be applied to the high pin count (High Pin Count) chip packaging structure, and has many advantages such as reducing the chip packaging area and shortening the signal transmission path, the flip chip bonding technology has been widely used so far. Used in the field of chip packaging. _ In terms of flip-chip bonding technology (FC), when the carrier uses a substrate with an organic material as the dielectric layer, the coefficient of thermal expansion between the wafer and the substrate (Coefficient of Thermal) Expansion (CTE) is slightly different, so after the chip is connected to the surface of the carrier board through multiple bumps, the
11181twf.ptd 第5頁 1223421 五、發明說明（2) 必/頁進行底膠填充製程（underfill dispense process )’將底膠材料（underfill material)填入晶片、載板 與凸塊之間所圍成的空間，用以降低晶片與載板之間熱應 力（thermal stress )集中的程度，特別是在晶片之周緣 區域，故可有效降低在多次熱膨脹循環（thermal expanding cycle)之後，凸塊之本身發生斷裂的機率， 例如在凸塊與晶片之接合處發生斷裂，或是在凸塊與載板 之間的接合處發生斷裂。 請參考第1圖，其搶示習知之一種覆晶封裝結構，其 尚未填入底膠的側視圖。覆晶封裝結構丨〇 〇主要包括晶片馨 110、載板120及多個凸塊130。晶片11〇具有一主動表面 112，其上配置有多個晶片墊（未繪示），而載板12〇具有 一承載平面1 22，其上配置有多個接合墊（未繪示），且 這些凸塊1 3 0係以面陣列的方式加以排列，並個別地配置 於晶片110之主動表面112及載板12〇之承載平面122之間， ，以將晶片110電性及機械性連接至載板12〇。值得注意的 是，在晶片110覆晶接合至載板丨2〇之後，通常會進行一底 膠填充製程，其主要是利用毛細現象（capilUrity)的一 原理，將底膠材料150緩慢地填入晶片11〇、載板12〇與這钃 些凸塊130所圍成之空間。 請同時參考第i、2圖，其中第2圖緣示第】圖之覆晶封 裝結構，其正在進行底膠填充製程的俯視圖。如第i、2圖 晶片110之主動表面112可區*為接合區域n2a及非 接合區域H2b，同樣地載板120之承載表面122亦可區分為11181twf.ptd Page 5 1223421 V. Description of the invention (2) The underfill dispense process must be performed per page. 'The underfill material is filled between the wafer, the carrier board and the bump. Space to reduce the concentration of thermal stress between the wafer and the carrier, especially in the peripheral area of the wafer, so it can effectively reduce the bump itself after multiple thermal expanding cycles The probability of breakage, for example, breakage at the junction between the bump and the wafer, or breakage at the junction between the bump and the carrier. Please refer to FIG. 1 for a side view of a conventional flip-chip packaging structure which has not been filled with primer. The flip-chip packaging structure includes a wafer 110, a carrier board 120, and a plurality of bumps 130. The wafer 11 has an active surface 112 on which a plurality of wafer pads (not shown) are disposed, and the carrier plate 120 has a load plane 1 22 on which a plurality of bonding pads (not shown) are disposed, and These bumps 130 are arranged in an area array and are individually arranged between the active surface 112 of the wafer 110 and the carrier plane 122 of the carrier board 120 to electrically and mechanically connect the wafer 110 to Carrier board 120. It is worth noting that after the wafer 110 is flip-chip bonded to the carrier board 20, a primer filling process is usually performed, which mainly uses the principle of capilUrity to fill the primer material 150 slowly. The space surrounded by the wafer 110, the carrier plate 120, and the bumps 130. Please refer to Figures i and 2 at the same time, where Figure 2 shows the flip-chip packaging structure in Figure 2. The top view of the underfill process is underway. As shown in Figures i and 2, the active surface 112 of the wafer 110 can be divided into the bonding area n2a and the non-bonding area H2b. Similarly, the carrying surface 122 of the carrier plate 120 can also be divided into
1223421 五、發明說明（3) 接合區域12 2a、非接合區域丨2 2b及其他區域（未標示）， 而這些凸塊130係配置於主動表面丨12之接合區域丨12a及承 載表面122之接合區域122a。一般而言，晶片之主動表面 的非接合區域通常都設計得很窄小，以提高主動表面之面 積利用率，但對於某些特殊設計的晶片，例如第1、2圖所 示之晶片11 0，其主動表面11 2之非接合區域11 2b卻相當地 大。 承上所述，當這樣的晶片11 〇在進行底膠填充製程 時，即將底膠材料1 50沿著箭頭方向1 0填入晶片11 0、載板 120及凸塊130所圍成的空間時’由於底膠材料15〇於非接_ 合區域1 1 2 b ( 1 2 2 b )所受到的阻力很小，造成底膠材料 150於非接合區域112b (122b)之流速將大於底膠材料15〇 於接合區域112a ( 1 22a )之流速，使得位於晶片11〇之右 側的底膠材料150將從非接合區域11 2b (122b)回流至接 合區域112a ( 122a )，因而導致空孔的產生，進而降低底 膠填充製程之良率。 潑^明内容 有鑑於此，本發明之目的就是在提供一種覆晶封裝結 構，其主要是利用擾流凸條來降低底膠材料於晶片之非接· 合區域的流速，用以降低空孔產生的機率，因而提高底膠 填充製程之良率。 為達本發明之上述目的，本發明提出一種覆晶封裝結 構，其至少包括一晶片、一載板、多個凸塊、多個擾流凸 條及一底膠材料。其中，晶片具有一主動表面，且此主動1223421 V. Description of the invention (3) Bonding area 12 2a, non-bonding area 2 2b and other areas (not labeled), and these bumps 130 are arranged on the active surface 12 of the bonding area 12 and the bonding of the bearing surface 122 Area 122a. Generally speaking, the non-bonding area of the active surface of a wafer is usually designed to be narrow to improve the area utilization of the active surface. However, for some specially designed wafers, such as the wafer shown in Figures 1 and 2 However, the non-joint area 11 2b of the active surface 112 is quite large. As mentioned above, when such a wafer 110 is underfilled, that is, when the primer material 150 is filled into the space surrounded by the wafer 110, the carrier plate 120 and the bump 130 in the direction of the arrow 10. 'Because the primer material 15 has a small resistance in the non-joining area 1 1 2 b (1 2 2 b), the flow rate of the primer material 150 in the non-joining area 112 b (122 b) will be greater than the primer material. The flow rate of 150 in the bonding area 112a (122a) causes the primer material 150 located on the right side of the wafer 110 to reflow from the non-bonding area 11 2b (122b) to the bonding area 112a (122a), thereby causing voids , Thereby reducing the yield of the primer filling process. In view of this, the object of the present invention is to provide a flip-chip package structure, which mainly uses spoiler ribs to reduce the flow rate of the primer material in the non-joining and joining areas of the wafer to reduce the occurrence of voids. Probability, thereby improving the yield of the primer filling process. In order to achieve the above object of the present invention, the present invention provides a flip-chip packaging structure, which at least includes a wafer, a carrier board, a plurality of bumps, a plurality of spoiler ribs, and a primer material. The chip has an active surface, and the active surface
11181twf.ptd 第7頁 1223421 五、發明說明（4) 表面具有一第 接合區域係位 承載表面，且 接合區域，而 側。另外，這 域之間，且晶 且，這些擾流 區域。而且， 這些擾流凸條 依照本發 度方向與晶片 度。此外，上 化石夕、金屬或 基於上述 區域或是載板 凸條，故在將 能夠藉由這些 合區域的流速 接合區域的流 機率，進而提 為讓本發 下文特舉一較 下·· 真·^方式 一接合區 於第一接 此承载表 第二非接 些凸塊係 片係經由 凸條係配 底膠材料 所圍成之 明的較佳 之側邊所 述之者些 防銲材料 ’本發明 之承載表 底膠材料 擾流凸條 ’使得底 速大致相 高底膠填 明之上述 佳實施例 域及一 合區域 面具有 合區域 配置於 這些凸 置於第 係填充 空間。 實施例 構成的 擾流凸 第 非接合區域，而第一 之周側。此外，載板具有一 一第二接合區域及一第二非 係位於第二接合區域之周 第一接合區域及第二接合區 塊而電性連接至載板。並 一非接合區域或第二非接合 於晶片、載板、這些凸塊及 所述’上述之擾流凸條之長 夾角其範圍係為8 〇〜1 〇 〇 條之材質係可為氧化矽、氮 主要是在晶片之主動表面的非接合 面的非接合區域上配設有多個擾流 填入晶片及載板之間的過程期間， 來降低底膠材料在流經晶片之非接 膠材料在流經晶片之接合區域及非 同，故可降低底膠材料形成空孔 充製程之良率。 目的、特徵和優點能更明顯易懂， ，並配合所附圖式，作詳細說明如11181twf.ptd Page 7 1223421 V. Description of the invention (4) The surface has a first joint area system bearing surface, and the joint area is on the side. In addition, between these domains, and crystals, these turbulent regions. Moreover, these spoiler ridges follow the direction of the hair and the degree of the wafer. In addition, the upper fossils, metal, or base strips based on the above areas, so the flow rate of these areas can be joined by the flow rate of these areas, and then referred to the following for the sake of ... · ^ One way is to connect the bonding area to the first non-connected bumper sheet. The soldering material is the one on the side of the brighter side surrounded by the ribs and the primer material. According to the present invention, the spoiler ridges for carrying the surface primer material make the base speed substantially higher than that of the above-mentioned preferred embodiment. The surface and the combination area have a combination area disposed on these convex spaces. The embodiment constitutes the spoiler convex second non-joined area, and the first peripheral side. In addition, the carrier board has a second joint region and a second joint region, and the first joint region and the second joint block are electrically connected to the carrier board. And a non-joint region or a second non-joint to the wafer, the carrier board, the bumps and the long angle between the above-mentioned spoiler ribs, the range of which is from 80 to 100; the material may be silicon oxide Nitrogen is mainly provided on the non-bonding area of the non-bonding surface of the active surface of the wafer with a plurality of turbulences filled between the wafer and the carrier during the process to reduce the primer material flowing through the non-bonding of the wafer. The material is different in the bonding area flowing through the wafer, so it can reduce the yield of the filling process of the primer material to form the hole. The purpose, characteristics and advantages can be more clearly understood, and in conjunction with the attached drawings, detailed descriptions such as
11181twf.ptd 第8頁 1223421 五、發明說明（5) 二同時參考第3、4 A圖，其中第3圖繪示本發明之 、4B圖繪示第3圖之覆晶封裝結構，其正在進行底 膠填充製程的俯視圖。覆晶封裝結構2GG主要包括晶片· 210、載板220、多個凸塊230及多個擾流凸條24()。首 晶片210具有一主動表面212，丨中主動表面212包括一接 合區域2 12a及一非接合區域212b，而非接合區域以礼係位 於接合區域2 12a之周侧，且接合區域212a係配置有多個晶 片墊（未繪示）。此外，載板220具有一承載平面222，= 中承載平面222亦包括一接合區域2 223及一非接合區域/、 222b，而非接合區域222b係同樣位於接合區域222a之周 側，且接合區域222a係配置有多個接合墊（未繪示）。另 外’這些凸塊2 3 0係以面陣列的方式加以排列，如第4 a圖 所示，並個別地配置於晶片21〇之主動表面212及載板22() 之承載平面2 2 2之間，用以將晶片2 1 〇電性及機械性連接至 載板220。 請同時參考第3、4 A圖，擾流凸條2 4 0係配置於載板 22 0之承載表面222的非接合區域22 2b，其排列方式如第4八 圖所示，而這些擾流凸條2 4 0係群聚地配置於這些凸塊2 3 〇麵丨 之周側，且這些擾流凸條240之長度方向係分別相應地垂 直於晶片21 0之四個側邊，意即個別擾流凸條2 4 〇之長度方 向與晶片210 (或接合區域222a)之側邊所構成的失角其 範圍係為80〜100度。然後，在晶片210經由這些凸塊 2 3 0 ’覆晶接合至載板2 2 0之後，利用毛細現象11181twf.ptd Page 8 1223421 V. Description of the invention (5) Secondly refer to Figures 3 and 4 A, where Figure 3 shows the present invention, and Figure 4B shows the flip-chip packaging structure of Figure 3, which is in progress Top view of the primer filling process. The flip-chip package structure 2GG mainly includes a wafer 210, a carrier board 220, a plurality of bumps 230, and a plurality of spoiler ribs 24 (). The first chip 210 has an active surface 212. The middle active surface 212 includes a bonding region 2 12a and a non-bonding region 212b. The non-bonding region is located on the peripheral side of the bonding region 2 12a in a polite manner. Multiple wafer pads (not shown). In addition, the carrier board 220 has a bearing plane 222, the middle bearing plane 222 also includes a joint region 2 223 and a non-joint region / 222b, and the non-joint region 222b is also located on the peripheral side of the joint region 222a, and the joint region 222a is provided with a plurality of bonding pads (not shown). In addition, these bumps 2 3 0 are arranged in a surface array manner, as shown in FIG. 4 a, and are individually arranged on the active surface 212 of the wafer 21 and the bearing plane 2 2 2 of the carrier plate 22 (). For electrically and mechanically connecting the chip 210 to the carrier board 220. Please refer to FIGS. 3 and 4A at the same time. The spoiler ridges 2 40 are arranged on the non-joint area 22 2b of the bearing surface 222 of the carrier plate 22 0. The arrangement is shown in FIG. 4 and FIG. The convex strips 2 4 0 are clustered and arranged on the peripheral sides of the convex 2 3 0 planes, and the length directions of the spoiler convex strips 240 are respectively perpendicular to the four sides of the wafer 2 0, which means that The misalignment angle between the longitudinal direction of the individual spoiler ridges 2 40 and the side of the wafer 210 (or the bonding area 222a) ranges from 80 to 100 degrees. Then, after the wafer 210 is bonded to the carrier board 2 2 0 through these bumps 2 3 0 ′, the capillary phenomenon is used.
1223421 五、發明說明（6) 2;marty'，原、理，將底膠材料250緩慢地填入晶片 ^ 反20、这些凸塊23〇及這些擾流凸條240所圍成之 至間。 口月參考第4 A圖’與—般晶片相較之下，由於晶片2 j 〇 =動表面212的非接合區域2m較大，因此，當這樣的 !θ 2 1 0在進彳丁底膠填充製程時，即將底膠材料2 5 〇沿著箭 ，方向20填入晶片210、載板22〇、這些凸塊23〇及這些擾 二^條240所圍成的空間時，可以利用這些擾流凸條24〇來 H回底膠材料25G在流經非接合區域212b ( 222b )之阻 =，使彳于底膠材料250流經非接合區域212b ( 222b)之底馨 =材料2 50的流速，其與流經接合區域212&( 222&)之底 膠材料250的流速大致相同，使得底膠材料25〇能夠從晶片 21 0之左側’而均勻地流到晶片2丨〇之右半部下方，故可有 效地降低在晶片2 1 0之右半部下方形成空孔的機率。 請參考第4A、4B圖，如第4A圖所示，這些擾流凸條 2 4 0除了分佈在晶片2 1 〇之四個側邊以外，這些擾流凸條 24 0亦可僅分佈於晶片2 1 〇之上下側邊，如第4B圖所示。因 此’當底膠材料2 5 0沿著箭頭方向2 〇流入晶片2 1 〇與載板 2 2 0之間，並流經晶片2 1 〇之上下兩側的部分非接合區域 _ 22 2b時，可利用這些擾流凸條24〇來降低底膠材料25〇之流 速’使得底膠材料250在晶片210之產生空孔的機率可大幅 降低。 請依序參考第5A〜5C圖，其中第5A圖繪示第3圖之覆 晶封裝結構，其已填入底膠的剖面圖，而第5B圖繪示本發1223421 V. Description of the invention (6) 2; marty ', original and physical, slowly fill the base material 250 into the wafer ^ Anti 20, the bumps 23 and the spoiler strips 240 are surrounded by them. Compared with the general wafer, reference is made to Fig. 4A. As the wafer 2 j 〇 = the non-joint area 2m of the moving surface 212 is larger, when such! Θ 2 1 0 During the filling process, that is, when the primer material 2 50 is filled in the space surrounded by the wafer 210, the carrier 22, the bumps 23, and the interference bars 240 along the arrow 20, these interferences can be used. The resistance of the convex strips 24 to 25 to the base adhesive material 25G when flowing through the non-joined area 212b (222b) =, so that the base rubber material 250 flows through the non-joined area 212b (222b). The flow rate is substantially the same as the flow rate of the primer material 250 passing through the bonding area 212 & (222 &), so that the primer material 250 can flow uniformly from the left side of the wafer 21 to the right half of the wafer 2 丨 0. Lower portion of the wafer, so the probability of forming voids under the right half of the wafer 210 can be effectively reduced. Please refer to Figs. 4A and 4B. As shown in Fig. 4A, in addition to the spoiler ridges 2 40 being distributed on the four sides of the wafer 2 10, the spoiler ridges 24 0 can also be distributed only on the wafer. 2 1 〇 The upper and lower sides, as shown in Figure 4B. Therefore, 'When the primer material 2 50 flows into the wafer 2 1 0 and the carrier 2 2 0 in the direction of the arrow 20 and flows through the part of the non-bonded area _ 22 2b on the upper and lower sides of the wafer 2 1 0, These spoiler strips 240 can be used to reduce the flow rate of the primer material 250, so that the probability that the primer material 250 generates voids in the wafer 210 can be greatly reduced. Please refer to Figures 5A to 5C in sequence, where Figure 5A shows the flip-chip package structure of Figure 3, which has been filled with a cross-section of the primer, and Figure 5B shows the hair
11181twf.ptd 第10頁 1223421 五、發明說明（7) 明之較佳實施例之第二種覆晶封裝結構的剖面圖，且第％ 圖繪示本發明之較佳實施例之第三種覆晶封裝結構的 圖。 。 首先，如第5Α圖所示，在覆晶封裝結構2〇2之中，擾 流凸條240係配置於載板220之承載表面222的非接合區域 2 2 2 b ’用以降低底膠材料2 5 0流經非接合區域2 2 2 b之流 速。此外，如第5B圖所示，在覆晶封装結構2〇4之中，擾 流凸條240亦可配置於晶片210之主動表面212的非接合區 域212b，這樣的設計亦可降低底膠材料25〇在流經非&合 區域2 12b之流速，其中這些擾流凸條240在晶片21〇上之排_ 列方式如同於其在載板2 2 0上之排列方式，於此不多贅 述。另外，如第5C圖所示，在覆晶封裝結構2〇6之中，可 將擾流凸條2 4 0同時配置於晶片2 1 〇之主動表面2 1 2的非接 合區域212b及載板220之承載表面222的非接合區域222b， 這樣的設計亦可降低底膠材料250於流經非接合區域2 12b 及非接合區域222b之流速。最終，在擾流凸條24〇的擾流 作用之下’底膠材料250在晶片21 0及載板220之間形成空 孔的機率將可大幅降低。 請同樣參考第5C圖，當擾流凸條24〇係配置於載板22〇 _ 之承載表面2 2 2的非接合區域2 2 2 b時，可利用載板2 2 0之防 銲層（solder mask)(未繪示）來直接形成這些擾流凸 條2 4 0，故可在製作載板2 2 0之防銲層的同時，一併將這些 擾流凸條240製作於載板220之承載表面222，所以擾流凸 條2 4 0之材質係可包括防銲材料。11181twf.ptd Page 10 1223421 V. Description of the invention (7) A cross-sectional view of the second flip-chip package structure of the preferred embodiment of the invention, and the% chart shows the third flip-chip of the preferred embodiment of the present invention Diagram of package structure. . First, as shown in FIG. 5A, in the flip-chip package structure 202, the spoiler ridge 240 is disposed on the non-joint area 2 2 2 b of the carrier surface 220 of the carrier board 220 to reduce the primer material. The flow rate of 2 50 passing through the non-joining area 2 2 2 b. In addition, as shown in FIG. 5B, in the flip-chip package structure 204, the spoiler ridges 240 can also be arranged in the non-joined area 212b of the active surface 212 of the chip 210. This design can also reduce the primer material The flow rate of 25 ° through the non-amp region 2 12b, in which the spoiler ridges 240 are arranged on the wafer 21 ° is the same as that on the carrier plate 2 2 0, not much here To repeat. In addition, as shown in FIG. 5C, in the flip-chip package structure 206, spoiler ridges 2 40 can be simultaneously disposed on the non-bonding area 212b of the active surface 2 1 2 of the chip 2 10 and the carrier board. The design of the non-joined region 222b of the bearing surface 222 of 220 can also reduce the flow velocity of the primer material 250 through the non-joined region 2 12b and the non-joined region 222b. In the end, under the effect of the turbulence of the spoiler ridge 24, the probability that the primer material 250 forms a hole between the wafer 210 and the carrier plate 220 can be greatly reduced. Please also refer to FIG. 5C. When the spoiler 24 is disposed on the non-joining area 2 2 2 b of the bearing surface 2 2 2 of the carrier plate 22 0_, a solder resist layer of the carrier plate 2 2 0 ( solder mask) (not shown) to directly form these spoiler ridges 2 4 0, so while making the solder mask of the carrier plate 2 2 0, these spoiler ridges 240 are also fabricated on the carrier plate 220 The load-bearing surface 222, so the material of the spoiler strip 2 40 may include a solder resist material.
11181twf.ptd 第11頁 1223421 五、發明說明（8) 請同樣參考第5 C圖，當擾流凸條2 4 0係配置於晶片2 1 0 之主動表面2 1 2的非接合區域2 1 2 b時，可利用晶片2 1 〇之保 護層（passivation)或凸塊底金屬層（Under Ban Metallurgy ’UBM)(均未繪示）來直接形成這些擾流凸 條240，故可在製作晶片21〇之保護層或凸塊底金屬層 (UBM )的同時，一併將這些擾流凸條24〇製作於晶片21Q 之主動表面212。其中，當擾流凸條24〇係由保護層所形成 時，這些擾流凸條240之材質係可相同於保護層之材質， 例如氧化梦或氮切。&外，#擾流凸條24()係由凸塊底 金屬層（UBM )所形成時，這些擾流凸條24〇之 同於凸塊底金屬層之材質，即金屬。11181twf.ptd Page 11 1223421 V. Description of the invention (8) Please also refer to Figure 5C. When the spoiler 2 4 0 is arranged on the active surface 2 1 2 of the chip 2 1 2 non-joined area 2 1 2 At b, these spoiler ribs 240 can be directly formed by using a passivation of the wafer 2 10 or an under ban metallurgy 'UBM (neither of which is shown). At the same time as the protection layer or the bump bottom metal layer (UBM) of 〇, these spoiler strips 24 are fabricated on the active surface 212 of the wafer 21Q. Among them, when the spoiler ridges 240 are formed of a protective layer, the material of the spoiler ridges 240 may be the same as that of the protective layer, such as an oxide dream or nitrogen cutting. & In addition, when the spoiler ridges 24 () are formed by a bump bottom metal layer (UBM), these spoiler ridges 24 are the same as the material of the bump bottom metal layer, that is, metal.
片之主 區域上 載板之 材料在 經接合 材料形 雖 以限定 神和範 護範圍 上所述， 動表面的 配設有多 間的過程 流經晶片 區域及非 成空孔的 然本發明 本發明， 圍内，當 當視後附 ^ /十、贯听 非接合區 個擾流凸 期間，能 之非接合 接合區域 機率，進 已以—車交 任何熟習 可作些許 之申請專 之覆晶封 域或是載 條，故在 夠藉由這 區域的流 的流速大 而提南底 佳實施例 此技藝者 之更動與 利範圍所 裝結構中 板之承載 將底膠材 些擾流凸 速，使得 致相同， 膠填充製 揭露如上 ’在不脫 潤飾，因 界定者為 ，主要 表面的 料填入 條來降 底膠材 故可降 程之良 ，然其 離本發 此本發 準。 是在晶 非接合 晶片及 低底膠 料在流 低底膠 率〇 並非用 明之精 明之保In the main area of the film, the material of the board is described in the shape of the bonded material to limit the scope of the god and the protection. The dynamic surface is provided with multiple processes that flow through the wafer area and the non-empty holes. Within the range, Dangdang attaches ^ / 10, listening to the non-joint zone during a spoiler, the probability of the non-joint joint zone, has been taken into account-any familiar with the car can apply for a special application of the flip-chip sealing domain or It is a carrier strip, so that the flow rate in this area can be large enough to improve the performance of this embodiment. The load of the board in the structure installed by this artist will increase the velocity of the bottom glue material, causing the Similarly, the glue-filled system is exposed as above. It is not retouched. Because it is defined as the main surface of the material to fill the strip to lower the bottom of the rubber material, it can be a good range, but it is accurate. It is in the crystal, the non-bonding wafer and the low-base rubber are flowing. The low-base rubber rate is not used.
1223421 圖式簡單說明 =圖繪示習知之一種覆晶封裝結構，其尚未填入 底 膠的側視圖㈠示第1圖之覆晶封袭結構，其正在進行底 充製程的俯視圖。 第3圖繪示本發明之較伟每 構，其尚未填入底膠的側視圖…之一種覆晶封裝結 第4A、4B圖繪示第3圖之覆晶封裝結構，其正 底膠填充製程的俯視圖。 苐5 A圖繪示第3圖之覆晶驻έ士接 復日日封裝結構，其已填入底 刮曲圖。 第5 Β圖繪示本發明 構的剖面圖。 第5C圖繪不本發明之較佳實施例之第三種覆晶封裝結 構的剖面圖。 膠填 進行 膠的 之較佳實施例之第二種覆晶封裝結 【圖式標示說明】 1 0、2 0 :箭頭方向 I 0 0 :覆晶封裝結構 II 0 :晶片 11 2 :主動表面 11 2 a .接合區域 112b :非接合區域 120 :載板 1 2 2 :承載表面 1223421 圖式簡單說明 122a :接合區域 122b :非接合區域 1 3 0 :凸塊 1 5 0 :底膠材料 2 0 0、2 0 2、2 0 4、2 0 6 :覆晶封裝結構 2 1 0 :晶片 212 :主動表面 212a :接合區域 212b :非接合區域 220 :載板 2 2 2 :承載表面 222a :接合區域 222b :非接合區域 « 230 ： 凸塊 240 ： 擾流凸條 250 ： 底膠材料 11181twf.ptd 第14頁1223421 Brief description of the drawing = The drawing shows a conventional flip-chip packaging structure, which has not been filled with the primer. The side view shows the flip-chip mounting structure of Figure 1, which is a top view of the underfill process. Fig. 3 shows a side view of the relatively robust structure of the present invention, which has not been filled with primer. A flip-chip package junction. Figs. 4A and 4B show the flip-chip package structure of Fig. 3, which is filled with positive primer. Top view of the process. Figure 5A shows the flip chip package structure of Figure 3, which has been filled in the bottom scratch curve. Figure 5B is a cross-sectional view of the structure of the present invention. FIG. 5C illustrates a cross-sectional view of a third flip-chip package structure according to a preferred embodiment of the present invention. The second type of flip-chip packaging junction of the preferred embodiment of the glue-filling method [illustrated by drawing] 1 0, 2 0: arrow direction I 0 0: flip-chip packaging structure II 0: wafer 11 2: active surface 11 2 a. Bonding area 112b: Non-bonding area 120: Carrier board 1 2 2: Bearing surface 1223421 Brief description of the drawing 122a: Bonding area 122b: Non-bonding area 1 3 0: Bump 1 5 0: Primer material 2 0 0 , 2 0 2, 2 0 4, 2 0 6: flip-chip package structure 2 1 0: wafer 212: active surface 212a: bonding area 212b: non-bonding area 220: carrier board 2 2 2: carrying surface 222a: bonding area 222b : Non-joint area «230: Bump 240: Spoiler rib 250: Primer material 11181twf.ptd Page 14