CN106298711A - 电子组件与制造方法 - Google Patents

电子组件与制造方法 Download PDF

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CN106298711A
CN106298711A CN201510744847.5A CN201510744847A CN106298711A CN 106298711 A CN106298711 A CN 106298711A CN 201510744847 A CN201510744847 A CN 201510744847A CN 106298711 A CN106298711 A CN 106298711A
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projection
metal layer
bottom metal
described projection
substrate
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曾国玮
陈柏琦
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Sitronix Technology Corp
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Sitronix Technology Corp
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    • H—ELECTRICITY
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

本发明公开了一种电子组件与制造方法。电子组件用于一电子产品，所述电子组件包含有一衬底；一凸块，设置在所述衬底上，用以电性连接所述电子产品；以及至少一凸块底层金属层，设置在所述凸块与所述衬底间来让所述凸块贴合在所述衬底；其中，所述凸块底层金属层形成一缺口结构，用来提高所述凸块与所述衬底间的抗剪应力能力，以稳固所述凸块与所述衬底的耦接关系。

Description

电子组件与制造方法
技术领域
本发明涉及一种电子组件与制造方法，尤其涉及一种提高抗剪应力的电子组件与制造方法。
背景技术
常见的各类型电子装置，其内部是通过多种电子组件的适性组装与连接设置，来实现不同电子装置的工作。其中，现有技术常通过至少一凸块(Bump)，来做为电子组件中一驱动芯片与其周边多个组成组件间的信号传导材料。
然而，受限于驱动芯片追求小尺寸的设计规格，此种设计规格将导致驱动芯片所用凸块的相关尺寸也需对应减少，据此，凸块减少后的尺寸将造成凸块设置在驱动芯片的接触面积与其对应的贴合强度下降，一旦出现外力作用在凸块上，其将造成部分或全部的凸块容易剥离驱动芯片的接触面积，而产生电子组件的损坏与相关修补成本的增加。
因此，在现有电子产品与电子组件追求小尺寸设计的概念下，提供另一种具备改良结构设计的电子组件与制造方法，以对应提高电子组件的抗剪应力能力，已成为本领域的重要课题。
发明内容
因此，本发明的主要目的即在于提供一种改良结构设计的电子组件与制造方法，以对应提高电子组件的抗剪应力能力。
本发明公开一种电子组件，用于一电子产品，所述电子组件包含有一衬底；一凸块，设置在所述衬底上，用以电性连接所述电子产品；以及至少一凸块底层金属层，设置在所述凸块与所述衬底间来让所述凸块贴合在所述衬底；其中，所述凸块底层金属层形成一缺口结构，用来提高所述凸块与所述衬底间的抗剪应力能力，以稳固所述凸块与所述衬底的耦接关系。
本发明另外公开一种制造方法，用于一电子产品的一电子组件，其中所述电子组件包含有一衬底、一凸块以及至少一凸块底层金属层，所述制造方法包含有依序在所述衬底上设置所述凸块底层金属层与所述凸块；以及在所述凸块底层金属层进行一蚀刻工作来形成一缺口结构；其中，所述缺口结构用来提高所述凸块与所述衬底间的抗剪应力能力，以稳固所述凸块与所述衬底的耦接关系。
附图说明
图1A为本发明实施例一电子组件的局部示意图。
图1B为本发明实施例另一电子组件的局部示意图。
图2为图1A中一电子组件的俯视截面示意图。
图3为图1A中一电子组件产生缺口结构的流程图。
图4为本发明实施例中一电子组件产生缺口结构前或后所进行一剪应力试验的比较图。
图5为本发明实施例一的制造流程的流程图。
其中，附图标记说明如下：
10、12 电子组件
100、120 衬底
102、122 凸块
104、124、126 凸块底层金属层
300、302、304、306、308、310、500、步骤
502、504、506
31 光阻层
32 钝化层
50 制造流程
BB 凸块连接底部
具体实施方式
在说明书及权利要求书中使用了某些词汇来指称特定的组件。所属领域中具有通常知识者应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区别组件的方式，而是以组件在功能上的差异来作为区别的基准。在通篇说明书及权利要求当中所提及的「包含」为一开放式的用语，故应解释成「包含但不限定于」。此外，「耦接」一词在此包含任何直接及间接的电气连接手段。因此，若文中描述一第一装置耦接于一第二装置，则代表所述第一装置可直接连接于所述第二装置，或通过其他装置或连接手段间接地连接至所述第二装置。
针对已知技术中遭遇外力时，凸块恐无法有效贴合在驱动芯片上或产生容易剥离的情形，本发明实施例是在凸块与驱动芯片间的单一或多个凸块底层金属层的结构进行进行改良，且为了方便说明，以下实施例仅适性绘出部分的凸块与凸块底层金属层的结构特征。
请参考图1A，图1A为本发明实施例一电子组件12的局部示意图。如图1A所示，本实施例中的电子组件12设置在一电子产品中，而本实施例中电子产品例如可为一手机、一平板装置、一穿戴式电子产品或一笔记型计算器等，而电子组件12可为电子产品中的一驱动芯片等，但不限于此。电子组件12包含有一衬底120、一凸块122以及凸块底层金属(Under bump metal，UBM)层124、126，其中，衬底120可为驱动芯片的一电路板，凸块122设置在衬底120上来电性连接电子产品的相关传输线或工作组件/模块，而凸块底层金属层124、126依序设置在凸块122与衬底120间，以让凸块122可适性地贴合在衬底120上。当然，在其他实施例中，凸块与衬底间也可设置两个以上的凸块底层金属层，而非用以限制本发明的范围。
进一步，本实施例并未限制凸块与凸块底层金属层的材质为何，即考虑不同电子产品或电子组件的生产成本与信号传输的导通效率，本实施例可适性挑选各类型金属或半导体来做为凸块与凸块底层金属层的材质。举例来说，在一实施例中，凸块可以选择一第一材质(例如为金)，而多个凸块底层金属层可间隔选择相异于第一材质的一第二材质(例如为铜)与一第三材质(例如为银)，即类似于图1A所绘的实施例的结构特征，其中凸块与凸块底层金属层124、126将形成依序堆栈设置的一金属键结合体，且金属键结合体还耦接至衬底，以提供更强的贴合效果来让凸块可稳固在衬底上。当然，在另一实施例中，若凸块已选择为一第一材质，紧邻的凸块底层金属层选择相异的第二材质，而另一凸块底层金属层也选择相同的第一材质，则此实施例也将形成类似于图1A中的结构特征，即凸块与凸块底层金属层形成堆栈设置的金属键结合体，并让凸块稳固在衬底上。
进一步，在另一实施例中，假定凸块的材质已选择第一材质，紧邻凸块的凸块底层金属层的材质选择相同的第一材质，而另一凸块底层金属层的材质选择相异的第二材质。据此，由于凸块与紧邻的凸块底层金属层都为第一材质，将不易区别凸块与其相紧邻的凸块底层金属层间的差异，在此情况下，可将紧邻在凸块的凸块底层金属层视为凸块的一部分，即形成一凸块连接底部。请再参考图1B，图1B为本发明实施例另一电子组件10的局部示意图。类似于图1A电子组件12的结构特征，图1B中的电子组件10也包含有一衬底100、一凸块102、一凸块底层金属层104，且凸块102与凸块底层金属层104之间还连接一凸块连接底部BB(即箭头所指处)，据此，本实施例也可仅包含单一的凸块底层金属层，而非用以限制本发明的范围。
据此，针对不同电子产品或电子组件的实际需要，本实施例可适性选择凸块与至少一凸块底层金属层的材质，且设置在凸块与衬底间的凸块底层金属层的数量也可对应调整，以利后续的产品制造。
请继续参考图1A与图1B，不论凸块底层金属层的数量多寡，本发明实施例在紧邻凸块的凸块底层金属层(或凸块连接底部)形成一缺口结构，如图1A与图1B实施例中所圈之处。较佳地，本发明的缺口结构可用来提高凸块与衬底间的抗剪应力能力，以稳固凸块与衬底的耦接关系。再者，形成缺口结构之处也可不限于紧邻凸块的凸块底层金属层，将缺口结构形成紧邻凸块的凸块底层金属层仅为较佳的实施例。相比较于已知技术凸块无法有效贴合或设置在驱动芯片上，本发明可改良凸块与驱动芯片间的紧邻凸块底层金属层(或凸块连接底部BB)的结构设计，对应形成缺口结构，以大幅提高凸块抵抗外来剪应力的抵抗能力。
请参考图2，图2为图1A中一电子组件12的俯视截面示意图。如图2所示，本实施例中的缺口结构位于凸块122贴合凸块底层金属层124的一平面上，即缺口结构位于与凸块122相互紧邻的凸块底层金属层124上。较佳地，凸块122的一第一截面积大于凸块底层金属层124的一第二截面积，同时，另一凸块底层金属层126的一第三截面积也大于凸块底层金属层124的第二截面积。据此，本实施例中的凸块底层金属层124所对应的截面积为最小，而凸块122的截面积或凸块底层金属层126的截面积都大于凸块底层金属层124的截面积，至于凸块122的截面积与凸块底层金属层126的截面积的大小关系，可根据不同实施例来对应调整，非用以限制本发明的范围。
再者，本实施例可通过一蚀刻工作来对应产生缺口结构，换言之，本实施例可对紧邻凸块的凸块底层金属层(或凸块连接底部)进行一结构破坏程序，以对应在凸块贴合凸块底层金属层的一平面上形成缺口结构。请参考图3，图3为图1A中电子组件12产生缺口结构的流程图。如图3所示，在步骤300到步骤308中，电子组件12的凸块122以及凸块底层金属层124、126通过一系列的制造程序，对应形成且设置在衬底120上，例如步骤300可设置一光阻层31与一钝化层32，以对应在衬底120上生成凸块底层金属层124、126；步骤302可进行一电镀工作，以产生凸块122；步骤304到步骤308可进行一连串之蚀刻/剥离工作，以让凸块122以及凸块底层金属层124、126对应成型，且符合一预定产品的设计规格。
除此之外，为了加强电子组件12的抗剪应力能力，步骤310的蚀刻工作在紧邻凸块122的凸块底层金属层124上进行结构破坏程序，并对应形成缺口结构。较佳地，本实施例可利用一湿蚀刻工作，以将电子组件12浸至一反应溶剂中来进行氧化还原反应，进而在紧邻凸块122的凸块底层金属层124上形成缺口结构。相比较于步骤308中凸块底层金属层124的外观结构，本实施例中完成步骤310湿蚀刻工作的凸块底层金属层124可对应在每一边上后退至少0.5微米到1微米的距离，使得凸块底层金属层124所对应的截面积小于凸块122与凸块底层金属层126的截面积，而形成所谓的缺口结构。当然，本领域技术人员也可替换本实施例中所举例的湿蚀刻工作为其他类型的蚀刻工作，以对应在紧邻凸块的凸块底层金属层形成缺口结构者，再者，缺口结构也不限于形成在图3的凸块底层金属层124处，技术人员也能理解，缺口结构也能够形成在图3中的凸块底层金属层126处(图中未示)，此都属于本发明的范围。
请参考图4，图4为本发明实施例中一电子组件产生缺口结构前或后所进行一剪应力试验的比较图。如图4所示，相比较于未形成缺口结构的电子组件所进行的剪应力试验，其所得到的剪应力大小为一第一剪应力，本实施例在紧邻凸块的凸块底层金属层形成缺口结构，且其进行剪应力试验后得到的剪应力大小为一第二剪应力，据此，由图4的比较图可知第一剪应力将普遍小于第二剪应力，即本实施例所提供已形成缺口结构的电子组件将可承受较大的外来剪应力，具备有较强的抗剪应力能力，而不致使凸块轻易剥离衬底。
进一步地，本实施例电子组件所适用的制造方法可归纳为一制造流程50，且被编译为程序代码而储存在一制造机台的一储存装置中，以在电子组件制造过程中对应形成缺口结构且提高其抗剪应力能力，如图5所示，制造流程50包含以下步骤。
步骤500：开始。
步骤502：依序在衬底上设置凸块底层金属层与凸块。
步骤504：在凸块底层金属层进行蚀刻工作来形成缺口结构。
步骤506：结束。
简言之，配合不同电子产品或电子组件的制造流程，本实施例中制造流程50所对应的程序代码可储存在各类型制造机台的储存装置内，进一步，在完成步骤502的工作后(或者根据不同电子产品或电子组件所对应的各种复杂工作完成后)，再额外进行步骤504的蚀刻工作，以在紧贴凸块的凸块底层金属层(或凸块连接底部)形成缺口结构，进而加强各类型电子组件的抗剪应力能力。据此，已具备有缺口结构的电子组件可在后续切割、研磨或封装压合工作中，提供较高的制造良率，且对应降低凸块剥离衬底(或驱动芯片)的可能。同时，对于驱动芯片缩小化的设计规格下，本实施例也能对应提供更弹性的布局设计，以在相同衬底面积上容纳/设置更多的布线。至于缺口结构所对应的尺寸大小，本实施例可再搭配一工作者接口，并在步骤504进行前让使用者进行一工作时间的设定，以对应调整蚀刻工作所对应的工作时间长短，也属于本发明的范围。
当然，根据不同电子产品/组件的实际需求，凸块底层金属层的材质选择与数量多寡可适性地进行调整，并让凸块与衬底间多个凸块底层金属层堆栈形成一阶梯状结构，且由紧邻凸块的至少一凸块底层金属层设置有缺口结构，即至少维持紧邻凸块的凸块底层金属层的截面积最小，至于其他凸块底层金属层或凸块的截面积大小可适性地根据电子产品或电子组件来进行调整与修饰，非用以限制本发明的范围。
综上所述，本发明实施例提供一种改良结构设计的电子组件与制造方法，在紧邻凸块的凸块底层金属层形成一缺口结构，以对应提高电子组件的抗剪应力能力，进而降低制造电子组件或相关切割、研磨或封装压合工作的成本，同时提高制造电子组件的生产良率。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

1.一种电子组件，用于一电子产品，其特征在于，所述电子组件包含有：
一衬底；
一凸块，设置在所述衬底上，用以电性连接所述电子产品；以及
至少一凸块底层金属层，设置在所述凸块与所述衬底间来让所述凸块贴合所述衬底；
其中，所述凸块底层金属层形成一缺口结构，用来提高所述凸块与所述衬底间的抗剪应力能力，以稳固所述凸块与所述衬底的耦接关系。
2.如权利要求1所述的电子组件，其特征在于，所述凸块的材质与所述凸块底层金属层的材质为相同时，所述凸块底层金属层形成所述凸块的一部分，以及所述凸块的材质与所述凸块底层金属层的材质为不相同时，所述凸块与所述凸块底层金属层为堆栈设置的一金属键结合体。
3.如权利要求1所述的电子组件，其特征在于，所述缺口结构位于所述凸块贴合所述凸块底层金属层的一平面上，且所述凸块的一第一截面积大于所述凸块底层金属层的一第二截面积。
4.如权利要求1所述的电子组件，其特征在于，在一蚀刻工作中，所述凸块底层金属层进行一结构破坏程序，以对应在所述凸块贴合所述凸块底层金属层的一平面上形成所述缺口结构。
5.如权利要求1所述的电子组件，其特征在于，包含另一凸块底层金属层，设置在所述凸块底层金属与所述衬底间，且所述另一凸块底层金属层的一第三截面积大于所述凸块底层金属层的所述第二截面积。
6.如权利要求5所述的电子组件，其特征在于，所述凸块底层金属层与所述另一凸块底层金属层堆栈形成一阶梯状结构。
7.一种制造方法，用于一电子产品的一电子组件，其中所述电子组件包含有一衬底、一凸块以及至少一凸块底层金属层，其特征在于，所述制造方法包含有：
依序在所述衬底上设置所述凸块底层金属层与所述凸块；以及
在所述凸块底层金属层进行一蚀刻工作来形成一缺口结构；
其中，所述缺口结构用来提高所述凸块与所述衬底间的抗剪应力能力，以稳固所述凸块与所述衬底的耦接关系。
8.如权利要求7所述的制造方法，其特征在于，所述凸块的材质与所述凸块底层金属层的材质为相同时，所述凸块底层金属层形成所述凸块的一部分，以及所述凸块的材质与所述凸块底层金属层的材质为不相同时，所述凸块与所述凸块底层金属层为堆栈设置的一金属键结合体。
9.如权利要求7所述的制造方法，其特征在于，所述缺口结构位于所述凸块贴合所述凸块底层金属层的一平面上，且所述凸块的一第一截面积大于所述凸块底层金属层的一第二截面积。
10.如权利要求7所述的制造方法，其特征在于，所述蚀刻工作对所述凸块底层金属层进行一结构破坏程序，以对应在所述凸块贴合所述凸块底层金属层的一平面上形成所述缺口结构。
11.如权利要求7所述的制造方法，其特征在于，还包含在所述凸块底层金属与所述衬底间形成另一凸块底层金属层，且所述另一凸块底层金属层的一第三截面积大于所述凸块底层金属层的所述第二截面积。
12.如权利要求11所述的制造方法，其特征在于，所述凸块底层金属层与所述另一凸块底层金属层堆栈形成一阶梯状结构。
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US9773746B2 (en) 2017-09-26
TWI599276B (zh) 2017-09-11
KR20170001541A (ko) 2017-01-04
US20170345784A1 (en) 2017-11-30
CN114373730A (zh) 2022-04-19
JP6324361B2 (ja) 2018-05-16
KR101702975B1 (ko) 2017-02-06
US10163769B2 (en) 2018-12-25
JP2017017302A (ja) 2017-01-19

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