TW417262B - Semiconductor device of molding in ball grid array - Google Patents

Semiconductor device of molding in ball grid array Download PDF

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Publication number
TW417262B
TW417262B TW87117807A TW87117807A TW417262B TW 417262 B TW417262 B TW 417262B TW 87117807 A TW87117807 A TW 87117807A TW 87117807 A TW87117807 A TW 87117807A TW 417262 B TW417262 B TW 417262B
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Taiwan
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conductive layer
semiconductor device
grid array
ball grid
wire
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TW87117807A
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English (en)
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Naoto Kimura
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Nippon Electric Co
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/4805—Shape
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    • H01L2224/48091—Arched
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

417262 五、發明說明（1) 本發明是有關 array ; 3BGA)式半 式半導體裝置之方 的連接排列方式。 習知一種模具 1 B圖所示，其結構 料1 0，然後，再黏 壓縮鍵結法焊在晶 封。第1A圖顯示的 而第1B圖顯示的則 此外，曰本專 8-204062(1996)說 體裝置，其中焊料 脂表面上。 於一種換具球柵陣列（ball grid 導體裝置、’及_種製造此模具球柵陣列 GA代表主要基底表面之球狀焊料 ，，陣列式半導體裝置，如第1A圖和第 是藉由沾黏一種稱為橡膠之緩衝彈性材 附於晶片1表面。銅導線1 2則是利用熱 片1之焊墊2上。最後，再以密封劑1 3密 是一種峰沈積於晶片1中心的狀態， 走矣•壤^'。 * 利申請公開號3-9 4438( 1 991 )和 明書中揭示了數種模具球栅陣列式半導 球是位在充填於半導體晶片前表面的樹 在另一例子中’日本專利申請公開號3_94438( 1 99 1 ) 揭示一種如第2A圖所示之半導體裝置。如第2A圖和第2B圖 所示之剖面圖’其顯示在形成焊料球前之半導體裝置，而 第2B圖所顯示的則是形成焊料球後的半導體裝置剖面圖。 如第2A圖所示’形成一與預備放置半導體晶片1於其 上的晶片墊14連接的虛擬的支撐物15，其次以導線5(金屬 細導線）連接半導體晶片焊墊2以及虛擬的支撐物1 5，然後 再以樹脂密封整個薄膜。如第2B圖所示，在以樹脂密封 後，第2A圖中的線段B-B’和C-C’之外側部份將必須切離， 留下部份半導體晶片1。然後，留下部份的表面和導線5必
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^jl7262^^ 87Π7807 及、發明說明（3) 焊料球，設置在該洞内、 導辦^發明之另一特徵是揭示一種製造模具球柵陣列弋皁 導體裝置之製造方法，其步驟包括： 哗歹】式. 形成一絕緣細膜於一半導體晶片表面除焊墊外之至，丨、 〜部份； 乂 利用導線將該焊墊、該導電層焊結合在一起，且該導 線〜鍵結是位在該導電層上； 利用樹脂密封該半導體晶片； 施一打孔步驟，以形成一個貫穿該密封樹脂且露出部 份導線鍵結於該導電層上之金屬細導線的孔；以及 在該孔内設置一焊料。 為使本發明之優點和特徵更清楚可見’茲將以根據本 發明之較佳實施例，配合相關圖式，詳細說明如下。 第1Α圖顯示的是一種習知中央焊墊結構的模具球栅陣 列式半導體裝置之剖面圖； 第1B圖顯示的是一種習知周邊焊墊結構的球柵陣列式 半導體裝置之剖面圖； 第2A圖和第2B圖顯示的是另一種習知的球柵陣列式半 導體裝置之剖面圖，及其製造流程； 第3A圖和第3B圖顯示的分別是根據本發明之一較佳實 施例的模具球栅陣列式半導體裝置之平面圖和剖面圖；以 及 4A〜4F圖顯示的是根據本發明之一較佳實施例的以 具球柵陣列式半導體裝置之剖面流程圖。
417262 案號871 Π; im- 卜?月7 _Β 曰 修正 五 '發明說明（4) 實施例： 首先’請參照第3 A圖7責顯示的是一種根據本發明之 模具球柵阵列式半導體裝置平面圖，而第3B圖顯示的則是 第3 A圖的剖面圖。 如第3A圖和第3B圖所示，利用氣相沈積一細片 狀金屬屠4 ’例如銘層’於晶片！表面之聚醯並藉由 導線5(金屬細導線）與焊墊2 此外，形成一反^狀的 導線於細板狀的金屬層4上。春脂7密封後，經由樹脂 7的打孔處理’使焊料球6與裸露的反u狀的導線5鍵結。 其次，關於上述模具球柵陣列式半導體裝置的製造方 法將於第4A〜4F圖詳細描述。 面， 首先，請參照第4A圖，形成 然後再利用氣相沉積法形成 一聚醯胺層3於晶片1表 預備負載焊料球6之銘層 其次，如第4B圖所示’以導線5進行拉線程序 J ’ 外狂吁，連接 焊墊2和鋁層4。其中，焊墊2之位置是決定於晶片丨之電 路。因此’可經由導線5連接焊料球6所在的位置 然後’請參照第4C圖，導線連結是導通在紹層 此外’如第4D圖所示’以樹脂7進行密封程 後，如第4E圖所示，以雷射光8進行打洞步驟二二价 出部份於第4C圖所形成的導線5之烊料玻Q I成一路 q J么札y , | i 4丨田愈 射進行打洞的過程中，並不會傷害到導線。最，丹才j 圖所示，將焊料球6置於焊料球孔9内。 後’如第 本發明之優點：
第7頁 五、發明說明（5) |的年々月7曰 如上所述，、在本
月 Θ
J^-iL 由於導電層是形成於 曲片表 因此 面之絕緣樹脂上，故可降低導線連接時 於曰1 可降低半導體元件之成本。此外’焊 =化費，因此 可被簡易地導通。 屬、，田導線也 雖然本發明已以較佳實施例揭露如上，然其並 限定本發明，任何熟習此技藝者，在不 欲 你个脱離本發明之精神 和範圍内，所作之各種更動與潤飾均落在本發明之範圍 内，因此本發明之專利保護範圍當視後附之申請專利範圍 所界定者為準。
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Claims (1)

  1. 417262 盡號 87117807 修正本 六、申請專利範圍 1. 一種模具球柵陣列式半導體裝置，豆 半導體晶片，其包括有形成於半導體晶片表面除一焊 墊外之至少一部份之絕緣樹脂細膜； ’、 導電層，形成於該絕緣樹脂細膜上的一個區域，該區 域包括至少部份對應於一焊料球所在的位置； 第一金屬細導線，線鍵結該燁墊和該導電層； 第二金屬細導線’被線鍵結在該導電層上； 樹脂，部份密封該導電晶片，且包括有一露出部分該 第二金屬細導線之洞；以及 焊料球，設置在該洞内。 2. 如申請專利範圍第1項所述之模具球柵陣列式半導 體裝置’其中該絕緣樹脂細膜是聚醯胺細膜。 3. 如申請專利範圍第3項所述之模具球柵陣列式半導 體裝置，其中該導電層為鋁層。 4-如申請專利範圍第2項所述之模具球柵陣列式半導 體裝置，其中該導電層為鋁層。 5.—種製造模具球栅陣列式半導體裝置之製造方法， 其步驟包括： 形成一絕緣細膜於一半導體晶片表面除焊墊外之至少 一部份； 利用導線將該焊墊、該導電層焊結合在一起，且該導 線-鍵結是位在該導電層上； 利用樹脂密封該半導體晶片； 施一打孔步驟，以形成一個貫穿該密封樹脂且露出部
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TW87117807A 1997-10-28 1998-10-27 Semiconductor device of molding in ball grid array TW417262B (en)

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JP29530597A JP2978861B2 (ja) 1997-10-28 1997-10-28 モールドｂｇａ型半導体装置及びその製造方法

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TW417262B true TW417262B (en) 2001-01-01

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JPH11135663A (ja) 1999-05-21
KR100304681B1 (ko) 2001-11-02
KR19990037421A (ko) 1999-05-25
CN1215921A (zh) 1999-05-05
JP2978861B2 (ja) 1999-11-15
US6218728B1 (en) 2001-04-17

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