JPH11135663A - モールドｂｇａ型半導体装置及びその製造方法 - Google Patents

モールドｂｇａ型半導体装置及びその製造方法

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Publication number
JPH11135663A
JPH11135663A JP29530597A JP29530597A JPH11135663A JP H11135663 A JPH11135663 A JP H11135663A JP 29530597 A JP29530597 A JP 29530597A JP 29530597 A JP29530597 A JP 29530597A JP H11135663 A JPH11135663 A JP H11135663A
Authority
JP
Japan
Prior art keywords
conductive layer
semiconductor device
wire
type semiconductor
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP29530597A
Other languages
English (en)
Other versions
JP2978861B2 (ja
Inventor
Naoto Kimura
直人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
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Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP29530597A priority Critical patent/JP2978861B2/ja
Priority to US09/179,154 priority patent/US6218728B1/en
Priority to KR1019980045068A priority patent/KR100304681B1/ko
Priority to TW87117807A priority patent/TW417262B/zh
Priority to CN98120497A priority patent/CN1215921A/zh
Publication of JPH11135663A publication Critical patent/JPH11135663A/ja
Application granted granted Critical
Publication of JP2978861B2 publication Critical patent/JP2978861B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】 材料コストの低減が困難。 【解決手段】 パッド２を除く表面の少なくとも一部に
絶縁性樹脂膜３を有する半導体チップ１と、絶縁性樹脂
膜３上の、少なくとも半田ボール搭載位置に対応する箇
所を含む領域に設けられた導電層４と、パッド２と導電
層４とをワイヤボンディングする第１の金属細線５と、
導電層上でワイヤボンディングする第２の金属細線５
と、第２の金属細線５の一部が露出するように穴が設け
られた、半導体チップを封止する樹脂部７と、穴に搭載
された半田ボール６と、を有する。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明はモールドＢＧＡ（Ba
ll Grid Arry）型半導体装置及びその製造方法に関す
る。なお、ＢＧＡとは基板の主面に球状のハンダをアレ
イ状に並べて接続を行うことをいう。
【０００２】
【従来の技術】従来のモールドＢＧＡ型半導体装置は、
図３（ａ），（ｂ）に示すようにエラストマ１０といわ
れる緩衝用の弾性材をチップ１表面に貼り付けて、かつ
銅配線１２を接合したポリイミドテープ１１を貼り付
け、銅配線１２をチップ１のパッド２に熱圧着にて接合
し、封止材１３にて封止した構造になっている。図３
（ａ）はパッド２がチップ１の中央部分に設置されてい
る状態を示し、図３（ｂ）は周辺に設置されている状態
を示す。
【０００３】また、ハンダボールを半導体チップ表面側
の樹脂パッケージ表面に配設したモールドＢＧＡ型半導
体装置の例が特開平３−９４４３８号公報や特開平８−
２０４０６２号公報に記載されている。
【０００４】一例として、特開平３−９４４３８号公報
記載の半導体装置のハンダボール形成前の断面図を図４
（ａ）に、ハンダボール形成後の断面図を図４（ｂ）に
示す。
【０００５】図４（ａ）に示すように、半導体チップ１
を搭載するダイパッド１４と一体に形成されたダミーの
支持体１５を有し、半導体チップ１をダイパッド１４上
に接着した後、半導体チップ１のパッド２とダミーの支
持体１５とをワイヤ（金属細線）５でボンディング接続
し、これら部材全体を樹脂封止する。樹脂封止後、図４
（ｂ）に示すように、図４（ａ）の線Ｂ−Ｂ’および線
Ｃ−Ｃ’から外側を切断分離し、半導体チップ１を搭載
した部分を残す。この残った部分の表面およびワイヤ５
を研磨し、ワイヤ５の表面を所定の厚さまで露出させ
る。このワイヤ５の露出研磨された部分にハンダボール
６を形成する。
【０００６】
【発明が解決しようとする課題】しかしながら、上記図
３のモールドＢＧＡ型半導体装置では、パッド２から半
田ボール６への配線構造がポリイミドテープ１１を使用
したり、エラストマ１０を使用したりして材料コストが
高くなることと、接着構造のため製造方法が煩雑になる
等の課題があった。
【０００７】また、図４に示したモールドＢＧＡ型半導
体装置においても、ダミーの支持体１５を用いるため材
料コストが高くなる等の課題があった。
【０００８】本発明の目的は、より低コストで、ワイヤ
を介した半田ボールとの接続を行なうことができるモー
ルドＢＧＡ型半導体装置およびその製造方法を提供する
ことにある。
【０００９】
【課題を解決するための手段】本発明のモールドＢＧＡ
型半導体装置は、パッドを除く表面の少なくとも一部に
絶縁性樹脂膜を有する半導体チップと、該絶縁性樹脂膜
上の、少なくとも半田ボール搭載位置に対応する箇所を
含む領域に設けられた導電層と、該パッドと該導電層と
をワイヤボンディングする第１の金属細線と、前記導電
層上でワイヤボンディングする第２の金属細線と、該第
２の金属細線の一部が露出するように穴が設けられた、
前記半導体チップを封止する樹脂部と、該穴に搭載され
た半田ボールと、を有するものである。
【００１０】本発明のモールドＢＧＡ型半導体装置の製
造方法は、半導体チップのパッドを除く表面の少なくと
も一部に絶縁性樹脂膜を形成する工程と、前記絶縁性樹
脂膜上の、少なくとも半田ボール搭載位置に対応する箇
所を含む領域に導電層を形成する工程と、前記パッドと
前記導電層とをワイヤボンディングするとともに、前記
導電層上でワイヤボンディングする工程と、前記半導体
チップを樹脂封止する工程と、前記導電層上でワイヤボ
ンディングした金属細線の一部が露出するように、封止
した樹脂に穴を開ける工程と、前記穴に半田ボールを搭
載する工程と、を有するものである。
【００１１】
【発明の実施の形態】以下、本発明の実施形態について
図面を用いて説明する。
【００１２】図１（ａ）は本発明の一実施形態のモール
ドＢＧＡ型半導体装置の樹脂部の一部を切り欠いた平面
図、図１（ｂ）は図１（ａ）の断面図である。
【００１３】図１（ａ），（ｂ）に示すように、チップ
１上に形成されているポリイミド膜３上にアルミ等の積
層金属層４を蒸着等で形成し、パッド２からワイヤ（金
属細線）５にて配線し、さらにアルミ等積層金属４上で
ワイヤ５にて逆「Ｕ」字状の配線を行なう。樹脂７によ
る封止後に、樹脂７に穴をあけて露出した逆「Ｕ」字状
のワイヤ５を半田ボール６と接合する。
【００１４】次に、上記モールドＢＧＡ型半導体装置の
製造方法について図２（ａ）〜図２（ｆ）を用いて説明
する。
【００１５】まず、図２（ａ）に示すように、チップ１
表面にポリイミド３を施し、半田ボール６の設置個所に
対応する場所にアルミ４を蒸着する。
【００１６】図２（ｂ）に示すように、パッド２からア
ルミ層４へワイヤ５にてワイヤボンディングを行う。パ
ッド２はチップ１の回路により位置が不定であるために
ワイヤ５にて半田ボール６搭載箇所ヘワイヤリングする
ものである。次に、図２（ｃ）に示すようにアルミ４上
にてワイヤボンディングを行う。
【００１７】さらに図２（ｄ）に示すように、樹脂７に
て樹脂封止を行う。次に図２（ｅ）に示すように、レー
ザ光８にて半田ボール穴９を形成し図２（ｃ）で形成し
たワイヤ５の一部を露出させる。半田ボール穴９は研磨
により露出させることもできるが、レーザ光を用いると
ワイヤをきずつけることなく露出させることができる。
最後に図２（ｆ）にて半田ボール穴９に半田ボール６を
搭載する。
【００１８】
【発明の効果】以上説明したように、本発明によれば、
チップの絶縁性樹脂膜に導電層を設置するので、ワイヤ
ボンディングを行うために資材費用が少なく低コストで
製造できる。また、半田ボールとの金属細線による接合
が容易になる。
【図面の簡単な説明】
【図１】本発明の一実施形態のモールドＢＧＡ型半導体
装置の樹脂部の一部を切り欠いた平面図及び断面図であ
る。
【図２】上記モールドＢＧＡ型半導体装置の製造方法を
説明するための工程図である。
【図３】従来のセンタパッド構造ＢＧＡ型半導体装置の
断面図及び周辺パッド構造ＢＧＡ型半導体装置の断面図
である。
【図４】従来の他の構成のＢＧＡ型半導体装置の構成お
よび製造方法を示す断面図である。
【符号の説明】
１ チップ ２ パッド ３ ポリイミド ４ アルミ等金属積層 ５ ワイヤ ６ 半田ボール ７ 樹脂 ８ レーザ光 ９ 半田ボール穴 １０ エラストマ １１ ポリイミドテープ １２ 銅配線 １３ 封止材 １４ ダイパッド １５ ダミーの支持体

Claims (7)

    【特許請求の範囲】
  1. 【請求項１】 パッドを除く表面の少なくとも一部に絶
    縁性樹脂膜を有する半導体チップと、該絶縁性樹脂膜上
    の、少なくとも半田ボール搭載位置に対応する箇所を含
    む領域に設けられた導電層と、該パッドと該導電層とを
    ワイヤボンディングする第１の金属細線と、前記導電層
    上でワイヤボンディングする第２の金属細線と、該第２
    の金属細線の一部が露出するように穴が設けられた、前
    記半導体チップを封止する樹脂部と、該穴に搭載された
    半田ボールと、を有するモールドＢＧＡ型半導体装置。
  2. 【請求項２】 前記絶縁性樹脂膜は、ポリイミド膜であ
    ることを特徴とする請求項１に記載のモールドＢＧＡ型
    半導体装置。
  3. 【請求項３】 前記導電層はアルミ層であることを特徴
    とする請求項１または請求項２に記載のモールドＢＧＡ
    型半導体装置。
  4. 【請求項４】 半導体チップのパッドを除く表面の少な
    くとも一部に絶縁性樹脂膜を形成する工程と、 前記絶縁性樹脂膜上の、少なくとも半田ボール搭載位置
    に対応する箇所を含む領域に導電層を形成する工程と、 前記パッドと前記導電層とをワイヤボンディングすると
    ともに、前記導電層上でワイヤボンディングする工程
    と、 前記半導体チップを樹脂封止する工程と、 前記導電層上でワイヤボンディングした金属細線の一部
    が露出するように、封止した樹脂に穴を開ける工程と、 前記穴に半田ボールを搭載する工程と、を有するモール
    ドＢＧＡ型半導体装置の製造方法。
  5. 【請求項５】 封止した樹脂の穴はレーザー光を照射す
    ることで形成されることを特徴とする請求項４に記載の
    モールドＢＧＡ型半導体装置の製造方法。
  6. 【請求項６】 前記絶縁性樹脂膜は、ポリイミド膜であ
    ることを特徴とする請求項４または請求項５に記載のモ
    ールドＢＧＡ型半導体装置の製造方法。
  7. 【請求項７】 前記導電層はアルミ層であることを特徴
    とする請求項４〜６のいずれかの請求項に記載のモール
    ドＢＧＡ型半導体装置の製造方法。
JP29530597A 1997-10-28 1997-10-28 モールドｂｇａ型半導体装置及びその製造方法 Expired - Fee Related JP2978861B2 (ja)

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JP29530597A JP2978861B2 (ja) 1997-10-28 1997-10-28 モールドｂｇａ型半導体装置及びその製造方法
US09/179,154 US6218728B1 (en) 1997-10-28 1998-10-26 Mold-BGA-type semiconductor device and method for making the same
KR1019980045068A KR100304681B1 (ko) 1997-10-28 1998-10-27 몰드bga형반도체장치및그제조방법
TW87117807A TW417262B (en) 1997-10-28 1998-10-27 Semiconductor device of molding in ball grid array
CN98120497A CN1215921A (zh) 1997-10-28 1998-10-28 模压球栅阵列型半导体器件及其制造方法

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TW417262B (en) 2001-01-01
US6218728B1 (en) 2001-04-17
CN1215921A (zh) 1999-05-05
KR19990037421A (ko) 1999-05-25
KR100304681B1 (ko) 2001-11-02

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