TW412834B - A method of forming a void free trench isolation - Google Patents

A method of forming a void free trench isolation Download PDF

Info

Publication number
TW412834B
TW412834B TW088100962A TW88100962A TW412834B TW 412834 B TW412834 B TW 412834B TW 088100962 A TW088100962 A TW 088100962A TW 88100962 A TW88100962 A TW 88100962A TW 412834 B TW412834 B TW 412834B
Authority
TW
Taiwan
Prior art keywords
trench
substrate
layer
forming
oxide layer
Prior art date
Application number
TW088100962A
Other languages
English (en)
Chinese (zh)
Inventor
Chang-Ki Hong
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW412834B publication Critical patent/TW412834B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
TW088100962A 1998-01-26 1999-01-22 A method of forming a void free trench isolation TW412834B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980002390A KR19990066454A (ko) 1998-01-26 1998-01-26 반도체 장치의 트렌치 격리 형성 방법

Publications (1)

Publication Number Publication Date
TW412834B true TW412834B (en) 2000-11-21

Family

ID=19532169

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088100962A TW412834B (en) 1998-01-26 1999-01-22 A method of forming a void free trench isolation

Country Status (6)

Country Link
JP (1) JPH11260903A (fr)
KR (1) KR19990066454A (fr)
DE (1) DE19902999A1 (fr)
FR (1) FR2776126A1 (fr)
GB (1) GB2333644A (fr)
TW (1) TW412834B (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3540633B2 (ja) * 1998-11-11 2004-07-07 株式会社東芝 半導体装置の製造方法
JP2001118920A (ja) * 1999-10-15 2001-04-27 Seiko Epson Corp 半導体装置およびその製造方法
JP2001332613A (ja) * 2000-05-24 2001-11-30 Nec Corp 半導体装置の製造方法
US6518148B1 (en) * 2001-09-06 2003-02-11 Taiwan Semiconductor Manufacturing Company, Ltd Method for protecting STI structures with low etching rate liners
KR100485518B1 (ko) * 2002-09-18 2005-04-27 동부아남반도체 주식회사 셀로우 트렌치 소자분리막의 제조 방법
KR100476934B1 (ko) * 2002-10-10 2005-03-16 삼성전자주식회사 트렌치 소자분리막을 갖는 반도체소자 형성방법
CN111863706A (zh) * 2020-08-28 2020-10-30 上海华力微电子有限公司 闪存存储器及其制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW291580B (en) * 1996-04-22 1996-11-21 United Microelectronics Corp Manufacturing process of shallow isolation trench
US5712185A (en) * 1996-04-23 1998-01-27 United Microelectronics Method for forming shallow trench isolation

Also Published As

Publication number Publication date
FR2776126A1 (fr) 1999-09-17
DE19902999A1 (de) 1999-07-29
JPH11260903A (ja) 1999-09-24
GB9901480D0 (en) 1999-03-17
KR19990066454A (ko) 1999-08-16
GB2333644A (en) 1999-07-28

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