經濟部智慧財產局員工消費合作社印製 412841 A7 ____B7____ 五、發明說明（/ ) 發明背景： 發明領域： 丨 本發明係有關一種半導體元件中隔離區的製造方法’尤 指一種在半導體元件中形成淺溝槽以作爲元件間的相互隔離 之淺溝槽隔離區的製造方法。 先前技藝战述： 當半導體積體電路朝向更細微的尺寸發展時，元件間的 距離隨之縮短，而元件與元件間的電性隔離也因而成爲非常 重要的關鍵。填滿絕緣材質的淺溝槽已經被證實爲隔離元件 的理想結構；然而，溝槽隔離的製程仍然遭受到一些問題’ 例如，在電流電壓的特性中，次臨界區観察到“雙峰狀曲線” 的現象，此乃由於隔離溝槽之頂端周圍的棱角所造成;此外， 在經過傳統的淺溝槽隔離製程步驟後，溝槽邊緣的絕緣材質 也會遭受侵蝕，此侵蝕現象使得溝槽邊緣產生更大的凹陷， 惡化了原本就不正常的元件特性一雙峰狀的電流電壓特性； 而後續的閘極餓刻也因而更加困難。因此，工業上的挑戰莫 過於提供一種平坦化隔離溝槽的製造方法，使溝槽的頂端周 圍平滑而無稜角，溝槽邊緣則不會有凹陷的現象發生。 有許多改善平坦化隔離溝槽的製造方法已經陸續被揭 露，例如，美國專利第5, 578, 518號，於1996年11月26 曰通過，由Hidetoshi Koike等人申請的“平滑溝槽隔離之 製造方法”中，即揭露了如何製造平滑淺溝槽隔離的方法。 此外，美國專利第5,258, 332號，於1993年11月2日 2 ----L---------- I--------訂 iit---線’ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4X2841 A7 _B7_ 五、發明說明（X) 通過，由Mr. Keiji Horioka等人申請的“以蝕刻形成平滑 結構之半導體元件製造方法”中，即揭露在氟和氧混和的氣 體中，如何使用電漿蝕刻的方法來實現平滑結構的淺隔離溝 槽，另有美國專利第5, 674, 775號，於1997年10月7曰通 過，由Mr. Chin-Hsiung Ho等人申請的“利用蝕刻緩衝層 形成平滑隔離溝槽的製造方法”中，即揭露在進行溝槽的蝕 刻過程中，如何使用緩衝層的方法來製造平滑的淺隔離溝 槽，美國專利第5, 433, 794號，於1995年7月18日通過， 由Mr. Pierre C. Fazan等人申請的“利用邊牆來改善溝槽 隔離”中，即揭露了如何使溝槽隔離的絕緣材質伸展至溝槽 周圍邊緣上方，以在溝槽上方形成一個小圓蓋，美國專利第 4, 876,217 號，於 1989 年 10 月 24 日通過，由 Mr. Peter J. Zdebel申請的‘‘半導體中隔離區之製造方法”中，即揭露 在半導體基座上形成介質隔離區的方法，也就是在半導體基 座上蝕刻溝槽，然後填入第一層介質層作爲襯墊，接著再以 第二層介質填滿溝槽，最後以光罩定義出隔離區，將隔離區 外的第二層介質移除即可，美國專利第5,190, 889號，於1993 年3月2曰通過，由Mr. Stephen S. Poon等人申請的“填 充矽酸鍺之溝槽隔離製造方法”中，即揭露平滑溝槽的製造 方法，該方法利用了阻障層作爲襯墊，並且用矽酸鍺作爲填 充材料，美國專利第4, 994, 406號，於1991年2月19日通 過，由Mr. Barbara Vasquez所申請的“深與淺隔離結構之 半導體元件製造方法”中，即揭露半導體基座中隔離結構的 製造方法，不同寬度的深溝槽隔離和淺介質隔離的結構都可 ---^----------- --------訂·--------1 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 412S41 A7 _____B7_ 五、發明說明（j ) 以形成。 發明簡要說明： 本發明主要目的爲提供一種半導體積體電路中製造平坦 化隔離溝槽的改善方法；進一步來說，也就是去除溝槽頂端 周圍的稜角；另一方面，則是爲了抑制隔離溝槽邊緣之絕緣 材質的侵触現象。 根據本發明，爲了將元件隔離，上述及其他的目的將可 藉由在半導體基座表面形成溝槽隔離結構來加以實現，此方 法包含下列步驟：在一個具有元件的半導體基座表面上形成 第一層氧化層，接著在第一層氧化層上沉積氮化矽層，然後 進行微影曝光，將部分的氣化矽層去除，於是部分的第一層 氧化層裸露，也就是部分的氧化層未被氮化矽覆蓋。繼續進 行氧化層的蝕刻，未被氮化矽覆蓋的氧化層被蝕刻去除，使 半導體基座的表面暴露出來。然後再進行半導體基座的蝕 刻，於是未被覆蓋的部分則形成溝槽，之後進行非等向性氧 化層蝕刻，此時由於開口邊緣的第一層氧化層也會被蝕刻 到，因此使半導體基座與溝槽的邊界便形成了一個暴露出來 的棱角。接著將第二層氧化層覆蓋於整個表面，包括溝槽內 部以及半導體基座與溝槽邊界所暴露出來的邊緣處都形成一 層氧化層。繼續進行氮化矽層的等向性蝕刻，此蝕刻使得氮 化砍層的厚度變薄，並且將開口邊緣的氮化矽蝕刻掉，第二 層氧化層裸露的部分於是增加。接下來覆蓋第三層氧化層於 整個表面，並且將半導體基座上的溝槽填滿’然後再進行化 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---；----------t--------訂---------線' <請先閱讀背面之注意事項再填寫本I> 412841 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（if ) 學機械研磨，將第三層氧化層磨除，一直磨到氣化矽層爲止， 此時只有溝槽上方的部分仍保有第三層氧化層’使得氮化矽 層與氧化層呈現平坦的表面。接著除去氮化矽層，再移去半 導體表面的第一層氧化層，於是就形成了填滿二氧化矽的平 坦溝槽。 圖示的簡要說明： 圖1Α到圚1Η以概略的剖面圖來說明本發明實施的方法。 圓號的簡要說明： 10半導體基座 12氮化矽層 14溝槽 17第二層氧化層 發明之詳細說明： 參考圖1Α到圖1Η，即爲包含元件（並未表示）的半導 體基^ 10 ’半導體基座1〇以單晶矽爲佳，但也可以是任何 的半導體材料’例如：在積體電路製造中所使用的矽或鍺， 或者砂或砷化鎵。二氧化矽層li的厚度大約在5〇埃到500 埃之間’氮化矽層12的厚度大約在ioog埃到3000埃之間， 二氧化砂層11與氮化矽層12經過光罩曝光後定義出一個開 口區域13，這開口區域即定義爲隔離溝槽形成的位置。 圖1A顯示半導體基座10被蝕刻出—溝槽14，接著， 如圖1B所顯示，二氧化矽層u經由曝光的開口區域進行氧 _ 5 11二氧化矽層 13開口區域 16凹洞 18第三層氧化層 (請先閲讀背面之注意事項再填寫本頁> 裝 訂---------線 本紙张尺度通用干國國豕標準（CNS)A4規格（21〇 X 297公爱） A7 412841 __B7__ 五、發明說明（> ) 化層餓刻後，會造成二氧化矽層11的側向蝕刻。在此’等 向性的蝕刻溶液被使用來進行二氧化矽的蝕刻’例如：稀釋 的氫氟酸，此触刻方法對二氧化矽的触刻比氮化矽的蝕刻具 有較高的選擇性，一般而言，二氧化矽蝕刻率與氮化矽蝕刻 率的比值介於20到500之間；此外，這個蝕刻方法對二氧 化矽的選擇性也較矽來的高，一般而言，二氧化矽蝕刻率與 矽触刻率的比值介於20到1G00之間。因此，側向蝕刻將氮 化砂層12下的二氧化砂層11形成一個凹洞16，此凹洞16 延伸過溝槽的邊緣一段距離，這個距離大約在30埃到300 埃之間，就在二氧化矽層11發生側向蝕刻的同時，砍基座 中溝槽頂端的棱角也就形成了。 參考圖1C ,第二層氧化層17覆蓋在整個砂表面，同時 也覆蓋了溝槽的內部以及溝槽邊緣所暴露出來的半導體基座 區域，第二層氧化層17的形成使得溝槽的內部形成一層襯 墊，並且跨過溝槽頂端的稜角，圖1C中顯示第二層氧化層 17緊接著二氧化矽層11 ’這第二層氧化層是在水蒸氣中或 是氧氣中氧化而成，溫度在8Q0度至1〇〇〇度之間，於是形 成厚度50埃到500埃的二氧化矽。在第二層氧化層的形成 過程中，由於角落的氧化速率較快一又稱爲平面效應，使得 凹洞16與溝槽14在進行氧化時’溝槽的稜角會變的平滑些。 參考圖1D ’用氮化矽蝕刻率高於二氧化矽蝕刻率的等 向性蝕刻溶液來進行氮化矽層12的蝕刻，例如熱磷酸；— 般而言’熱磷酸對氮化矽的蝕刻率大約是二氧化矽触刻率的 _6 本紙張尺度適用中國國家標畢（CNS)A4規格（210 X 297公楚^ " --- Ίι I -------^i---- - 訂--------- 線 (請先間讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 412841 A7 __ B7 五、發明說明（b) 20到100倍之間’此溶液正好使氮化砂層12的開口邊緣部 分被蝕刻掉，大約20G埃到600埃，同時，如圖id所示， 氮化矽層的厚度也減少爲2GG埃到6GG埃之間。 接著參考圖1E，第三層氧化層18覆蓋住整個表面，並 且將半導體基座上的溝槽填滿。第三層氧化層可以是以低壓 化學氣相沉積或電漿增強化學氣相沉積的製程方法來均勻地 形成，此氧化層的厚度大約在2G0G埃到1QG00埃之間。下 一步就利用化學機械研磨的製程方法來使第三層氧化層平坦 化，磨去氧化層直到氮化矽爲止。最後只有溝槽上方才保留 一部份的第三層氧化層，因此如圖1F所示，形成氮化矽與 第三層氧化層的平坦表面。在研磨填滿溝槽的第三層氧化層 以後，第三層氧化層延伸過溝槽邊緣一段距離，見圖1F， 此距離大約是200埃到600埃之間，這段延伸出來的氧化層 可以在後續的蝕刻步驟中保護溝槽的邊緣。 參考圖1G和1H，剛才剩餘的氮化矽層用熱隣酸溶液加 以去除，接著再用稀釋的氫氟酸溶液將二氧化砍層11蝕刻 掉，再進行氧化層的移除時，溝槽的邊緣被溝槽內部及延伸 出來大約200埃到600埃的第三層氧化層18所保護著。 (請先閲讚背面之注意事項再填寫本頁) 裝-------訂------線 經濟部智慧財產局員工消費合作社印製 7 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 412841 A7 ____B7____ V. Description of the Invention (/) Background of the Invention: Field of the Invention: 丨 The present invention relates to a method for manufacturing an isolation region in a semiconductor element, especially a method for forming a shallow region in a semiconductor element. The trench is a method for manufacturing a shallow trench isolation region that is isolated from each other. The previous art warfare description: When the semiconductor integrated circuit develops toward a finer size, the distance between the components is shortened, and the electrical isolation between the components becomes a very important key. Shallow trenches filled with insulating material have proven to be ideal structures for isolating components; however, the process of trench isolation still suffers from some problems. 'For example, in the characteristics of current and voltage, a "double-peak curve" was observed in the subcritical region. "This is caused by the edges and corners around the top of the isolation trench. In addition, after the traditional shallow trench isolation process, the insulating material at the edge of the trench will also be eroded. This erosion phenomenon makes the edge of the trench Larger pits are generated, which deteriorates the already abnormal component characteristics, such as a double-peak current-voltage characteristic, and the subsequent gate engraving is more difficult. Therefore, the industrial challenge is to provide a method for manufacturing a planarized isolation trench, so that the top periphery of the trench is smooth without edges and corners, and there is no depression at the edge of the trench. Many manufacturing methods for improving the planarization isolation trenches have been successively disclosed. For example, U.S. Patent No. 5,578,518 was adopted on November 26, 1996. The "Smooth Trench Isolation Method" applied by Hidetoshi Koike et al. The "manufacturing method" disclosed how to make a smooth shallow trench isolation. In addition, U.S. Patent No. 5,258,332, on November 2, 1993 2 ---- L ---------- I -------- Order iit --- line '( Please read the notes on the back before filling this page.) This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm). 4X2841 A7 _B7_ printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. ) Through, "Semiconductor element manufacturing method for forming a smooth structure by etching" applied by Mr. Keiji Horioka et al., That is, exposing how to use plasma etching in a gas mixed with fluorine and oxygen to achieve a shallow structure with a smooth structure. Isolation trenches, also US Pat. No. 5,674,775, adopted on October 7, 1997, and a method for manufacturing a smooth isolation trench using an etching buffer layer, applied by Mr. Chin-Hsiung Ho et al. In the process of etching trenches, it is disclosed how to use a buffer layer method to make smooth shallow isolation trenches. US Patent No. 5,433,794, adopted on July 18, 1995, by Mr. Pierre C. Fazan et al.'S application "Using side walls to improve trench isolation" How to make the trench isolation insulation material stretch over the edge around the trench to form a small round cover above the trench, US Patent No. 4,876,217, approved on October 24, 1989, by Mr. Peter J. In the "Manufacturing Method of Isolation Area in Semiconductor" applied by Zdebel, the method of forming a dielectric isolation area on a semiconductor substrate is disclosed, that is, etching a trench on the semiconductor substrate, and then filling the first dielectric layer as a liner Pad, then fill the trench with a second layer of dielectric, and finally define the isolation zone with a photomask, and remove the second layer of dielectric outside the isolation zone. US Patent No. 5,190,889, March 1993 Passed on the 2nd, "German Silicate Filled Trench Isolation Manufacturing Method", applied by Mr. Stephen S. Poon et al., Discloses a method for manufacturing smooth trenches, which uses a barrier layer as a liner, and Using germanium silicate as a filling material, U.S. Patent No. 4,994,406, adopted on February 19, 1991, in "Method for Manufacturing Semiconductor Components with Deep and Shallow Isolation Structure", applied by Mr. Barbara Vasquez, that is, Expose semiconductor The manufacturing method of the isolation structure in the seat, the structures of deep trench isolation and shallow dielectric isolation of different widths are all available. ------------------------ Order ---- ----- 1 (Please read the precautions on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 412S41 A7 _____B7_ 5. Description of the invention (j) to form. Brief description of the invention: The main purpose of the present invention is to provide an improved method for manufacturing a planarized isolation trench in a semiconductor integrated circuit; further, that is, to remove edges and corners around the top of the trench; on the other hand, to suppress the isolation trench The interference of the insulating material on the edge of the groove. According to the present invention, in order to isolate components, the above and other objects can be achieved by forming a trench isolation structure on the surface of a semiconductor base. The method includes the following steps: forming a first semiconductor base surface with a component; An oxide layer, then a silicon nitride layer is deposited on the first oxide layer, and then a lithographic exposure is performed to remove part of the vaporized silicon layer, so that part of the first oxide layer is exposed, that is, part of the oxide layer Not covered by silicon nitride. The etching of the oxide layer is continued, and the oxide layer not covered by the silicon nitride is etched and removed, so that the surface of the semiconductor base is exposed. Then the semiconductor base is etched, so the uncovered part is formed with a trench, and then anisotropic oxide layer etching is performed. At this time, because the first oxide layer on the edge of the opening is also etched, the semiconductor The boundary between the base and the groove forms an exposed corner. Next, a second oxide layer is formed on the entire surface, including the inside of the trench and the exposed edge of the semiconductor substrate and the trench boundary to form an oxide layer. The isotropic etching of the silicon nitride layer is continued. This etching makes the thickness of the nitrided layer thinner, and the silicon nitride at the edge of the opening is etched away, so the exposed portion of the second oxide layer is increased. Next, cover the third layer of oxide on the entire surface, and fill the grooves on the semiconductor substrate. Then, the paper size will be adapted to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --- ; -------- t -------- Order --------- line '< Please read the notes on the back before filling in this I > 412841 A7 B7 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau. 5. Description of the invention (if) The mechanical grinding is performed, and the third oxide layer is removed until the siliconized gas layer is removed. At this time, only the part above the trench still retains the third. An oxide layer 'makes the silicon nitride layer and the oxide layer present a flat surface. Then the silicon nitride layer is removed, and the first oxide layer on the surface of the semiconductor is removed, so that a flat trench filled with silicon dioxide is formed. Brief description of the figures: FIGS. 1A to 1A illustrate the method of the present invention in a schematic sectional view. Brief description of French horn: 10 semiconductor base 12 silicon nitride layer 14 trench 17 second oxide layer invention detailed description: Refer to FIG. 1A to FIG. 1Η, which is a semiconductor base including components (not shown) ^ 10 ' The semiconductor pedestal 10 is preferably monocrystalline silicon, but it can also be any semiconductor material such as silicon or germanium, or sand or gallium arsenide used in the fabrication of integrated circuits. The thickness of the silicon dioxide layer li is between 50 angstroms and 500 angstroms. The thickness of the silicon nitride layer 12 is between ioog angstroms and 3000 angstroms. After the sand dioxide layer 11 and the silicon nitride layer 12 are exposed through a photomask, An open area 13 is defined, and this open area is defined as the position where the isolation trench is formed. FIG. 1A shows that the semiconductor pedestal 10 is etched out—trenches 14, and then, as shown in FIG. 1B, the silicon dioxide layer u is exposed to oxygen through the exposed opening area. Three-layer oxide layer (Please read the precautions on the back before filling in this page> Binding --------- Threaded Paper Standard Common Dry Country Standard (CNS) A4 Specification (21〇X 297 Public Love ) A7 412841 __B7__ 5. Description of the invention (&); After the formation layer is etched, the silicon dioxide layer 11 will be etched sideways. Here, an isotropic etching solution is used to etch silicon dioxide. For example : Diluted hydrofluoric acid. This etching method is more selective for silicon dioxide etching than silicon nitride etching. Generally speaking, the ratio of silicon dioxide etching rate to silicon nitride etching rate is between In addition, the selectivity of this etching method to silicon dioxide is higher than that of silicon. Generally speaking, the ratio of silicon dioxide etching rate to silicon contact rate is between 20 and 1G00. Therefore The lateral etching will form a hollow 16 in the sand dioxide layer 11 under the nitrided sand layer 12, and this concave The hole 16 extends a distance from the edge of the trench. This distance is about 30 angstroms to 300 angstroms. At the same time that the silicon dioxide layer 11 is etched laterally, the corners of the trench apex in the base are formed. Referring to FIG. 1C, the second oxide layer 17 covers the entire sand surface, and also covers the inside of the trench and the semiconductor base region exposed by the edge of the trench. The formation of the second oxide layer 17 makes the interior of the trench Form a layer of pads and cross the edges and corners of the trench. Figure 1C shows that the second oxide layer 17 is next to the silicon dioxide layer 11 'This second oxide layer is oxidized in water vapor or oxygen , The temperature is between 8Q0 degrees and 1000 degrees, so silicon dioxide is formed with a thickness of 50 angstroms to 500 angstroms. During the formation of the second oxide layer, the corners are oxidized at a faster rate. Effect, when the recesses 16 and the trenches 14 are oxidized, the edges of the trenches become smoother. Referring to FIG. 1D, the isotropic etching solution with a silicon nitride etching rate higher than the silicon dioxide etching rate is used. Etching of silicon nitride layer 12, for example Thermal phosphoric acid; — Generally speaking, the etching rate of silicon nitride by thermal phosphoric acid is about _6 of silicon dioxide. This paper size is applicable to China National Standard Complete (CNS) A4 specification (210 X 297 cm) " --- Ίι I ------- ^ i -----Order --------- Line (please read the precautions on the back before filling out this page) Staff of the Intellectual Property Bureau of the Ministry of Economic Affairs Consumption Cooperation Du printed 412841 A7 __ B7 V. Description of the invention (b) 20 to 100 times' This solution just etched away the opening edge portion of the nitrided sand layer 12, about 20G to 600 Angstroms. At the same time, as shown in the figure As indicated by id, the thickness of the silicon nitride layer is also reduced to between 2GG and 6GG. Referring next to FIG. 1E, a third oxide layer 18 covers the entire surface and fills the trench on the semiconductor substrate. The third oxide layer may be uniformly formed by a low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition process. The thickness of this oxide layer is approximately 2G0G to 1QG00. The next step is to use a chemical mechanical polishing process to flatten the third oxide layer and remove the oxide layer until the silicon nitride. Finally, only a portion of the third oxide layer remains above the trench, so as shown in FIG. 1F, a flat surface of the silicon nitride and the third oxide layer is formed. After grinding the third oxide layer that fills the trench, the third oxide layer extends a distance over the edge of the trench, as shown in Figure 1F. This distance is approximately 200 angstroms to 600 angstroms. This extended oxide layer The edges of the trenches can be protected in subsequent etching steps. Referring to FIGS. 1G and 1H, the remaining silicon nitride layer was removed with a hot acid solution, and then the dicing layer 11 was etched away with a diluted hydrofluoric acid solution, and then the trench was removed when the oxide layer was removed. The edges are protected by the inside of the trench and a third oxide layer 18 extending from about 200 angstroms to 600 angstroms. (Please read the notes on the back of the praise before filling out this page.) ------------ Order -------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 This paper size is applicable to Chinese national standards ( CNS) A4 size (210 X 297 mm)