A? B7 4 3 91 ^8 五、發明説明（） 5-1發明領域： (請先閱讀背面之注意事項再填寫本頁) 本發明係有關於一種淺隔離溝（shallow trench isolation)製程中，防止淺隔離溝中的氧化矽層形成凹陷 (re cess)的方法，特別是有關於一種 0.25徽米（micro η) 或以下的淺隔離溝製程中，防止淺隔離溝中的氧化矽層形 成凹陷的方法。 5-2發明背景： 在製造一個電晶體的時候，當電晶體體積縮小時， 經濟部中夾標苹局員工消費合作社印製 用以作為絕緣的技術由區域場氧化法（LOCOS)進步到淺 隔離溝（shallow trench isolation: STI)製程，尤其是當 線寬由0.35微米縮小到0-25微米以下時，通常都使用淺 隔離溝製程作為元件之間絕緣的方法。在製造電晶體的時 候，傳統的淺隔離溝製程如下所述。首先參考第一圖，提 供底材100，並依順序在底材100上形成墊氧化層（pad oxide)101以及敗化梦層102»其次，參考第二圖，於氮 化矽層102上形成光阻圖案層103,並接著蝕刻此半導體 晶圓。藉此，在底材1 00中形成淺溝1 04，並且也定義了 電晶體的主動區域。然後在淺溝104中形成熱氧化層 105，而此熱氧化層105是由氧化矽所組成。 接著去除該光阻圖案層103，然後在整個半導體晶 圓上以化學氣相沉積法（Chemical Vapor Deposition: CVD)沉積上一層氧化矽層，並接著對此氧化矽層進行一 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4 3 91 9 S' ^ A 7 B7 五、發明説明（） 化學機械研磨（Chemical Mechanical Polish : CMP)。然 後參考第三圊，除去氮化矽層102，並且以一第一氩氟酸 溶液去除墊氧化層101,其中的第一氫氟酸溶液是以氫氟 酸與襄化氣（ammonium fluoride)依照1:10的比例混合， 而第—氫氟酸溶液以15秒鐘去除墊氧化層101。同時參 考第四圖’隔離溝1 06的角被蝕刻，並且使得隔離溝1 〇6 在角的地方向後退縮。除此之外，底材1〇〇也因此步驟 而裸露出來。猜考第五圖，下一個步驟是要在底材1〇〇 上’形成一個犧牲氧化層108，然後以離子植入步驟來形 成電晶體中的主動區（active a re a)中的通道。 下一個步驟是以一個第二氫氟酸溶液來去除犧牲 氧化層108’參考第六圖，因此犧牲氧化層1〇8是去除 了’然而同時隔離溝106的角卻也同時被钱刻掉了。其 中的第二乱氧酸溶液是以氫數酸與氟化氨（amrn〇niUtT| f丨u o r i d e)依照1:1 〇 〇的比例混合’而第二氫氟酸溶液以 3 0 0秒鐘去除犧牲氧化層1 〇 8。藉此，隔離溝彳〇 6就被形 成於底材100之中了。接著的步驟是要形成一個電晶體， 首先在底材1 0 0以及隔離溝1 0 6上形成一個閘極氧化層 1 1 〇，然後沉積一個閘極複晶矽層1 1 2於閘極氧化層1 ·] 〇 上。其中顯然因為隔離溝1 06角的退縮，所以會在隔離 溝106的角上形成凹陷120。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之这意事項再填寫本頁} 此外’若用上述的淺溝來做電晶體之間的絕緣，還 有一些傳統的步驟用以製造電晶體》在一串的製造電晶體 的步驟之後，所形成上述電晶體的上視圖如第八圖所示。 3 本紙張尺度適用中國國家標率(CNS )八4規格（2〗〇X 297公及）A? B7 4 3 91 ^ 8 V. Description of the invention () 5-1 Field of invention: (Please read the notes on the back before filling out this page) The present invention relates to a shallow trench isolation process. Method for preventing silicon oxide layer in shallow isolation trench from forming recesses, in particular to a shallow isolation trench process with a thickness of 0.25 micrometers or less, preventing silicon oxide layer in shallow isolation trenches from forming depressions Methods. 5-2 Background of the Invention: When manufacturing a transistor, when the transistor size shrinks, the technology printed by the Apple Bureau Consumers Cooperative in the Ministry of Economic Affairs to be used as insulation has progressed from LOCOS to shallow. Shallow trench isolation (STI) process, especially when the line width is reduced from 0.35 micrometers to 0-25 micrometers, usually uses a shallow trench isolation process as a method of insulation between components. When manufacturing transistors, the traditional shallow isolation trench process is described below. First refer to the first figure, provide a substrate 100, and form a pad oxide layer 101 and a degraded dream layer 102 on the substrate 100 in order. Second, refer to the second figure, and form on the silicon nitride layer 102. The photoresist pattern layer 103 is then etched to the semiconductor wafer. Thereby, shallow grooves 104 are formed in the substrate 100, and the active area of the transistor is also defined. A thermal oxide layer 105 is then formed in the shallow trench 104, and the thermal oxide layer 105 is composed of silicon oxide. Next, the photoresist pattern layer 103 is removed, and then a silicon oxide layer is deposited by chemical vapor deposition (CVD) on the entire semiconductor wafer, and then the silicon oxide layer is subjected to a paper standard suitable for China National Standard (CNS) A4 specification (210X297 mm) 4 3 91 9 S '^ A 7 B7 V. Description of the invention () Chemical Mechanical Polishing (CMP). Then referring to the third step, the silicon nitride layer 102 is removed, and the pad oxide layer 101 is removed with a first argon fluoride solution. The first hydrofluoric acid solution is based on hydrofluoric acid and ammonium fluoride. The ratio of 1:10 is mixed, and the first hydrofluoric acid solution removes the pad oxide layer 101 in 15 seconds. At the same time, referring to the fourth figure, the corner of the isolation trench 106 is etched, and the isolation trench 106 is retracted in the direction of the ground of the corner. In addition, the substrate 100 is exposed by this step. Guessing the fifth figure, the next step is to form a sacrificial oxide layer 108 'on the substrate 100, and then an ion implantation step is used to form a channel in the active area of the transistor. The next step is to remove the sacrificial oxide layer 108 with a second hydrofluoric acid solution. Refer to the sixth figure, so the sacrificial oxide layer 108 is removed. However, at the same time, the corner of the isolation trench 106 is also engraved by money. . The second oxyhydrogen acid solution is a mixture of hydrogen acid and ammonium fluoride (amrn〇niUtT | fuouoride) in a ratio of 1: 1 00 ′, and the second hydrofluoric acid solution is removed in 300 seconds. Sacrificial oxide layer 108. As a result, the isolation trench 06 is formed in the substrate 100. The next step is to form a transistor. First, a gate oxide layer 1 1 0 is formed on the substrate 100 and the isolation trench 106, and then a gate polycrystalline silicon layer 1 1 2 is deposited on the gate oxide. Layer 1]] 〇. Obviously, a recess 120 is formed on the corner of the isolation trench 106 because of the shrinkage of the isolation trench 106. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read this notice on the back before filling out this page) In addition, 'If the above shallow trench is used for insulation between transistors, there are some traditional steps for manufacturing "Transistor" After a series of steps for manufacturing the transistor, the top view of the transistor as shown above is shown in Figure 8. 3 This paper size applies to China National Standards (CNS) 8 4 specifications (2) 0X 297 Public)
五、發明説明（） 其t位於虛線矩形與實線矩形之間的區域就是隔離溝 1〇6的區域，並且其中的實線矩形也鄰接於閘極以及源 極，而1隔離溝106也與複晶矽閘極有重疊的部分。依 據線段a a所做的電晶體剖面圖，接近線段a a,右侧的a， 蠕之剖面圖顯示於第九圖中。 如第九圖所示，當氧化梦凹陷變得更大時，會使得 扭曲效應變得更為嚴重。扭曲效應，或者說是通道邊緣的 臨界電壓之減少，總是會在淺隔離溝邊緣的絕緣與導通區 域之邊界上發生，也因此而導致了製作淺隔離溝製程的餘 (process w丨ndow)變小》所以為了要盡量降低扭曲效 應，必須要盡量減少凹陷1 2 0。 5_3發明目的及概述： 鑒於上述之發明背景中，傳統形成隔離溝的方法會 使其具有扭曲效應（kink effect)，並且使得使用該隔離溝 的電子元件之電性（electrical characteristic)不佳。所以 本發明的目的乃是要提供一種形成不會產生扭曲效應的 隔離溝’使得使用該隔離溝的電子元件之電性獲得改善 本發明的另一目的在提供一種使用於元件線寬J 於0.25微岽（miCr〇n)時，適合用於做兀件之間電性隔絕 的淺隔離溝之製程，以使得此淺隔離溝不會具有扭2效 應，而且使用此淺隔離溝做電性隔絕的凡件’也不會又到 扭曲效應的影響，所以使用本發明所形成的淺隔離溝一 件會有較佳的電性。 本紙張尺度適用中國國家楼準（CNS ) Λ4规格（210X297公漦） (請先閱讀背面之注惫事項再填莴本頁) 訂 經濟部中央標準局員工消费合作社印製 經濟部中央標準局員工消资合作社印製 4391 93 Λ7 ___Η7 五、發明説明（） 根據以上所述之目的，本發明提供一種在半導體底 材中形成隔離溝的方法，本發明所提出的方法包含下列步 驟：首先依序形成墊氧化層及氮化矽層於半導體底材上。 然後形成光阻圖案層於氮化矽層上，並蝕刻氮化矽層、墊 氧化層及半導體底材，以在半導體底材中形成溝渠。形成 第一氧化矽層於溝渠上之後，去除 '光阻圖案層。接著形成 氣氧化矽層於氮化矽層以及第一氧化矽層上，再以氧化矽 填充此溝渠以形成一二氧化梦溝渠。 然後以化學機械研磨法（Chemical Mechanical Polishing)以及第一溶液，去除氮化矽層、第一部份的氮 氧化梦層及一部份的二氧化矽溝渠。其中，氮氧化矽層包 含第一部份的氮氧化矽層及第二部分的氮氧化矽層。最後 以第一氫氟酸溶液蝕刻墊氧化層及二氧化矽溝渠以裸露 一部份的底材。第二部分的氮氧化矽層係用於防止二氧化 矽溝渠中’會產生的一氧化矽流失現象，藉以形成隔離 溝。其中上述的氮氧化矽層是以一電漿加強式化學氣相沉 積法（plasma enhanced chemical vapor deposition ： PECVD)。 5_4圓式簡單說明： 第一圖至第七圖顯示的是依據傳統製作電晶體的 方法中用於製作淺隔離溝（sha丨low trench isolation)的一 連串製程。 第一圖顯示的是在底材上依序沈積一墊氧化層以 本紙張尺度適用中國國家標準（CNS ) Α4規格< 210 χ 297公龄） (請先閱讀背而之注意事項再填^本頁) "° • Λ. 4 3 91 9 8' 經濟部中央標準局員工消費合作社印製 Λ7 B7_五、备明説明（） 及一氮化矽層之後的晶圓剖面圖。 第二圖顯示的是在底材中形成淺溝（sha丨丨〇w trench)，並且在上述淺溝表面形成一氧化矽層之後的晶 圓剔面圖σ第三圖顯示的是在淺溝中形成化學氣相沈積 (Chemical Vapor deposition)的氧化矽，並且經過化學機械研 磨（Chemical Mechanical P〇丨ishing)之後的晶圓剖面囷。 第四圖顯示的是依據傳統的方法，在蝕刻墊氧化矽 層以及氣化矽層時，對化學氣相沈積的氧化矽之邊角造成 钱刻，同時完成淺溝之後的晶圓剖面圖。 第五圖顯示的是使用離子植入，以形成使用傳统漫 隔離溝電晶體之通道（channel) c 第六圖顯示的是犧牲氧化層被去除後，同時對化學 氣相沈積的氧化矽之邊角造成進一步蝕刻後的晶圓剖面 圖。 第七圖顯示的是在半導體底材以及淺隔離溝上依 序形成閘極氧化層以及閘極複晶矽層之後的晶圓剖面 圖。 第八圖顯示的是電晶體結構的上視圖。 第九圖使用淺隔離溝的部份剖面圖以顯示導致扭 曲效應的原因。 第十圖至第十七圖顯示的是依據本發明的方法，製作電阳髅中的淺隔離溝（shallow trench isolation)之一連 串製程》 6 本纸張尺度 t _ ^；(cNs)^(2IOX 297^y ^ ——- ο裝！ (請先閱讀背面之注意事if再填跨木頁j 、-° Ί —.1. 4 3 91 9 8 B7 經濟部中央標準局員工消费合作社印裝 五、發明説明（ 第十圖所顯示的是在底材上依序沈積一墊氧化層 以及一氮化矽層之後的晶圓剖面圖。 第十一圖顯示的是依據本發明在底材中形成淺溝 (shallow trench)’並且在上述淺溝表面形成一氧化矽層 之後的晶圓剖面圖。 第十一圖顯示的是依據本發明，在上述的淺溝以及 il化梦潛表面形成一層氮氧化矽層之後的的晶圓剖面 圖。 第十三圖顯示的是在上述淺溝中形成化學氣相沈 積（Chemical Vapor deposition)的氧化矽之後的晶圓剖面圖。 第十四圖顯示的是對上述淺溝中形成化學氣相沈 積的氧化碎，並且經過化學機械研磨（Chemjca| Mechanical Polishing)之後的半導體晶圓剖面圖，其中的氮化矽層已經 被强刻掉。 第十五圖顯示的是依據本發明的步驟，在蝕刻完墊 氧化層後的晶圓剖面圖，其中氮氧化矽層的邊角之高度高 於化學氣相沈積的氧化矽的其餘部份之高度。 第十六圖顯示的是在導體晶圓表面上形成一犧牲 氡化層，並且用離子植入法形成依據本發明所形成之淺隔 離溝電晶體的通道（channel)。 第十七圈顯示的是本發明的製稂中，形成於離子植 入步驟之前的犧牲氧化層被去除後的半導體晶圓之剖面 圖’其中氮氧化梦層之邊肖高於化學氣相沈積的氧化矽之 高度。 本紙浪尺度適用中國國家標準（CNS ) A4規格（210 X297公炖） (請先閱讀背而之注意事項再填寫本頁) "0 4 3 91 9 8 Λ7 _____B7 五、發明説明（） ~ 第十八圖顯示的是在半導體底材以及淺隔離溝上 依序形成閘極氧化廣以及閘極複晶矽層之後的晶圓剖面 圖。 第十九圊顯示的是使用依據本發明的方法形成淺 隔離溝之後的半導體晶圓之部份剖面圖’以顯示導致扭曲 效應的氧化氣凹陷已經被消除。 5-5發明詳細說明： 本發明提供一種方法，以去除淺隔離溝製程中所產 生的凹陷’特別是有關於一種微米或以下的淺隔離 溝製程。傳統用以形成隔離溝的方法，會因為淺隔離溝氧 化石夕中的凹陷而導致扭曲效應的產生，所以本發明提供防 止淺隔離溝中產生氧化矽凹陷的製程。例如，在製造一個 電晶體時，參考第十圖’提供一個底材2 0 0，然後依序在 底材200上沉積上一層墊氧化層2〇1以及一層氮化矽層 202’其厚度分別是墊氧化層2〇1厚度約為1〇〇至2〇〇 埃（angstroms)’氮化矽層202厚度約為1000至2000 經濟部中央標準局員工消費合作社印裂 ί請先閱讀背面之注意事項再填碎本頁) ---- 埃。其次，參考第Η 圖’於氮化石夕層202上形成光阻 圊案層203，並接著蚀刻此半導體晶圓，也就是蝕刻墊氧 化層201、氮化矽層202以及底材200。藉此，在底材 2〇0中形成淺溝204,並且也定義了所要製造的電晶體（未 圖示）的主動區域。然後在淺溝204中形成熱氧化層 205’而此熱氧化層205是由氧化矽所組成。如第十一圖 所示’熱氧化層205是由一個熱處理步驟產生在半導體 本紙乐尺度適用中國國家標毕（CNS ) Α4規格（21〇Χ297公兹） 43 91 9 8 B7 五、發明説明（） 晶圓的淺隔離溝之中的。 接著以一電续加強式化學氣相沉積法（p!asma enhanced chemical vapor dep〇siti〇n: pECVD)’ 以在 整個半導體晶圓上形成一層氮氧化矽層，參考第十二圖， 因此在淺溝204中的熱氧化層2〇5上，形成了一層氮氧 化矽層208,其中的氮氧化矽層208之厚度大約為50-600 埃（angstroms)。而用來進行上述的電漿加強式化學氣相 沉積法之功率，在高頻率（大約為1356百萬赫茲）時，大 約為350瓦特（Watt)，而在低頻率（大約為2〇〇_4〇〇千赫 茲）時，大約為0-200瓦特。氮氧化矽層2〇8是Sj〇xNy由 所構成，而且用來形成Si0xNy的是流量大約為每分鐘兩千 立方釐来的所以本發明的實施例中Si〇xNy的y 的範圍分別如下，0.8妄d.2並且〇15客yS〇4。參考第十 三圖，T一個步驟是在半導體晶圓表面上，用化學氣相沉 積法在淺溝204中形成氧化梦層，以形成隔離溝209。 接著毁半導體晶圓表面平坦化，並且同時以一個化 學機械研磨法（Chemica丨 Mechanics P〇丨jsh: CMp)，以 去除氣化矽層202’然後以磷酸以去除殘餘的氤化矽層 2〇2,其半導體晶圓的剖面圖顯示於第十四圖中。因為字 使用化學機械研磨法時，同時研磨兩種不同的材質（氮化 石夕層2〇2以及氮氧化梦層2〇8)，所以氣氡化石夕層2〇8的 頂部高於塾氧化廣201。因為前述的殘餘之氣化石夕層2〇2 二：酸所去除的’所以氣氧切層2〇8中的I 之…以忽略。接著參考第十五圖，以一 背 之 意 亊 項 再. 填， 寫 本 頁 裝 訂 經濟部中央標华局負工消費合作社印製 9 4 3 91 9 8 A1 —___________B7 __ 五·、發明説明（〉 ^ ^~ 液去除墊氧化層201,其中的第一氫氟酸溶液是以氫氟酸 與I化氨（a m m ◦ η丨u巾f | u 0 r j d e)依照1:1 0的比例還人 σ ’而 且第一氫氟酸溶液以60秒去除墊氧化層201。如第十五 圖所示，因為氮氧化矽層2〇8的頂端保護隔離溝2〇9免 於側向蝕刻。所以隔離溝209的邊角上的氧化矽的流失 可以被大量的降低，故氮氧化矽層2〇8以及隔離溝2〇9 的邊角上的氧化矽之高度大於熱氧化層205之高度。因 此’底材200就被裸露出來，參考第十六圖，下—個步 驟是在底材200以及隔離溝209上形成一個犧牲氧化層 218’並且以離子植入步驟來形成電晶體中的主動區 (active area)中的通道（channel)。 經濟部中央標準局貝工消费合作·社印製 下一個步驟是以一第二氫氟酸溶液去除犧牲氧化 層218，參考第十七圖，犧牲氧化層218 士除之後，雖然 隔離溝209也被侵蝕，但是因為有氮化梦層208的保護， 所以隔離溝2 0 9沒有被大量的侧向蝕刻，所以隔離溝2 0 9 的邊角上不會產生凹陷。縱使隔離溝2〇9的邊角上會有 凹陷’因為氮氧化矽層208將隔離溝209以及熱氧化層 2 0 5隔離開來，所以上述的凹陷會遠離液離隔離溝的側 壁，所以用上述方法所形成的淺隔離溝絕緣不會產生扭曲 效應。在去除犧牲氧化層218時，是用第二氫氟酸溶液 去除’其中第二氫氟酸溶液是由1:100的氫氟酸與氟化 氨（ammonium fluoride)混合而成。藉此，隔離溝209就 被形成於底材2 0 0之中了。若用上述的淺溝來做電晶體 之間的絕緣’還須有一些傳統的步驟用以製造電晶艘。在 本紙張尺度適用中國國家標準（CN'S ) A4規格（210X29?公淹） 4391 9 8 Λ7 B7 五、發明説明（） 一連串的製造電晶體的步驟之後，參考第十八圖，後續步 驟是於底材200以及隔離溝2〇9上’形成閘極氧化層 220。接著沉積一閘極複晶矽層222於閘極氡化層22〇 上。 在一連_形成電晶體的製程步驟之後，上述電晶體 的結構之上視圖與第八圖中所示的結構相同，依據線段 aa’所做的電晶體剖面圖，接近線段aa，右侧的a,端之剖 面圖顯示於第十九圖中。#第十九圖戶斤卜即使在隔離溝 209中有凹陷發生時，因為有氮氧化石夕層2〇8將隔離溝 209以及.熱氧化層205隔離，所以上述的凹陷會遠淺離隔 離溝的側壁，故用上述方法所形成的淺隔離溝絕緣不會產 生扭曲效應。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍；凡其它未脫離本發明所揭示 之精神下所完成之等效改變或修飾，例如使用不同的蝕刻 劑，只要形成介電質層以使得產生凹陷的區域遠離隔離溝 侧壁，以使得所形成之元件得以避免扭曲效應者，均應包 含在下述之申請專利範圍内。 請 閱 讀 背 ιέ 之 ，士V. Description of the invention () The area where t lies between the dotted rectangle and the solid rectangle is the area of the isolation trench 106, and the solid rectangle is also adjacent to the gate and the source, and the isolation trench 106 is also connected to There is an overlapped part of the compound silicon gate. The cross section of the transistor according to line a a is close to line a a and right a. The cross section of the creep is shown in the ninth figure. As shown in the ninth figure, when the oxidized dream depression becomes larger, the distortion effect becomes more serious. The distortion effect, or the reduction of the critical voltage at the edge of the channel, always occurs at the boundary between the insulation and conduction area of the edge of the shallow isolation trench, which also leads to the process process of making the shallow isolation trench. "Small" so in order to minimize the distortion effect, we must minimize the depression 1 2 0. 5_3 Purpose and Summary of the Invention: In view of the above background of the invention, the traditional method of forming the isolation trenches has a kink effect, and makes the electrical characteristics of the electronic components using the isolation trenches poor. Therefore, the object of the present invention is to provide an isolation trench that does not produce a twisting effect, so that the electrical properties of electronic components using the isolation trench are improved. Another object of the present invention is to provide a line width J of the element that is less than 0.25. When miCrOn is used, it is suitable for the process of making shallow isolation trenches for electrically isolating components, so that the shallow isolation trenches do not have the twist 2 effect, and the shallow isolation trenches are used for electrical isolation. Every piece of 'will not be affected by the twisting effect, so a piece of shallow isolation trench formed using the present invention will have better electrical properties. This paper size applies to China National Building Standard (CNS) Λ4 specification (210X297 gong) (Please read the notes on the back before filling out the lettuce page) Subscribe to the staff of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by a consumer cooperative 4391 93 Λ7 ___ Η7 V. Description of the invention () According to the above-mentioned purpose, the present invention provides a method for forming an isolation trench in a semiconductor substrate. The method proposed by the present invention includes the following steps: first in order A pad oxide layer and a silicon nitride layer are formed on the semiconductor substrate. Then a photoresist pattern layer is formed on the silicon nitride layer, and the silicon nitride layer, the pad oxide layer and the semiconductor substrate are etched to form a trench in the semiconductor substrate. After the first silicon oxide layer is formed on the trench, the photoresist pattern layer is removed. An aerobic silicon oxide layer is formed on the silicon nitride layer and the first silicon oxide layer, and the trench is filled with silicon oxide to form a dream dioxide trench. Then chemical mechanical polishing (Chemical Mechanical Polishing) and the first solution are used to remove the silicon nitride layer, the first part of the oxynitride layer and the part of the silicon dioxide trench. The silicon oxynitride layer includes a first silicon oxynitride layer and a second silicon oxynitride layer. Finally, the first hydrofluoric acid solution is used to etch the pad oxide layer and the silicon dioxide trench to expose a part of the substrate. The second part of the silicon oxynitride layer is used to prevent the loss of silicon monoxide in the silicon dioxide trench, thereby forming an isolation trench. The silicon oxynitride layer is a plasma enhanced chemical vapor deposition (PECVD) method. 5_4 round type brief description: The first to seventh figures show a series of processes for making shallow trench isolation in the traditional method of making a transistor. The first picture shows the sequential deposition of a pad of oxide layer on the substrate. The Chinese National Standard (CNS) A4 specification < 210 χ 297 male age is applied at this paper size. (Please read the precautions before filling in the following ^ (In this page) ° Λ. 4 3 91 9 8 'Printed Λ7 B7_5, a note () and a silicon cross section of the wafer after the consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. The second image shows a wafer picking surface after a shallow trench is formed in the substrate and a silicon oxide layer is formed on the surface of the shallow trench. The third image shows a shallow trench. In the process, a chemical vapor deposition (Chemical Vapor deposition) of silicon oxide is formed, and the wafer cross section 经过 after chemical mechanical polishing (Chemical Mechanical Po ishing). The fourth figure shows the traditional method of etching the pad silicon oxide layer and the vaporized silicon layer, causing the corners of the chemical vapor deposited silicon oxide to be engraved, and at the same time completing the wafer cross-section view after the shallow trench. The fifth figure shows the use of ion implantation to form a channel using a conventional diffuse isolation trench transistor. The sixth figure shows the side of the chemical vapor deposition silicon oxide after the sacrificial oxide layer is removed. The corners result in a cross-sectional view of the wafer after further etching. The seventh figure shows a cross-sectional view of a wafer after a gate oxide layer and a gate polycrystalline silicon layer are sequentially formed on a semiconductor substrate and a shallow isolation trench. Figure 8 shows a top view of the transistor structure. Figure 9 uses a partial cross-section view of the shallow isolation trench to show the cause of the twisting effect. The tenth to seventeenth figures show a series of processes for making a shallow trench isolation in a solar cell according to the method of the present invention. 6 Paper size t_ ^; (cNs) ^ (2IOX 297 ^ y ^ ——- ο installed! (Please read the notes on the back if and then fill in the cross-page j,-° Ί —.1. 4 3 91 9 8 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Explanation of the invention (The tenth figure shows a cross-sectional view of a wafer after a pad oxide layer and a silicon nitride layer are sequentially deposited on the substrate. The eleventh figure shows the formation in the substrate according to the present invention. A cross-sectional view of a wafer after a shallow trench is formed on the surface of the shallow trench, and a silicon oxide layer is formed on the surface of the shallow trench. FIG. Cross section of the wafer after the silicon oxide layer. The thirteenth figure shows the cross section of the wafer after the chemical vapor deposition of silicon oxide is formed in the shallow trench. The fourteenth figure shows the For the oxidized particles formed by chemical vapor deposition in the shallow trench, A cross-sectional view of the semiconductor wafer after chemical mechanical polishing (Chemjca | Mechanical Polishing), in which the silicon nitride layer has been strongly etched. The fifteenth figure shows the step of etching the pad oxide layer in accordance with the present invention. The subsequent wafer cross-section view, in which the height of the corners of the silicon oxynitride layer is higher than the height of the rest of the chemical vapor deposited silicon oxide. Figure 16 shows the formation of a sacrificial puppet on the surface of the conductor wafer. Layer, and the channel of the shallow isolation trench transistor formed according to the present invention is formed by the ion implantation method. The seventeenth circle shows the sacrifices formed before the ion implantation step in the fabrication of the present invention. Sectional view of the semiconductor wafer after the oxide layer is removed, 'The edge of the nitrogen oxide oxide layer is higher than the height of chemical vapor deposited silicon oxide. The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X297 male stew) ) (Please read the precautions before filling this page) " 0 4 3 91 9 8 Λ7 _____B7 V. Description of the invention () ~ The eighteenth figure shows the semiconductor substrate and the shallow isolation trench Sectional view of the wafer after the gate oxide and gate compound silicon layer are sequentially formed. The nineteenth part (a) shows a partial cross-sectional view of a semiconductor wafer after forming a shallow isolation trench using the method according to the present invention. Oxidation gas depressions that have been shown to cause twisting effects have been eliminated. 5-5 Detailed description of the invention: The present invention provides a method to remove depressions generated in a shallow isolation trench process, particularly regarding a micron or less shallow isolation trench process. The traditional method for forming the isolation trenches will cause the distortion effect due to the depressions in the oxide trenches of the shallow isolation trenches. Therefore, the present invention provides a process for preventing the generation of silicon oxide depressions in the shallow isolation trenches. For example, when manufacturing a transistor, refer to the tenth figure 'provide a substrate 200, and then sequentially deposit a pad oxide layer 201 and a silicon nitride layer 202' on the substrate 200, respectively. The thickness of the pad oxide layer 001 is about 100 to 200 angstroms. The thickness of the silicon nitride layer 202 is about 1000 to 2000. The print is printed on the consumer consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Please read the note on the back first. Matters fill this page again) ---- Egypt. Next, referring to the second figure, a photoresist layer 203 is formed on the nitride nitride layer 202, and then the semiconductor wafer is etched, that is, the pad oxide layer 201, the silicon nitride layer 202, and the substrate 200 are etched. Thereby, a shallow trench 204 is formed in the substrate 200, and an active region of a transistor (not shown) to be manufactured is also defined. A thermal oxide layer 205 'is then formed in the shallow trench 204, and the thermal oxide layer 205 is composed of silicon oxide. As shown in Figure 11, 'The thermal oxide layer 205 is produced by a heat treatment step. It is applicable to Chinese National Standards (CNS) A4 specifications (21〇297297) at the semiconductor paper scale. 43 91 9 8 B7 V. Description of the invention ( ) In the shallow isolation trench of the wafer. Next, a p! Asma enhanced chemical vapor depOsition (pECVD) 'was used to form a silicon oxynitride layer on the entire semiconductor wafer. Referring to the twelfth figure, A silicon oxynitride layer 208 is formed on the thermal oxide layer 205 in the shallow trench 204, and the thickness of the silicon oxynitride layer 208 is about 50-600 angstroms. The power used to perform the above plasma enhanced chemical vapor deposition method is about 350 Watts at high frequencies (about 1356 megahertz), and at low frequencies (about 200_ 400 kHz), which is about 0-200 watts. The silicon oxynitride layer 208 is composed of SjOxNy, and the flow rate for forming Si0xNy is about two thousand cubic centimeters per minute. Therefore, the ranges of yxNy's y in the embodiment of the present invention are as follows, 0.8 d.2 and 0.15 yS04. Referring to the thirteenth figure, a step T is to form an oxide dream layer in the shallow trench 204 by chemical vapor deposition on the surface of the semiconductor wafer to form an isolation trench 209. Then the semiconductor wafer surface is destroyed and planarized, and at the same time, a chemical mechanical polishing method (Chemica 丨 Mechanics P〇 丨 jsh: CMp) is used to remove the vaporized silicon layer 202 ′ and then phosphoric acid is used to remove the residual silicon oxide layer 2〇 2. A cross-sectional view of the semiconductor wafer is shown in the fourteenth figure. When the chemical mechanical polishing method is used, two different materials are simultaneously polished (nitride stone layer 002 and oxynitride dream layer 208), so the top of the gas-fossilized layer 208 is higher than that of the oxidized layer. 201. Because of the aforementioned residual gasified fossil layer 002: acid removed, the I in the gas-oxygen cut layer 208 ... is ignored. Then refer to the fifteenth figure, and reiterate the items with the meaning of one back. Fill in, write this page and bind it. Printed by the Central Bureau of Standardization of the Ministry of Economic Affairs and Consumer Cooperatives. 9 4 3 91 9 8 A1 —___________ B7 __ V. Description of the invention ( 〉 ^ ^ ~ Liquid removal pad oxide layer 201, wherein the first hydrofluoric acid solution is returned to the people with hydrofluoric acid and ammonia (amm ◦ η 丨 u towel f | u 0 rjde) according to the ratio of 1: 10 σ 'and the first hydrofluoric acid solution removes the pad oxide layer 201 in 60 seconds. As shown in FIG. 15, because the top of the silicon oxynitride layer 208 protects the isolation trench 209 from lateral etching. Therefore, the isolation The loss of silicon oxide on the corners of the trench 209 can be greatly reduced, so the height of the silicon oxide on the corners of the silicon oxynitride layer 208 and the isolation trench 209 is greater than the height of the thermal oxide layer 205. Therefore, ' The substrate 200 is exposed. Referring to the sixteenth figure, the next step is to form a sacrificial oxide layer 218 'on the substrate 200 and the isolation trench 209 and to form an active region in the transistor by an ion implantation step ( channel in the active area. The Central Bureau of Standards of the Ministry of Economic Affairs The next step of printing is to remove the sacrificial oxide layer 218 with a second hydrofluoric acid solution. Referring to the seventeenth figure, after the sacrificial oxide layer 218 is removed, although the isolation trench 209 is also eroded, but because of the nitrided dream layer 208 protection, so the isolation trench 2 0 9 has not been etched by a large number of sides, so there will be no depressions in the corners of the isolation trench 2 0. Even if there are depressions in the corners of the isolation trench 2 09 'because of nitrogen oxidation The silicon layer 208 isolates the isolation trench 209 and the thermal oxidation layer 205, so the above-mentioned depression will be far away from the side wall of the liquid separation isolation trench, so the shallow isolation trench insulation formed by the above method will not produce a twisting effect. When the oxide layer 218 is sacrificed, it is removed with a second hydrofluoric acid solution, wherein the second hydrofluoric acid solution is a mixture of 1: 100 hydrofluoric acid and ammonium fluoride. Thus, the isolation trench 209 It is formed in the substrate 200. If the above shallow trench is used as the insulation between the transistors, there must be some traditional steps to manufacture the transistor boat. In this paper standard, Chinese national standards apply. (CN'S) A4 size (210X29? Male 4391 9 8 Λ7 B7 V. Description of the invention () After a series of steps for manufacturing the transistor, referring to the eighteenth figure, the next step is to form a gate oxide layer 220 on the substrate 200 and the isolation trench 209. Then A gate polycrystalline silicon layer 222 is deposited on the gate halide layer 22. After a process step of forming a transistor, the top view of the structure of the transistor is the same as the structure shown in the eighth figure, according to The cross-sectional view of the transistor made by the line segment aa 'is close to the line segment aa, and the cross-section view of the right side a and the end is shown in the nineteenth figure. # 第 19 图 Hu Jinbu Even when there is a depression in the isolation trench 209, the isolation trench 209 and the thermal oxidation layer 205 are isolated by the nitrogen oxide layer 208, so the above depression will be far away from the isolation. The side walls of the trench, so the shallow isolation trench insulation formed by the above method will not produce a twisting effect. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention, such as using different etchings Agents, as long as the dielectric layer is formed so that the recessed area is far from the side wall of the isolation trench, so that the formed element can avoid distortion effects, should be included in the scope of the patent application described below. Please read me
I i 訂 I 、- 經濟部中央標準局貝工消費合作社印策 本紙張尺度逋用中國國家標準（CNS ) A4規格（210 X 297公釐）I i Order I 、-Printing policy of Beigong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs This paper uses China National Standard (CNS) A4 (210 X 297 mm)