TW411592B - Accelerated isothermal integrating method for manufacturing semiconductor device - Google Patents

Accelerated isothermal integrating method for manufacturing semiconductor device Download PDF

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Publication number
TW411592B
TW411592B TW087117545A TW87117545A TW411592B TW 411592 B TW411592 B TW 411592B TW 087117545 A TW087117545 A TW 087117545A TW 87117545 A TW87117545 A TW 87117545A TW 411592 B TW411592 B TW 411592B
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Taiwan
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component
scope
patent application
manufacturing
item
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TW087117545A
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Xieoming Xie
Zhongzhe Shen
Juergen Freytag
Frank Stubhan
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Daimler Benz Ag
Shanghai Inst Metallurg
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/10Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating making use of vibrations, e.g. ultrasonic welding
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    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
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Description

411592 Λ7 B7 S9等6月16日修正 五、發明说明(〗) 本發明係關於半導«構件以及構件之等溫結合製法, 尤指具有微電子晶片和戰値之電子構件。 (对先抑锖背而之注意事項再访巧本菸
已知有等溫凝固法以製造構件,尤其是在基材上安裝 積體微電子構件。此種方法參.見例如DE-A-C 95 3 1 1 5S 所記載。 訂 於此先把微電子構件和散熱座與金屬積層,其中使用 至少一低熔點和一*髙熔點金屬。金屬層直按接觸,以預定 的溫度過程加溫,在反應期間壓在一起,直至低熔點金屬 與高熔點金屬的反應終止。於是,低熔點成份摻透入高熔 點成份內,成爲化合物層,在明顯較高溫度,一如低熔點 成份的熔點穩定。一旦此等溫凝固反應結束,化合物即堅 固。此製法可在電子材料適用溫度最高約300Ό範圍持續 60分鐘,以在真空烘箱內進行爲佳。在整個結合時間中, 二個別部份結合在一起時,必須對化合物處施加結合過程 所需的較高壓力。 _ 雖然此項金屬化合物技藝,可將微電子構件極優異地 加溫直接聯結於隨意的肆熱座或隨意的熱支架,但等溫凝 固方法由於微電子構件的商業化製法中持續數分鐘的結合 時間,在晶片裝上載體時,典型上只數秒的過程即不.合。 爲減少構件必須壓在一起的總體反應時間以及結合時 間,使化合物層在此時間內凝固或完成反應,擬議選用物 料組成份,提供較高成長率*於等溫凝固時形成金屬間的 相。降低反應時間的另一措施是,擬議減-少活性金屬層的 厚度。在許多系統中,把層厚減半,可使反應時間減到四 木紙汝尺度ii州肀ΚΚ家作?ΐ ( (,NS >以規枋u丨0·〆297公釐) 411592 Λ7 B7 S9等6月16日修正 五、發明说明(〗) 本發明係關於半導«構件以及構件之等溫結合製法, 尤指具有微電子晶片和戰値之電子構件。 (对先抑锖背而之注意事項再访巧本菸
已知有等溫凝固法以製造構件,尤其是在基材上安裝 積體微電子構件。此種方法參.見例如DE-A-C 95 3 1 1 5S 所記載。 訂 於此先把微電子構件和散熱座與金屬積層,其中使用 至少一低熔點和一*髙熔點金屬。金屬層直按接觸,以預定 的溫度過程加溫,在反應期間壓在一起,直至低熔點金屬 與高熔點金屬的反應終止。於是,低熔點成份摻透入高熔 點成份內,成爲化合物層,在明顯較高溫度,一如低熔點 成份的熔點穩定。一旦此等溫凝固反應結束,化合物即堅 固。此製法可在電子材料適用溫度最高約300Ό範圍持續 60分鐘,以在真空烘箱內進行爲佳。在整個結合時間中, 二個別部份結合在一起時,必須對化合物處施加結合過程 所需的較高壓力。 _ 雖然此項金屬化合物技藝,可將微電子構件極優異地 加溫直接聯結於隨意的肆熱座或隨意的熱支架,但等溫凝 固方法由於微電子構件的商業化製法中持續數分鐘的結合 時間,在晶片裝上載體時,典型上只數秒的過程即不.合。 爲減少構件必須壓在一起的總體反應時間以及結合時 間,使化合物層在此時間內凝固或完成反應,擬議選用物 料組成份,提供較高成長率*於等溫凝固時形成金屬間的 相。降低反應時間的另一措施是,擬議減-少活性金屬層的 厚度。在許多系統中,把層厚減半,可使反應時間減到四 木紙汝尺度ii州肀ΚΚ家作?ΐ ( (,NS >以規枋u丨0·〆297公釐) 411592 A7 _ B7 五、發明説明(2 ) 分之一。層厚減少的下限值是因組件表面的粗糙度和曲率 而定。 本發明之目的,在於提供構件藉由加熱凝固之製法, 及構件,其所需結合時間不超過1分鐘。 此目的可由申請專利範圍獨立項的特徵解決。進一步 且較佳具體例見其他申請專利範圍及說明書。 因此,本發明把反應時間期間分成二個時段。第一時 段定爲結合時間期限,而第二時段爲剩餘的反應時間期 限。由組件固定結合在一起成爲單一構件的過程,是在反 應時間期限內的結合時間期限迤行,此時需要等溫凝固。 結合時間期限宜較反應時間期限爲短。 按照本發明,在結合時間期限內,對構件即二組件施 加預定效果的動態壓力,以振動能,尤其是超音波能的形 式p進一歩有利的振動能作用包含,一組件或二組件融合 了摩擦擺動,於是並列接觸面彼此互動,以代替接觸面材 料的反應過程之機械式和/或熱力式支撐。 最好是二組件至少開始時或在振動作用之際,以預定 的靜態壓力壓在一起。壓力宜只在結合時間期限對構件作 用。更有利的是振動能和壓力同時作用。振動力對組件作 用時間要比結合時間期限短,而以振動力在結合時間期限 開始時作用尤佳。 、 因此,其優點是在較必要的基本反應時距爲短的結合 時間內,組件已爲了進一步完工經機械方式達成彼此固定 結合,而等溫凝固過程繼續進行。製法特別有利的是,剩 —2 — )、紙張尺廋讳川中阁1¾家標埤(CNS ) Λ4¾¾ { 210x297^fL ) ---------^----^--1T------.^ (1A先閲讀背面之注意事項再功寫本頁) :tr?·^,屮次杖τ十^ΰ〈-τ·消贤合:;::私印丨欠 411593 A7 ______B7_ 五、發明説明(3 ) 餘反應時間期限可對別處,一如結合在一起之處,施加振 動能.α 若選用較高反應溫度,則振動能的作用宜選較短時 間。 振動能作用的較佳時間期限,在50 ms和600 ms之 間。振動能作用最多宜爲結合時間期限的70% 。超音波 功率(P1)宜採用0.3 %/〇1〇12和3 W/mm2間。 靜壓力(F1)宜採用0.2 N/mm2和1.5 N/mm2間;以盡 量大的壓力爲佳。較佳靜壓力至少I·5 N/tnm2。有利的反 應溫度在I50eC和400Ό間。反應時間期限以1〇秒至3分 鐘爲宜。 製法最奸是在惰性氣體氛圍內,於較室想爲高的溫度 進行。 第一金屬層宜爲至少一層銦,以含金和銦的組層爲 佳,和/或第二金屬層至少含金層和/或銀層。二組件在 接觸處使銦層與金層接觸尤佳。進一歩的具體例是,二絪 層接觸。 金屬層宜在擴散層上面成長。擴散層較佳厚度低於 0.5 μιη ° 金屬層的較佳厚度在3和7μπι之間,二金屬層的厚 度比例,大約按二金屬間相的比例而調節。較佳選擇是, 金屬層厚度最多爲銦層厚度之大約一半。 以絪層在薄金層上成長尤佳,保護隨意的耐磨層和阻 層。 -3 - i紙认尺度ϊΐ七t因Κ家橾( ('NS ) Λ4規格(2】Ox 297公釐) " ---^---:-----Η-------1Τ-------^ (請先閱讀背而之注意事項再祯寫本頁) A7 ____B7_ 五、發明説明(4 ) 第一組件宜由微電子晶片,尤指矽晶片構成,第二組 件宜由傳熱體,尤指矽體、陶瓷體或金屬體構成,組件間 具有化合物層,由組成份Auln和/或Auln22合金和/ 或其混合物所構成。 化合物層對一或二組件設有擴散阻體層爲佳,以鈦和 /或鈦、鎳和鉻構成更好。化合物層以可在400°C以上溫 度時安定尤佳。‘ 茲參見附圚更進一歩說明本發明基本特徴如下。附圖 中: 圖1表示具苞金屬層的二組件在彼此結合成本發明構 件前之狀態: 圓2表示本發明構件按照本發明製法結合後之狀態; 圓3爲本發明製法之溫度時間圖。 本發明以微電子爲例說明如下。本發明並不縣於此應 用範圍,也不限於實施例中所述材料,而更適合於可進行 等溫凝固法的所有材料。 等溫凝固法可在較低溫度構成很堅固的化合物,而此 化合物可在很高溫度安定並耐久。按照已知技術,此化合 物製法之基本原則是,在二高熔成份之間配置箔或塗層等 低熔點金屬中間層。此項配置是在加壓下加熱至反應溫 度,構成流體中間層。因此,不是可超越低熔點層的熔點, 便是在高熔點和低熔點成份之間發生低共熔反應。 熔化的中間層在高、低熔點成份間進行較快速的相互 擴散或反應擴散。下述熱力學平衡狀況是等溫凝固的結 -4 - 不纸张尺度这州中K ( CNS ) ΛΊ現格(210X297公釐) ---^------I------·-------^ (讳先閱讀背而之注意事項再填巧本頁) 411592 a; 五、發明説明(5 ) 果。構成固體化合物層。在反應溫度時,於化合物層內形 成的固相,在相對應選用高、低熔點成份材料時,顯示培 化溫度高於反應溫度& 圖1表示本發明製法的開始歩驟。第一組件1宜爲微 電子晶片,更好是矽晶片,在與第二組件2化合而設的接 觸側1.1,帶有第一金屬層,包含複數,尤指三個分層12、 1.3、1.4。第二組件2宜爲良好傳熱基材,對晶片〗而言, 可用做散熱座或熱支架,在爲與第一組件1化合而設的接 觸側2.1,同樣帶有金屬層,包含複數分層2.2和2.3。第 二組件2以矽基材或傳熱陶瓷或金屬基材爲佳。 分層1,〗、1.3、1.4、2.2、2.3宜由各種金屬構成。 一組件的外層熔點宜比另一組件的外層爲低。 第一組件的外層1.2宜由絪構成,層厚以3-7 μπι爲 佳。此外層1.2孤離在第二層,更好是薄層1.3上,由同 樣材料構成,與此進行結合製程,再等溫凝固反應,尤以 金層爲佳。金層1.3厚度以約0.1 μιη爲宜。此第二層1.3 若孤離在第三層1.4上,則後者在等溫凝固成份與晶片I 之間,可做爲粘膠層和/或擴散阻體層。第三層1.4目的 在於通常的層組合,鈦加鎳和鉻或類似材料。此擴散阻體 的較佳層厚約0.1 μπι。在外層1.2和擴散阻體i.4間的第 二層1.3有特別有益的結果,因爲在引起的等溫凝固反應 中,外層1.2不但由接觸處,而且由層I.3和/或組件1 的界面,會開始反應,由此防止起反臌的層序受到組件1 的污染, 孓纸乐尺度述用_中因园家楛肀—) Λ4規格(210X297公犛)一~ ---------装-----^--JST------β (誚先閱讀背而之注意事項再翊荇本頁) 411592 A7 B7 五、發明説明(6 ) 第二組件2宜同樣具有粘膠和/或擴散阻體暦2.3, 其組合和厚度一如組件1。第二組件的外層2.2宜由金構 成。金層2.2厚度宜選擇成,二組件1和2的二外層1.2 和2.2成份完全反應,構成安定的金屬間化合物,以Auin 和/或Auln,或其混合物爲佳。在以銦爲第一組件1的外 層1.2,以金爲第二組件2的外層2.2之組合中,金層厚 只有絪層厚之半/更好是絪層厚在4-7μπι間,而金層厚 在 2 μηι 〇 在選用等溫凝固用的另一反應組成份時,金屬成份的 各層厚度,適當配合隨意構成的金屬間相。高、低熔點金 屬成份的厚度比例,要選擇成使參予反應的原子數,大約 爲所構成金屬間相的組合比例。 在此具體例中選用的材料,具有彼此相容的優點。其 一爲銦熔點極低約160°C,使裝在散熱座上的構件之熱負 菏小,另一爲金在該項製程中有鈦層之保護層的用途。本 發明層配置優點爲特別簡單,因爲金和銦間不需要阻體 層。 金屬層此項配置的優點爲,低熔點成份銦必須孤離在 一組件上。因此,低熔點成份的塗層歩驟只對第二組件。 但不排除二組件設有一低熔點成份層,尤其是銦層,做爲 接觸層。 1 在等溫凝固中宜形成的相Auin和Auln2,在實賛上 較铟熔點爲高的溫度安定。如此化合物層可耐約4 50°C。 二組件1和2並列,使最好是一絪層和一金層之二外 -6 - 孓紙張尺度j中K S家榡中{ >八4現格(210/ 297公釐) ------^-----^----:--、订------線 (銪先閱讀背面之注意事項再Y寫本頁) "·渋部屮士樣""G-T消介含ft"·印# 411592 a? B7 五、發明説明(7 ) 層1.2和2.2直接接觸,隨即加溫到反應溫度T1,以相當 於至少低熔點成份的熔點爲佳,尤其是在200°C和300eC 之間。在升溫階段不需使用壓力,反應溫度T1最好未達 高熔點成份的熔點。與習知技術不同的是,此法不必在真 空爐或形成氣體氛圍內進行。在提高溫度反應時,宜在惰 性氣體內,尤指氮或氬內進行。因此,在製成中可避免成 份,尤其是絪,發‘生意外的不良氧化。金層宜經絪潤濕。 適當的惰性氣體流量在例如0」至1公升/分鐘之間。惰 性氣體氛圍爲宜,但非本發明方法之決定要件,尤奠是在 隨意自動製法中,可完金摒棄惰性氣體氛圍。 組件在整個反應時間tl宜保持反應溫度T1,對於絪 —金系統,在反應溫度3 0 0°C的反應時間tl約15秒,若 反應溫度降到200°C,則反應時間11增加到近2分鐘。 低熔點成份在反應溫度熔化,並開始擴散入高熔點成份內 反應。 本發明製法基本上至少達反應溫度T1時,二組件1 和2即以振動能開始反應時間11,並在其接觸面彼此激 盪。較佳振動能爲超音波能,更好的振動能爲摩擦擺動, 類似二組件I,2間的摩擦焊接過程之振動,於是二或只有 一組件變動,此振動能特別適用於大面積的構件,其優點 是在摩擦焊接時頻率愈小,對構件的超音波負荷愈小。 構件在結合區局部施加結合振動能爲佳。因此,本案 引進振動能有炔定性作用,作動負荷P1可選用0.3至 3W/mm2的廣範圍,以0.5至2.5 W/mmz爲佳。振動能P1 一 7 — 本紙張尺度讳州中Κ K家榡彳(CN'S 1 Λ4現格(210X 297公釐) ^iT------ 0 (钎先聞讀背而之注意事項再^-.¾本頁) A7 411592 _ 137 五、發明説明(8 ) (誚先閱讀背面之注項再填衿本頁) 頂多在結合時間期限t2作用於構件。振動能的作用時間 期限宜較結合時間期限t2爲短,頂多爲結合時間期限t2 的70¾ ,而以結合時間期限開始時對組件施加振動能尤 佳。 在同樣時間t2內,於結合區內另外對構件施加壓力 F1,使二組件I,2彼此壓在一起。構件宜同時實施超音波 能P1和壓力F1。壓力以0.2 N/mm2和1 .5 N/mm2間爲佳, 而以0.25 N/mm2和1.25 N/mm2間尤佳。典型的2x2 mm2 晶片大小,壓力以例如1 — 5 N爲宜。壓力F1選用盡量 高爲佳。 於反應溫度300°C時約15秒和20 0°C時2分鐘之間的 反應時間裡,結合時間期限t2實質上較反應時間tl爲短。 在反應溫度Tt較高時,宜縮動振動能的作用,振動時間 期限在50 ms和600 ms間,以100 ms至500 ms尤佳。 雖然在結合時間期限t2屆滿後,等溫凝固皮應尙未 結束,但二組件1,2間的化合已堅固到不需再加壓力和/ 或實施超音波能以維持二組件1,2在一起。圚2表示本發 明構件,包含二原有組件1,2,與一化合物層3牢固結合, 化合物層3以親和金和/或Auln和/或Auln2,或其混 合物。構件宜在結合區的不變反應溫度T1,把超音波能 和壓力的作闬範圍區隔*而在另一範圍內業已徹底反應, 在絪-金系統內以2-4分鐘爲佳,隨即冷卻到室溫。結 合區在結合時間期限結束後,立刻又準備另一次結合過 程。在全部反應時間tl內的完全等溫凝固反應,隨即在 —8 — ί紙張尺度进A中Κ β家榡-々((’NS ) Λ4規格(210X297公釐) '~ Λ7 411592 ___.___B7 五、發明説明(9 ) 結合製法的時間無關緊要區內進行。化合物堅固到在通常 剪力試驗中可耐例如0.6 kg/mm2。 預備製程中的典型製法程序是,構件的組件以通常工 具於最好加熱結合區內,置於第二組件上,做爲安裝表面, 尤其是散熱座,於此在結合時間期限保持另外引進超音波 能或摩擦能,隨後在剩餘的反應睁間期限內保持在反應區 內。製程關鍵的昧謂構件於製法中取放於安裝表面的時 間,以秒計範圍爲宜,使結合區在秒計動作中即可自由配 置新構件的組件。 圓3表示本發明製法的溫度時間圖。等溫凝固在結合 時間期限t2內的反應時間期限11期間,到反應溫度T1 爲止,而以反應時間期限開始時爲佳。結合時間期限t2 宜只是反應時間期限tl的一部份。 因此,本發明製法可整合於商業化製程內,對此種結 合製程只容許幾秒鐘的動作時間,尤其是結合製程可以自 動化。組件1,2在結合區內的構造、組合、化合時間合計 在5秒以內,此時間可最適化到1秒以下。 以本發明製法製成的構件具有高度傳熱性,二組件間 化合物層的電阻低,而化合物層的熔點高。如此製成的微 電子組件適合於高傳導性的支架。 最好以姻和金做爲低、高熔點金屬組份的材料組合, 因爲通常的微電子晶片,廠商已可由背面接觸金製成。此 種微電子晶片即可以極簡單方式,以習知引線框,尤其是 銅或鐵、鎳合金,特別是所謂合金42,藉等溫凝固結合, —9 — 呆紙乐尺度鸿州'('NS ) Λ4^ ( 210X297^^ ) ---^---L----¾-------ΐτ------φ (誚先閲讀背面之注$項再ΐτη本頁) Λ7 B7 五、發明説明(10 ) 成本上較有利的方式是,金部份或全部以銀取代。 在第一較佳具體例中,於引線框的晶片表面或晶體載 體上至少有相當厚度的絪層,而晶片隨後即以本發明方法 與引線框牢固結合。在成本方面有利的是,在晶片表面實 施含姻糊劑。更好是在引線框和聶片載體上要接受構件的 表面,至少預先設有銀層。 在另一較佳真體例中,於晶片背側施加相當厚度的絪 層,做爲載體預設的接觸面,尤其是絪層在層順序上與薄 鈦層和金層分開,在引線框或晶片載體的範圍,預先引進 晶片,覆以金層,其厚度配合本發明絪層厚度。若只有直 接的晶片表面塗金時,可以節省費用。其優點是可進一步 避免引線框受到姻的污染。在反應後以不剩下多餘的銦尤 佳。金層游離的引線框或晶片載體邊緣區,另設有與銦無 相容塗層。 當金層表面只構成相當於晶片表面大小時爲宜,尤其 是隨意游離的晶片表面以不滲絪的材料被覆爲佳。如此可 避免化合製程中,引線框受到熔化絪的污染。 進一步較佳且成本低廉的具體例是*在引線框或晶片 載體上設有銀層,以代替金層。晶片背面的銦層以加設金 層爲佳,比銀層薄。 在較佳具體例中,爲了接觸具有引線框的晶片背側, 其層次是在晶片背側分別:首先爲薄鈦層,再薄金層,最 後是厚絪層。較佳層厚度約100 nm鈦,約1〇〇 nm金, 約4μηι絪。引線框在按照本發明方法結合晶片之側,覆 —10 — 本紙張尺戾这Α中园Κ家標彳(dS ) ( 210X 297/^® ) ' ‘ ---1--------^------1Τ·------^ (銪先間讀背而之注意事項再>0?本頁) 411592 A7 B7 五 '發明説明(11 ) 有厚金層,約爲朗層厚度之半。引線框以合金42構成爲 佳。金層厚度約2μπι爲宜。 在進一步較佳配置中,爲接觸設有引線框的晶片背 側,在晶片背側分開層次是先薄鈦層和/或鉻層,再厚絪 層,最後是薄金層。較佳層厚約100 nm鈦和/或鉻,約 100 nm金和約4 μπι銦。引線框在按照本發明方法要結合 晶片之側面,覆以厚金層和/或厚銀層,約爲铟層厚度之 半。引線框以合金42構成爲佳較佳金層厚度約2 μπι。 在又一較佳配置中,爲接觸設有引線框的晶片背側, 在晶片背側分開層次是先薄鈦層,再厚絪層,最後厚金層。 較佳層厚約ί〇〇 nm鈦,約2 μπι金和約4 μπι絪。引線框 在按照本發明方法要結合晶片之側面,覆以薄銀層,約爲 絪層厚度之半。引線框以合金42構成爲佳。較佳銀層厚 度約2 μιη。 在又一成本低廉的較佳配置中,爲接觭設有引線框的 晶片背側,在晶片背側分開層次是先薄鈦層,再厚金層。 引線框在按照本發明方法要結合晶片之側面,覆以含銦糊 劑之厚層,尤其是網印糊劑,約爲金層厚度的加倍。較佳 層厚約100 nm鈦,約2 μπι金和約4 μιη絪糊劑。引線框 以合金42構成爲佳。 一 11 - ί、紙張尺度读州中囚阀家標埤((’NS > Λ4规格(2】ΟΧ297公釐) ---^----r----择-------1T------4 (讀先閱讀背面之注意事項再本頁)

Claims (1)

  1. 411592 89年6月16日修正 穴、申請專利乾圍 1. 一種半導體構件之等溫結合製法,該構件包括第一 組件,其接觸側(1.1)的外表面由可熔金靥形成,和置於其 上之第二組件,其接觸側(2.1)外表面由可熔金屬形成,構 件在預定溫度和壓力過程中加溫,直到表面間等溫凝固反 應爲止,其特徵爲,二組件(1,2)彼此並列接觸面(1.1,2.1) 至少在比反應時間期限(tl)爲短的一部份結合時間期限(t2) 內,利用振動能(P0以動態壓力實施,其中組件(1,2)至少 其一在縱向和/或橫向激起振動者。 如申請專利範圍第1項之製法,其中組件實施振動 能的時間,較結合時間期限(t2)爲短者。 3. 如申請專利範圍第1或2項之製法,其中振動是藉 超音波能產生者。 4. 如申請專利範圍第1或2項之製法,其中振動是藉 頻率低於超音波範圍的摩擦擺動產生者。 5. 如申請專利範圍第1項之製法,其中組件(1,2)在結 合時間期限(t2)內,另以靜壓力(F1)彼此壓合者。 6-如申請專利範圔第1項之製法,其中超音波能(P1) 和壓力(F1)同時作用者。 如申請專利範圍第1項之製法,其中使用振動能(P1) 負載介於0.3 W/mm2和3 W/mm2間者。 8-如申請專利範圍第I項之製法,其中使用壓力(F1) 介於 0.2 N/ mm2 和 1.5 N/ mm2 間者。 9·如申請專利範圍第1項之製法,其中使用壓力(F1) 至少1.5 N/ mm2者。 -12- 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) ^讀^ΤΑ-'·/ ::ίi*..-§'Ft-4ft「-<r n ί-十 -Λ. 經濟部智慧財產局員工消費合作社印製, 411592 89年6月16日修正 穴、申請專利乾圍 1. 一種半導體構件之等溫結合製法,該構件包括第一 組件,其接觸側(1.1)的外表面由可熔金靥形成,和置於其 上之第二組件,其接觸側(2.1)外表面由可熔金屬形成,構 件在預定溫度和壓力過程中加溫,直到表面間等溫凝固反 應爲止,其特徵爲,二組件(1,2)彼此並列接觸面(1.1,2.1) 至少在比反應時間期限(tl)爲短的一部份結合時間期限(t2) 內,利用振動能(P0以動態壓力實施,其中組件(1,2)至少 其一在縱向和/或橫向激起振動者。 如申請專利範圍第1項之製法,其中組件實施振動 能的時間,較結合時間期限(t2)爲短者。 3. 如申請專利範圍第1或2項之製法,其中振動是藉 超音波能產生者。 4. 如申請專利範圍第1或2項之製法,其中振動是藉 頻率低於超音波範圍的摩擦擺動產生者。 5. 如申請專利範圍第1項之製法,其中組件(1,2)在結 合時間期限(t2)內,另以靜壓力(F1)彼此壓合者。 6-如申請專利範圔第1項之製法,其中超音波能(P1) 和壓力(F1)同時作用者。 如申請專利範圍第1項之製法,其中使用振動能(P1) 負載介於0.3 W/mm2和3 W/mm2間者。 8-如申請專利範圍第I項之製法,其中使用壓力(F1) 介於 0.2 N/ mm2 和 1.5 N/ mm2 間者。 9·如申請專利範圍第1項之製法,其中使用壓力(F1) 至少1.5 N/ mm2者。 -12- 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) ^讀^ΤΑ-'·/ ::ίi*..-§'Ft-4ft「-<r n ί-十 -Λ. 經濟部智慧財產局員工消費合作社印製, 411592 Λ8 BS C8 D8 六、申請專利範圍 10.如申請專利範圍第1項之製法,其中反應溫度(τι) 愈高,振動時間期限〇2)愈短者。 (請先聞讀背面之注意事項再填寫本頁) 11‘如申請專利範圍第1項之製法,其中反應時間期 限在1 0秒至3分鐘之問者。 12·如申請專利範圍第1項之製法,其中組件(1,2)實 施振動能(Ρ1)在50 ms和600 ms之間者。 13.如申請專利範圍第i項之製法,其中組件(12)實 施振動能(P1)頂多爲結合時間期限的70¾者。 I4·如申請專利範圍第1項之製法,其中組件(1,2)在 結合時間期限開始時實施振動能者。 15. 如申請専利範圍第1項之製法,其中組件(U)外 表面係由熔點不同的金屬構成者。 16. 如申請專利範圍第1項之製法,其中組件(ι,2)外 表面係由熔點相同的金屬構成者。 17. 如申請專利範圍第1項之製法,其中反應溫度(T1) 低於高熔點成份之熔點者。 18. 如申請專利範圍第1項之製法,其中反應溫度(T1) 介於150-C和400°C之間者。 經濟部中央標準局員工消費合作社印策 19. 如申請專利範圍第1項之製法,其中製法是在惰 性氣體氛圍內,於至少較室溫爲高的溫度進行者。 20. 如申請專利範圍第1項之製法*其中高、低熔點 金屬成份(I.2,2.2)的選用厚度比例,使各成份(1.2,2.2)參 予反應的原子數,大約在反應中所形成標的金屬間相綜合 比例範圍內者。 -1 3 - 本紙張尺度適用中國國家標率(CNS)A4規格(210X297公釐) Λ8 BS C8 D8 411592 夂、申請專利範圍 21. 如申請專利範圍第20項之製法,其中厚度比例使 髙熔點成份(2.2)過贵存在者。 22. 如申請專利範圍第1項之製法,其中第一金屬層 (1-2,1. 3,1.4)至少爲含金和絪之層次者。 23. 如申請專利範圍第丨項之製法,其中第二金屬層 (2· 1,2.2)至少含金層者。 24. 如申請專利範圍第丨項之製法,其中在二組件(12) 接觸處,使銦層(I.2)與金層(2.2)接觸者。 25. 如申請專利範圍第丨項之製法,其中在二組件(1,2) 接觸處,使銦層(1.2)與铟層接觸者。 26. 如申請專利範圍第1項之製法,其中朗層(1.2)厚 度介於3和7 μπι間者。 27. 如申請專利範圍第丨項之製法,其中銦層在薄金 屬(I.3)上成長者。 28. 如申請專利範圍第1項之製法,其中金屬(2.2)厚 度僅及銦層(1.2)厚度之半者。 29. 如申請專利範圍第1項之製法,其中第一組件(1) 由微電子晶片構成者。 30. 如申請專利範圍第1項之製法,其中第二組件(2) 由矽體構成者。 31. 如申請專利範圍第1項之製法,其中第二組件(2) 由髙傳熱性陶瓷體構成者。 32. 如申請專利範圍第1舉之製法,其中第二組件(2) 由金屬體構成者。 -14- 本纸ί長尺度適用中國国家榡準(CNS Μ4規格(21 ο X 297公釐} .,4-- (請先聞讀背面之注意事項再填寫本頁) *1Τ 經濟部中央標準局男工消費合作社印裝 B8 _4115.92 S__________ 六、申請專利範圍 33. —種半導體構件,由第一組件和第二組件構成,尤 指微電子晶片和引線框,其特徴爲,構件具有熔點在400 °C以上的等溫凝固化合物層(3 ),第一組件(1 )和第二組件(2) 超此即彼此牢固結合者。 34. 如申請專利範圍第33項之半導體構件,其中化合 物層(3)實質上含有Auln和/或Auln2之合金,或其混合 物者。 35. 如申請專利範圍第33或34項之半導體構件,其中 構件含有擴散阻體層(1.4,2.3),介於組件(I,2)之一或二者 與化合物層(3)之間者。 3 6.如申請專利範圍第35項之半導體構件,其中擴散 _阻體層含有欽、鎳、路者。 3 7.如申請專利範圍第33項之半導髖構件,其中擴散 阻體層含有鈦和/或鎳和/或鉻,或鈦、鎳和/或鉻之組 合物者。 (請先閱讀背而:':::?意#.-§*4填"'"頁, 經濟部智葸財產局具工消費合作社印製 -15 — 本纸張尺度適用中囷國家標隼(CNS )八4規格(210χ 297公董)
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