TW373368B - Separate set/reset paths for time critical signals - Google Patents

Separate set/reset paths for time critical signals

Info

Publication number
TW373368B
TW373368B TW086110687A TW86110687A TW373368B TW 373368 B TW373368 B TW 373368B TW 086110687 A TW086110687 A TW 086110687A TW 86110687 A TW86110687 A TW 86110687A TW 373368 B TW373368 B TW 373368B
Authority
TW
Taiwan
Prior art keywords
transition
digital signal
separate set
time critical
edge
Prior art date
Application number
TW086110687A
Other languages
English (en)
Inventor
Robert J Proebsting
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Application granted granted Critical
Publication of TW373368B publication Critical patent/TW373368B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
TW086110687A 1996-07-29 1997-07-26 Separate set/reset paths for time critical signals TW373368B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2329496P 1996-07-29 1996-07-29
US08/885,145 US5926050A (en) 1996-07-29 1997-06-30 Separate set/reset paths for time critical signals

Publications (1)

Publication Number Publication Date
TW373368B true TW373368B (en) 1999-11-01

Family

ID=26696943

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086110687A TW373368B (en) 1996-07-29 1997-07-26 Separate set/reset paths for time critical signals

Country Status (6)

Country Link
US (1) US5926050A (zh)
EP (1) EP0822663B1 (zh)
KR (1) KR100487097B1 (zh)
CN (1) CN1134107C (zh)
DE (1) DE69733047T2 (zh)
TW (1) TW373368B (zh)

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US6154045A (en) * 1998-12-22 2000-11-28 Intel Corporation Method and apparatus for reducing signal transmission delay using skewed gates
US6577152B1 (en) * 1999-05-28 2003-06-10 International Business Machines Corporation Noise suppression circuit for suppressing above-ground noises
US6552589B1 (en) * 1999-10-21 2003-04-22 International Business Machines Corporation Method and apparatus for process independent clock signal distribution
US6339347B1 (en) 2000-03-30 2002-01-15 Intel Corporation Method and apparatus for ratioed logic structure that uses zero or negative threshold voltage
US6668357B2 (en) * 2001-06-29 2003-12-23 Fujitsu Limited Cold clock power reduction
US6630851B2 (en) * 2001-06-29 2003-10-07 Fujitsu Limited Low latency clock distribution
KR100422947B1 (ko) * 2001-11-22 2004-03-16 주식회사 하이닉스반도체 버스트 리드 데이터의 출력방법 및 출력장치
WO2003067273A1 (fr) * 2002-02-06 2003-08-14 Fujitsu Limited Procede de diagnostic de tolerance de gigue, et dispositif correspondant
US7053680B2 (en) * 2002-06-12 2006-05-30 Fujitsu Limited Complement reset buffer
US6577176B1 (en) * 2002-06-12 2003-06-10 Fujitsu Limited Complement reset latch
WO2004054106A1 (ja) * 2002-12-09 2004-06-24 Fujitsu Limited 高速伝送回路
JP4683833B2 (ja) 2003-10-31 2011-05-18 株式会社半導体エネルギー研究所 機能回路及びその設計方法
US7635992B1 (en) 2004-06-08 2009-12-22 Robert Paul Masleid Configurable tapered delay chain with multiple sizes of delay elements
US7304503B2 (en) * 2004-06-08 2007-12-04 Transmeta Corporation Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability
US7656212B1 (en) 2004-06-08 2010-02-02 Robert Paul Masleid Configurable delay chain with switching control for tail delay elements
US7142018B2 (en) 2004-06-08 2006-11-28 Transmeta Corporation Circuits and methods for detecting and assisting wire transitions
US7498846B1 (en) 2004-06-08 2009-03-03 Transmeta Corporation Power efficient multiplexer
US7405597B1 (en) 2005-06-30 2008-07-29 Transmeta Corporation Advanced repeater with duty cycle adjustment
US7173455B2 (en) 2004-06-08 2007-02-06 Transmeta Corporation Repeater circuit having different operating and reset voltage ranges, and methods thereof
US7336103B1 (en) * 2004-06-08 2008-02-26 Transmeta Corporation Stacked inverter delay chain
US7071747B1 (en) * 2004-06-15 2006-07-04 Transmeta Corporation Inverting zipper repeater circuit
DE102004054546B4 (de) * 2004-11-11 2011-06-22 Qimonda AG, 81739 Treiberschaltung
US7199616B2 (en) * 2004-11-29 2007-04-03 Exar Corporation Method and apparatus to generate break before make signals for high speed TTL driver
US7592842B2 (en) * 2004-12-23 2009-09-22 Robert Paul Masleid Configurable delay chain with stacked inverter delay elements
US7710153B1 (en) 2006-06-30 2010-05-04 Masleid Robert P Cross point switch
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TWI353114B (en) * 2008-09-22 2011-11-21 Inventec Corp Clock pin setting circuit and clock driven circuit
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Also Published As

Publication number Publication date
CN1187071A (zh) 1998-07-08
KR980011424A (ko) 1998-04-30
US5926050A (en) 1999-07-20
EP0822663A2 (en) 1998-02-04
DE69733047D1 (de) 2005-05-25
EP0822663B1 (en) 2005-04-20
EP0822663A3 (en) 1999-04-14
CN1134107C (zh) 2004-01-07
KR100487097B1 (ko) 2005-08-25
DE69733047T2 (de) 2006-03-02

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees