JPS6423318A - Detecting system for clock phase difference - Google Patents

Abstract

PURPOSE:To realize the automatic detection for presence or absence of a phase difference between two clock signals by combining two FF circuits, two delay circuits and a gate circuit with each other. CONSTITUTION:The clock signals 101 and 102 are supplied to the clock input terminals of FF 11 and 12 respectively from different units. A gate 21 delays the signal 102 by a degree larger than the input data holding time of the FF 11 and supplies this delayed signal to the data input terminal of the FF 11. In the same way, a gate 22 delays the signal 101 by a degree larger than the input data holding time of the FF 12. The data signals of both FF 11 and 12 undergo the OR arithmetic through a gate 30. Then the presence or absence of a phase difference is dynamically detected between both signals 101 and 102 in accordance with '1' or '0' of a detection signal 301, i.e., the output of the gate 30.