JPS5572264A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5572264A
JPS5572264A JP14639878A JP14639878A JPS5572264A JP S5572264 A JPS5572264 A JP S5572264A JP 14639878 A JP14639878 A JP 14639878A JP 14639878 A JP14639878 A JP 14639878A JP S5572264 A JPS5572264 A JP S5572264A
Authority
JP
Japan
Prior art keywords
timing
logic units
distribution circuits
output
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14639878A
Other languages
Japanese (ja)
Other versions
JPS602699B2 (en
Inventor
Tadashi Okada
Masao Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53146398A priority Critical patent/JPS602699B2/en
Publication of JPS5572264A publication Critical patent/JPS5572264A/en
Publication of JPS602699B2 publication Critical patent/JPS602699B2/en
Expired legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To remove an error output to OFF, generated owing to common timing T between FFs, by delaying signal T to each FF when the output of merging circuit supplied with the content of IFF is checked by OFF. CONSTITUTION:Timing generating circuit 11 generates several timing signals 14- 14' differing in phase, which are supplied to timing distribution circuits 12-12' corresponding to logic units 13-13', and consequently timing distribution circuits 12-12' amplify timing signals of respective phase and then supplies them to logic units 13-13'. Timing distribution circuits 12-12' are provided with several timing supply-suppression control methods, with can control independently several timing signals distributed into logic units 13-13', e.g. those supplied to input FF and output FF.
JP53146398A 1978-11-27 1978-11-27 information processing equipment Expired JPS602699B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53146398A JPS602699B2 (en) 1978-11-27 1978-11-27 information processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53146398A JPS602699B2 (en) 1978-11-27 1978-11-27 information processing equipment

Publications (2)

Publication Number Publication Date
JPS5572264A true JPS5572264A (en) 1980-05-30
JPS602699B2 JPS602699B2 (en) 1985-01-23

Family

ID=15406793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53146398A Expired JPS602699B2 (en) 1978-11-27 1978-11-27 information processing equipment

Country Status (1)

Country Link
JP (1) JPS602699B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH034334A (en) * 1989-06-01 1991-01-10 Nec Corp Clock advance control system
JPH03116210A (en) * 1990-08-31 1991-05-17 Hitachi Ltd Data processing system
JPH0457123A (en) * 1990-06-26 1992-02-24 Fujitsu Ltd Scan control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH034334A (en) * 1989-06-01 1991-01-10 Nec Corp Clock advance control system
JPH0457123A (en) * 1990-06-26 1992-02-24 Fujitsu Ltd Scan control system
JPH03116210A (en) * 1990-08-31 1991-05-17 Hitachi Ltd Data processing system
JPH0512728B2 (en) * 1990-08-31 1993-02-18 Hitachi Ltd

Also Published As

Publication number Publication date
JPS602699B2 (en) 1985-01-23

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