JPS5671125A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS5671125A
JPS5671125A JP14804879A JP14804879A JPS5671125A JP S5671125 A JPS5671125 A JP S5671125A JP 14804879 A JP14804879 A JP 14804879A JP 14804879 A JP14804879 A JP 14804879A JP S5671125 A JPS5671125 A JP S5671125A
Authority
JP
Japan
Prior art keywords
data
output
circuit
supplied
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14804879A
Other languages
Japanese (ja)
Inventor
Daisaku Ide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14804879A priority Critical patent/JPS5671125A/en
Publication of JPS5671125A publication Critical patent/JPS5671125A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to detect troubles with a simple circuit, by providing a data output circuit and a parity output circuit, which outputs a parity bit according to the data output, so that they may operate independently of each other.
CONSTITUTION: Data processing circuit 2 outputs data output 12 according to input data 11 supplied from the two-way data bus. Data output 12 is supplied to data bit output circuit 4 and parity generating circuit 5, and parity bit 13 is supplied to parity bit output circuit 6. Output circuits 4 and 6 are controlled independently of each other by logical outputs 16 and 17 of logical operation circuits 7 and 8 to which control signal 15 and output indication control signals 18 and 19 are input, and respective outputs 10 and 14 are supplied to the two-way bus.
COPYRIGHT: (C)1981,JPO&Japio
JP14804879A 1979-11-15 1979-11-15 Data processing device Pending JPS5671125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14804879A JPS5671125A (en) 1979-11-15 1979-11-15 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14804879A JPS5671125A (en) 1979-11-15 1979-11-15 Data processing device

Publications (1)

Publication Number Publication Date
JPS5671125A true JPS5671125A (en) 1981-06-13

Family

ID=15443969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14804879A Pending JPS5671125A (en) 1979-11-15 1979-11-15 Data processing device

Country Status (1)

Country Link
JP (1) JPS5671125A (en)

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