SE8402897L - Buffertkrets - Google Patents

Buffertkrets

Info

Publication number
SE8402897L
SE8402897L SE8402897A SE8402897A SE8402897L SE 8402897 L SE8402897 L SE 8402897L SE 8402897 A SE8402897 A SE 8402897A SE 8402897 A SE8402897 A SE 8402897A SE 8402897 L SE8402897 L SE 8402897L
Authority
SE
Sweden
Prior art keywords
buffer
signal
low
propagation delay
transition
Prior art date
Application number
SE8402897A
Other languages
Unknown language ( )
English (en)
Other versions
SE8402897D0 (sv
SE453786B (sv
Inventor
S P Saneski
Original Assignee
American Telephone & Telegraph
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone & Telegraph filed Critical American Telephone & Telegraph
Publication of SE8402897D0 publication Critical patent/SE8402897D0/sv
Publication of SE8402897L publication Critical patent/SE8402897L/sv
Publication of SE453786B publication Critical patent/SE453786B/sv

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
  • Dc Digital Transmission (AREA)
  • Manipulation Of Pulses (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
SE8402897A 1983-06-02 1984-05-29 Buffertkrets SE453786B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/500,419 US4575646A (en) 1983-06-02 1983-06-02 High-speed buffer arrangement with no delay distortion

Publications (3)

Publication Number Publication Date
SE8402897D0 SE8402897D0 (sv) 1984-05-29
SE8402897L true SE8402897L (sv) 1984-12-03
SE453786B SE453786B (sv) 1988-02-29

Family

ID=23989338

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8402897A SE453786B (sv) 1983-06-02 1984-05-29 Buffertkrets

Country Status (9)

Country Link
US (1) US4575646A (sv)
JP (1) JPS605627A (sv)
CA (1) CA1215137A (sv)
DE (1) DE3420239A1 (sv)
FR (1) FR2547135B1 (sv)
GB (1) GB2141600B (sv)
IT (1) IT1176241B (sv)
NL (1) NL8401768A (sv)
SE (1) SE453786B (sv)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4782253A (en) * 1984-02-15 1988-11-01 American Telephone & Telegraph Company, At&T Bell Laboratories High speed MOS circuits
US4786824A (en) * 1984-05-24 1988-11-22 Kabushiki Kaisha Toshiba Input signal level detecting circuit
JPS61218143A (ja) * 1985-03-25 1986-09-27 Hitachi Ltd 半導体集積回路装置
JPS6235716A (ja) * 1985-08-09 1987-02-16 Hitachi Ltd 半導体集積回路装置
KR900001817B1 (ko) * 1987-08-01 1990-03-24 삼성전자 주식회사 저항 수단을 이용한 씨 모스 티티엘 인푸트 버퍼
CA1331214C (en) * 1989-01-05 1994-08-02 Kun-Ming Lee Interfacing control circuit with active circuit charge or discharge
US4940908A (en) * 1989-04-27 1990-07-10 Advanced Micro Devices, Inc. Method and apparatus for reducing critical speed path delays
FR2791370B1 (fr) 1999-03-22 2001-05-25 Sogreah Bloc de carapace a surface rugueuse
NL2003428C2 (nl) * 2009-09-02 2011-03-03 Cremer Speciaalmachines B V Vulinrichting.

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1451732A (en) * 1973-03-19 1976-10-06 Motorola Inc Signal shaping circuit
US3925689A (en) * 1974-09-13 1975-12-09 Gen Instrument Corp High speed data buffer and amplifier
JPS5516539A (en) * 1978-07-20 1980-02-05 Nec Corp Level shifter circuit
JPS5522238A (en) * 1978-07-31 1980-02-16 Fujitsu Ltd Decoder circuit
US4318015A (en) * 1979-06-29 1982-03-02 Rca Corporation Level shift circuit
US4314166A (en) * 1980-02-22 1982-02-02 Rca Corporation Fast level shift circuits
DE3072018D1 (en) * 1980-11-28 1987-10-01 Ibm System for the distribution of digital signals
JPS58184817A (ja) * 1982-02-26 1983-10-28 Yokogawa Hewlett Packard Ltd 遅延回路

Also Published As

Publication number Publication date
FR2547135A1 (fr) 1984-12-07
JPS605627A (ja) 1985-01-12
NL8401768A (nl) 1985-01-02
IT8421227A0 (it) 1984-06-01
CA1215137A (en) 1986-12-09
US4575646A (en) 1986-03-11
GB2141600A (en) 1984-12-19
FR2547135B1 (fr) 1988-02-05
SE8402897D0 (sv) 1984-05-29
GB2141600B (en) 1986-09-17
IT1176241B (it) 1987-08-18
DE3420239C2 (sv) 1992-12-10
IT8421227A1 (it) 1985-12-01
GB8413786D0 (en) 1984-07-04
SE453786B (sv) 1988-02-29
DE3420239A1 (de) 1984-12-06

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ALKALAY et al. Performance degradation of a 7400 TTL NAND gate due to sinusoidal interference[Final Technical Report, Jun. 1979- Jun. 1980]

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