DE60142969D1 - Schaltung zur erzeugung eines invertierten digitalen signals mit minimaler zeitverzögerung zwischen - Google Patents
Schaltung zur erzeugung eines invertierten digitalen signals mit minimaler zeitverzögerung zwischenInfo
- Publication number
- DE60142969D1 DE60142969D1 DE60142969T DE60142969T DE60142969D1 DE 60142969 D1 DE60142969 D1 DE 60142969D1 DE 60142969 T DE60142969 T DE 60142969T DE 60142969 T DE60142969 T DE 60142969T DE 60142969 D1 DE60142969 D1 DE 60142969D1
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- signal
- digital signal
- generating
- pass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00202450 | 2000-07-10 | ||
PCT/EP2001/007404 WO2002005427A1 (en) | 2000-07-10 | 2001-06-28 | Circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60142969D1 true DE60142969D1 (de) | 2010-10-14 |
Family
ID=8171780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60142969T Expired - Lifetime DE60142969D1 (de) | 2000-07-10 | 2001-06-28 | Schaltung zur erzeugung eines invertierten digitalen signals mit minimaler zeitverzögerung zwischen |
Country Status (7)
Country | Link |
---|---|
US (1) | US6480048B2 (de) |
EP (1) | EP1303914B8 (de) |
JP (1) | JP4836024B2 (de) |
KR (1) | KR20020036850A (de) |
AT (1) | ATE480046T1 (de) |
DE (1) | DE60142969D1 (de) |
WO (1) | WO2002005427A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6920187B2 (en) * | 2002-10-02 | 2005-07-19 | Micron Technology, Inc. | Constant delay zero standby differential logic receiver and method |
US20130152081A1 (en) | 2011-12-13 | 2013-06-13 | International Business Machines Corporation | Selectable event reporting for highly virtualized partitioned systems |
EP2608411B1 (de) | 2011-12-22 | 2020-03-11 | Nxp B.V. | Schaltkreis |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5834982B2 (ja) * | 1977-05-11 | 1983-07-30 | 日本電気株式会社 | クロツクドライバ−回路 |
JPS5997222A (ja) * | 1982-11-26 | 1984-06-05 | Matsushita Electric Ind Co Ltd | クロツクパルス発生回路 |
JPS6439817A (en) * | 1987-08-05 | 1989-02-10 | Toshiba Corp | Complementary output circuit |
JPH01109816A (ja) * | 1987-10-22 | 1989-04-26 | Mitsubishi Electric Corp | 相補型半導体集積回路装置 |
JPH0356223U (de) * | 1989-10-05 | 1991-05-30 | ||
US5341048A (en) * | 1992-11-25 | 1994-08-23 | Altera Corporation | Clock invert and select circuit |
DE4315298C1 (de) * | 1993-05-07 | 1994-08-18 | Siemens Ag | Schaltungsanordnung zur Erzeugung zweier komplementärer Signale |
US5541532A (en) * | 1995-08-17 | 1996-07-30 | Analog Devices, Inc. | All MOS single-ended to differential level converter |
KR100202193B1 (ko) * | 1995-12-30 | 1999-06-15 | 문정환 | 상보 클럭 발생 방법 및 클럭 발생기 |
US5896047A (en) * | 1997-02-05 | 1999-04-20 | Xilinx, Inc. | Balanced truth-and-complement circuit |
DE19821458C1 (de) * | 1998-05-13 | 1999-11-18 | Siemens Ag | Schaltungsanordnung zur Erzeugung komplementärer Signale |
-
2001
- 2001-06-28 WO PCT/EP2001/007404 patent/WO2002005427A1/en active Application Filing
- 2001-06-28 AT AT01960412T patent/ATE480046T1/de not_active IP Right Cessation
- 2001-06-28 KR KR1020027003065A patent/KR20020036850A/ko not_active Application Discontinuation
- 2001-06-28 JP JP2002509173A patent/JP4836024B2/ja not_active Expired - Fee Related
- 2001-06-28 DE DE60142969T patent/DE60142969D1/de not_active Expired - Lifetime
- 2001-06-28 EP EP01960412A patent/EP1303914B8/de not_active Expired - Lifetime
- 2001-07-10 US US09/902,218 patent/US6480048B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US20020012413A1 (en) | 2002-01-31 |
US6480048B2 (en) | 2002-11-12 |
KR20020036850A (ko) | 2002-05-16 |
WO2002005427A1 (en) | 2002-01-17 |
EP1303914B1 (de) | 2010-09-01 |
EP1303914B8 (de) | 2010-11-10 |
JP4836024B2 (ja) | 2011-12-14 |
EP1303914A1 (de) | 2003-04-23 |
JP2004503166A (ja) | 2004-01-29 |
ATE480046T1 (de) | 2010-09-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8327 | Change in the person/name/address of the patent owner |
Owner name: ST-ERICSSON SA, GENEVE PLAN-LES-QUATES, CH |