JPS6439817A - Complementary output circuit - Google Patents
Complementary output circuitInfo
- Publication number
- JPS6439817A JPS6439817A JP62194526A JP19452687A JPS6439817A JP S6439817 A JPS6439817 A JP S6439817A JP 62194526 A JP62194526 A JP 62194526A JP 19452687 A JP19452687 A JP 19452687A JP S6439817 A JPS6439817 A JP S6439817A
- Authority
- JP
- Japan
- Prior art keywords
- output
- inverter circuit
- input signal
- output part
- complementary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
Abstract
PURPOSE:To reduce the skew between complementary outputs by a low power consumption, by bringing each output part to a conduction control by an output of a corresponding fourth CMOS inverter circuit or a fifth CMOS inverter circuit, and obtaining a complementary output against an input signal. CONSTITUTION:A line for generating an output signal, the inverse of phi from an input signal CK is constituted of inverter circuits 21, 23 and an output part 25. That is, the inverter circuit 23 consists of a P channel MOS type transistor (PMOS) P5 and an N channel MOS type transistor (NMOS) N5, inverted by receiving an output of the inverter circuit 21, and provides an output to an output part 25. On the other hand, a line for generating an output signal phifrom the input signal CK is constituted of inverter circuits 29, 31 and 33, NPN type bipolar transistors Q3, Q4 which have been brought to a Darlington connection, and an output part 35, and this inverter circuit 33 consists of a PMOSP12 and an NMOSN12, inverted by receiving the input signal CK, and provides an output to an output part 35. In such a way, the skew between complementary outputs is reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62194526A JPS6439817A (en) | 1987-08-05 | 1987-08-05 | Complementary output circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62194526A JPS6439817A (en) | 1987-08-05 | 1987-08-05 | Complementary output circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6439817A true JPS6439817A (en) | 1989-02-10 |
Family
ID=16326000
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62194526A Pending JPS6439817A (en) | 1987-08-05 | 1987-08-05 | Complementary output circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6439817A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0583881A1 (en) * | 1992-08-07 | 1994-02-23 | Lsi Logic Corporation | CMOS differential driver circuit for high offset ground |
EP0621691A2 (en) * | 1993-04-19 | 1994-10-26 | Koninklijke Philips Electronics N.V. | Complementary-signal BiCMOS line driver with low skew |
EP0533354B1 (en) * | 1991-09-18 | 1999-02-03 | STMicroelectronics, Inc. | Driver circuit with FET and bipolar transistors |
JP4836024B2 (en) * | 2000-07-10 | 2011-12-14 | エスティー‐エリクソン、ソシエテ、アノニム | A circuit for generating an inverse signal of a digital signal by minimizing a delay difference between the digital signal and the inverse signal. |
-
1987
- 1987-08-05 JP JP62194526A patent/JPS6439817A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0533354B1 (en) * | 1991-09-18 | 1999-02-03 | STMicroelectronics, Inc. | Driver circuit with FET and bipolar transistors |
EP0583881A1 (en) * | 1992-08-07 | 1994-02-23 | Lsi Logic Corporation | CMOS differential driver circuit for high offset ground |
EP0621691A2 (en) * | 1993-04-19 | 1994-10-26 | Koninklijke Philips Electronics N.V. | Complementary-signal BiCMOS line driver with low skew |
EP0621691A3 (en) * | 1993-04-19 | 1995-03-22 | Koninkl Philips Electronics Nv | Complementary-signal BiCMOS line driver with low skew. |
JP4836024B2 (en) * | 2000-07-10 | 2011-12-14 | エスティー‐エリクソン、ソシエテ、アノニム | A circuit for generating an inverse signal of a digital signal by minimizing a delay difference between the digital signal and the inverse signal. |
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