TW346654B - Fluorine barrier layer between conductor and insulator for degradation prevention - Google Patents

Fluorine barrier layer between conductor and insulator for degradation prevention

Info

Publication number
TW346654B
TW346654B TW086113993A TW86113993A TW346654B TW 346654 B TW346654 B TW 346654B TW 086113993 A TW086113993 A TW 086113993A TW 86113993 A TW86113993 A TW 86113993A TW 346654 B TW346654 B TW 346654B
Authority
TW
Taiwan
Prior art keywords
barrier layer
insulator
conductor
fluorine
degradation prevention
Prior art date
Application number
TW086113993A
Other languages
English (en)
Inventor
C Cooney Edward Iii
K Lee Hyun
L Mcdevitt Thomas
K Stamper Anthony
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW346654B publication Critical patent/TW346654B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/963—Removing process residues from vertical substrate surfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulating Bodies (AREA)
TW086113993A 1996-11-08 1997-09-25 Fluorine barrier layer between conductor and insulator for degradation prevention TW346654B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/744,846 US6310300B1 (en) 1996-11-08 1996-11-08 Fluorine-free barrier layer between conductor and insulator for degradation prevention

Publications (1)

Publication Number Publication Date
TW346654B true TW346654B (en) 1998-12-01

Family

ID=24994193

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086113993A TW346654B (en) 1996-11-08 1997-09-25 Fluorine barrier layer between conductor and insulator for degradation prevention

Country Status (7)

Country Link
US (4) US6310300B1 (zh)
JP (1) JP3245104B2 (zh)
KR (1) KR100332272B1 (zh)
CN (1) CN1106030C (zh)
MY (1) MY127478A (zh)
SG (1) SG65024A1 (zh)
TW (1) TW346654B (zh)

Families Citing this family (116)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5989998A (en) * 1996-08-29 1999-11-23 Matsushita Electric Industrial Co., Ltd. Method of forming interlayer insulating film
US6310300B1 (en) * 1996-11-08 2001-10-30 International Business Machines Corporation Fluorine-free barrier layer between conductor and insulator for degradation prevention
JP3019021B2 (ja) * 1997-03-31 2000-03-13 日本電気株式会社 半導体装置及びその製造方法
US6121159A (en) 1997-06-19 2000-09-19 Lsi Logic Corporation Polymeric dielectric layers having low dielectric constants and improved adhesion to metal lines
EP0911697A3 (en) * 1997-10-22 1999-09-15 Interuniversitair Microelektronica Centrum Vzw A fluorinated hard mask for micropatterning of polymers
US6054380A (en) * 1997-12-09 2000-04-25 Applied Materials, Inc. Method and apparatus for integrating low dielectric constant materials into a multilevel metallization and interconnect structure
US6277730B1 (en) * 1998-02-17 2001-08-21 Matsushita Electronics Corporation Method of fabricating interconnects utilizing fluorine doped insulators and barrier layers
JP3189781B2 (ja) * 1998-04-08 2001-07-16 日本電気株式会社 半導体装置の製造方法
JP3177968B2 (ja) * 1998-12-04 2001-06-18 日本電気株式会社 半導体装置及びその製造方法
US6153509A (en) * 1998-07-01 2000-11-28 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
US6373114B1 (en) * 1998-10-23 2002-04-16 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity
US6372301B1 (en) * 1998-12-22 2002-04-16 Applied Materials, Inc. Method of improving adhesion of diffusion layers on fluorinated silicon dioxide
KR100381961B1 (ko) 1999-04-26 2003-04-26 삼성전자주식회사 반도체 기판 상에 질화된 계면을 형성하는 방법
US6797601B2 (en) * 1999-06-11 2004-09-28 Micron Technology, Inc. Methods for forming wordlines, transistor gates, and conductive interconnects
US6730584B2 (en) * 1999-06-15 2004-05-04 Micron Technology, Inc. Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
US6727588B1 (en) * 1999-08-19 2004-04-27 Agere Systems Inc. Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
US6559076B1 (en) * 1999-08-19 2003-05-06 Micron Technology, Inc. Method of removing free halogen from a halogenated polymer insulating layer of a semiconductor device
JP4236778B2 (ja) * 1999-11-01 2009-03-11 株式会社ルネサステクノロジ 半導体装置
US20020076917A1 (en) * 1999-12-20 2002-06-20 Edward P Barth Dual damascene interconnect structure using low stress flourosilicate insulator with copper conductors
US6372291B1 (en) * 1999-12-23 2002-04-16 Applied Materials, Inc. In situ deposition and integration of silicon nitride in a high density plasma reactor
US6573030B1 (en) 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US6284657B1 (en) * 2000-02-25 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Non-metallic barrier formation for copper damascene type interconnects
AU2001245685A1 (en) * 2000-03-29 2001-10-08 Intel Corporation Method for modifying the surface of a fluorocarbon
JP2002194547A (ja) * 2000-06-08 2002-07-10 Applied Materials Inc アモルファスカーボン層の堆積方法
US6429129B1 (en) * 2000-06-16 2002-08-06 Chartered Semiconductor Manufacturing Ltd. Method of using silicon rich carbide as a barrier material for fluorinated materials
US6492731B1 (en) 2000-06-27 2002-12-10 Lsi Logic Corporation Composite low dielectric constant film for integrated circuit structure
JP3574383B2 (ja) 2000-07-31 2004-10-06 富士通株式会社 半導体装置及びその製造方法
US6489242B1 (en) 2000-09-13 2002-12-03 Lsi Logic Corporation Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures
US6537923B1 (en) 2000-10-31 2003-03-25 Lsi Logic Corporation Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
US6423630B1 (en) 2000-10-31 2002-07-23 Lsi Logic Corporation Process for forming low K dielectric material between metal lines
US6607967B1 (en) 2000-11-15 2003-08-19 Lsi Logic Corporation Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate
DE10059935A1 (de) * 2000-11-28 2002-06-06 Infineon Technologies Ag Dicht gepackte Halbleiterstruktur und Verfahren zum Herstellen einer solchen
DE10063469B4 (de) * 2000-12-19 2004-03-25 Micronas Gmbh Verfahren zur Herstellung eines elektronischen Chips und mit dem Verfahren hergestellter elektronischer Chip
US6649219B2 (en) 2001-02-23 2003-11-18 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
US6858195B2 (en) 2001-02-23 2005-02-22 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material
US6572925B2 (en) 2001-02-23 2003-06-03 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric material
US6576545B1 (en) * 2001-03-29 2003-06-10 Advanced Micro Devices, Inc. Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US6559048B1 (en) 2001-05-30 2003-05-06 Lsi Logic Corporation Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning
US6583026B1 (en) 2001-05-31 2003-06-24 Lsi Logic Corporation Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure
US6562700B1 (en) 2001-05-31 2003-05-13 Lsi Logic Corporation Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal
US6566171B1 (en) 2001-06-12 2003-05-20 Lsi Logic Corporation Fuse construction for integrated circuit structure having low dielectric constant dielectric material
US6930056B1 (en) * 2001-06-19 2005-08-16 Lsi Logic Corporation Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure
US6559033B1 (en) 2001-06-27 2003-05-06 Lsi Logic Corporation Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
US6627546B2 (en) * 2001-06-29 2003-09-30 Ashland Inc. Process for removing contaminant from a surface and composition useful therefor
US7085616B2 (en) * 2001-07-27 2006-08-01 Applied Materials, Inc. Atomic layer deposition apparatus
US6881664B2 (en) * 2001-08-28 2005-04-19 Lsi Logic Corporation Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
US6521520B1 (en) 2001-08-30 2003-02-18 Lsi Logic Corporation Semiconductor wafer arrangement and method of processing a semiconductor wafer
US6620745B2 (en) * 2001-10-19 2003-09-16 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming a blocking layer
US6613665B1 (en) 2001-10-26 2003-09-02 Lsi Logic Corporation Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface
US6528423B1 (en) * 2001-10-26 2003-03-04 Lsi Logic Corporation Process for forming composite of barrier layers of dielectric material to inhibit migration of copper from copper metal interconnect of integrated circuit structure into adjacent layer of low k dielectric material
KR20030039286A (ko) * 2001-11-12 2003-05-17 아남반도체 주식회사 반도체 소자 제조 방법
US7001823B1 (en) 2001-11-14 2006-02-21 Lsi Logic Corporation Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance
US6537896B1 (en) * 2001-12-04 2003-03-25 Lsi Logic Corporation Process for treating porous low k dielectric material in damascene structure to form a non-porous dielectric diffusion barrier on etched via and trench surfaces in the porous low k dielectric material
US6562735B1 (en) 2001-12-11 2003-05-13 Lsi Logic Corporation Control of reaction rate in formation of low k carbon-containing silicon oxide dielectric material using organosilane, unsubstituted silane, and hydrogen peroxide reactants
US6541397B1 (en) 2002-03-29 2003-04-01 Applied Materials, Inc. Removable amorphous carbon CMP stop
US6911378B2 (en) * 2003-06-24 2005-06-28 International Business Machines Corporation Stabilization of fluorine-containing dielectric materials in a metal insulator wiring structure
DE10339988B4 (de) * 2003-08-29 2008-06-12 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer antireflektierenden Schicht
US7129171B2 (en) * 2003-10-14 2006-10-31 Lam Research Corporation Selective oxygen-free etching process for barrier materials
KR100563487B1 (ko) * 2003-12-31 2006-03-27 동부아남반도체 주식회사 반도체 소자의 금속배선 형성방법
KR100529676B1 (ko) 2003-12-31 2005-11-17 동부아남반도체 주식회사 듀얼 다마신 패턴을 형성하는 방법
KR100552812B1 (ko) * 2003-12-31 2006-02-22 동부아남반도체 주식회사 반도체 소자의 구리 배선 형성 방법
JP4879159B2 (ja) * 2004-03-05 2012-02-22 アプライド マテリアルズ インコーポレイテッド アモルファス炭素膜堆積のためのｃｖｄプロセス
US7638440B2 (en) * 2004-03-12 2009-12-29 Applied Materials, Inc. Method of depositing an amorphous carbon film for etch hardmask application
US7079740B2 (en) * 2004-03-12 2006-07-18 Applied Materials, Inc. Use of amorphous carbon film as a hardmask in the fabrication of optical waveguides
US20050199585A1 (en) * 2004-03-12 2005-09-15 Applied Materials, Inc. Method of depositing an amorphous carbon film for metal etch hardmask application
KR20050114784A (ko) * 2004-06-01 2005-12-07 동부아남반도체 주식회사 반도체 소자의 구리배선 형성방법
DE102004031744A1 (de) * 2004-06-30 2006-07-27 Advanced Micro Devices, Inc., Sunnyvale Eine Technik zur Herstellung einer dielektrischen Zwischenschicht über einer Struktur mit eng beabstandeten Leitungen
US20060046465A1 (en) * 2004-08-27 2006-03-02 Dongbuanam Semiconductor Inc. Method for manufacturing a semiconductor device
KR100876532B1 (ko) * 2004-08-27 2008-12-31 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
KR100641506B1 (ko) * 2004-09-17 2006-11-01 동부일렉트로닉스 주식회사 반도체 소자 세정 방법
KR100552857B1 (ko) * 2004-10-25 2006-02-22 동부아남반도체 주식회사 반도체 소자의 콘택 형성 방법
US7579224B2 (en) * 2005-01-21 2009-08-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film semiconductor device
KR100731085B1 (ko) * 2005-09-28 2007-06-22 동부일렉트로닉스 주식회사 듀얼 다마신 공정을 이용한 구리 배선 형성 방법
GB0521582D0 (en) * 2005-10-22 2005-11-30 Depuy Int Ltd An implant for supporting a spinal column
GB0521585D0 (en) * 2005-10-22 2005-11-30 Depuy Int Ltd A spinal support rod
US8348952B2 (en) 2006-01-26 2013-01-08 Depuy International Ltd. System and method for cooling a spinal correction device comprising a shape memory material for corrective spinal surgery
US7851351B2 (en) 2006-03-31 2010-12-14 Tokyo Electron Limited Manufacturing method for semiconductor devices with enhanced adhesivity and barrier properties
JP5119606B2 (ja) * 2006-03-31 2013-01-16 東京エレクトロン株式会社 半導体装置及び半導体装置の製造方法
US20070286954A1 (en) * 2006-06-13 2007-12-13 Applied Materials, Inc. Methods for low temperature deposition of an amorphous carbon layer
US20080254233A1 (en) * 2007-04-10 2008-10-16 Kwangduk Douglas Lee Plasma-induced charge damage control for plasma enhanced chemical vapor deposition processes
US20090093128A1 (en) * 2007-10-08 2009-04-09 Martin Jay Seamons Methods for high temperature deposition of an amorphous carbon layer
GB0720762D0 (en) * 2007-10-24 2007-12-05 Depuy Spine Sorl Assembly for orthopaedic surgery
US7985513B2 (en) * 2008-03-18 2011-07-26 Advanced Micro Devices, Inc. Fluorine-passivated reticles for use in lithography and methods for fabricating the same
US20090269923A1 (en) * 2008-04-25 2009-10-29 Lee Sang M Adhesion and electromigration improvement between dielectric and conductive layers
US7830016B2 (en) * 2008-06-30 2010-11-09 Intel Corporation Seed layer for reduced resistance tungsten film
US8293634B2 (en) * 2008-08-07 2012-10-23 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices
US8551885B2 (en) * 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US8623733B2 (en) 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8709948B2 (en) * 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
US9255316B2 (en) 2010-07-19 2016-02-09 Ati Properties, Inc. Processing of α+β titanium alloys
US9653327B2 (en) 2011-05-12 2017-05-16 Applied Materials, Inc. Methods of removing a material layer from a substrate using water vapor treatment
JP6144003B2 (ja) * 2011-08-29 2017-06-07 富士通株式会社 配線構造及びその製造方法並びに電子装置及びその製造方法
TWI602283B (zh) 2012-03-27 2017-10-11 諾發系統有限公司 鎢特徵部塡充
CN102664193A (zh) * 2012-04-01 2012-09-12 京东方科技集团股份有限公司 导电结构及制造方法、薄膜晶体管、阵列基板和显示装置
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9034769B2 (en) 2012-12-12 2015-05-19 Micron Technology, Inc. Methods of selectively removing a substrate material
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
CN105448801A (zh) * 2014-05-28 2016-03-30 中芯国际集成电路制造(上海)有限公司 一种形成浅沟槽隔离的方法
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
CN111095488A (zh) 2017-08-14 2020-05-01 朗姆研究公司 三维竖直nand字线的金属填充过程
WO2019213604A1 (en) 2018-05-03 2019-11-07 Lam Research Corporation Method of depositing tungsten and other metals in 3d nand structures
JP2022513479A (ja) 2018-12-14 2022-02-08 ラム リサーチ コーポレーション ３ｄ ｎａｎｄ構造上の原子層堆積
US10847367B2 (en) 2018-12-28 2020-11-24 Micron Technology, Inc. Methods of forming tungsten structures
KR20210141762A (ko) 2019-04-11 2021-11-23 램 리써치 코포레이션 고 단차 커버리지 (step coverage) 텅스텐 증착
JP2022544931A (ja) 2019-08-12 2022-10-24 ラム リサーチ コーポレーション タングステン堆積
US11244903B2 (en) 2019-12-30 2022-02-08 Micron Technology, Inc. Tungsten structures and methods of forming the structures

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3620833A (en) * 1966-12-23 1971-11-16 Texas Instruments Inc Integrated circuit fabrication
US4300989A (en) 1979-10-03 1981-11-17 Bell Telephone Laboratories, Incorporated Fluorine enhanced plasma growth of native layers on silicon
US5181985A (en) * 1988-06-01 1993-01-26 Wacker-Chemitronic Gesellschaft Fur Elektronik-Grundstoffe Mbh Process for the wet-chemical surface treatment of semiconductor wafers
US5821175A (en) * 1988-07-08 1998-10-13 Cauldron Limited Partnership Removal of surface contaminants by irradiation using various methods to achieve desired inert gas flow over treated surface
JPH06103787B2 (ja) * 1988-07-26 1994-12-14 日本碍子株式会社 導電性膜付ガラスセラミック基板
EP0809283A3 (en) 1989-08-28 1998-02-25 Hitachi, Ltd. Method of treating wafers
JPH0456325A (ja) 1990-06-26 1992-02-24 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2814021B2 (ja) 1990-07-09 1998-10-22 三菱電機株式会社 半導体基板表面の処理方法
US5138432A (en) * 1990-08-30 1992-08-11 Cornell Research Foundation, Inc. Selective deposition of tungsten on TiSi2
US5378317A (en) * 1990-10-09 1995-01-03 Chlorine Engineers Corp., Ltd. Method for removing organic film
US5219791A (en) 1991-06-07 1993-06-15 Intel Corporation TEOS intermetal dielectric preclean for VIA formation
US5397748A (en) 1991-12-28 1995-03-14 Nec Corporation Method of producing semiconductor device with insulating film having at least silicon nitride film
US5423945A (en) 1992-09-08 1995-06-13 Applied Materials, Inc. Selectivity for etching an oxide over a nitride
JP2748768B2 (ja) * 1992-03-19 1998-05-13 株式会社日立製作所 薄膜多層配線基板およびその製造方法
US5753564A (en) 1992-11-24 1998-05-19 Sumitomo Metal Industries, Ltd. Method for forming a thin film of a silicon oxide on a silicon substrate, by BCR plasma
KR0131439B1 (ko) 1992-11-24 1998-04-14 나카무라 타메아키 반도체장치 및 그 제조방법
US5384281A (en) 1992-12-29 1995-01-24 International Business Machines Corporation Non-conformal and oxidizable etch stops for submicron features
JPH07202186A (ja) 1993-12-28 1995-08-04 Sony Corp 半導体装置の製造方法
US5451543A (en) 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
JP2845160B2 (ja) * 1995-03-23 1999-01-13 日本電気株式会社 半導体装置
US5644166A (en) * 1995-07-17 1997-07-01 Micron Technology, Inc. Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts
US5661334A (en) * 1996-01-16 1997-08-26 Micron Technology, Inc. Inter-metal dielectric structure which combines fluorine-doped glass and barrier layers
JP3323055B2 (ja) * 1996-04-03 2002-09-09 株式会社東芝 半導体装置およびその製造方法
US6310300B1 (en) * 1996-11-08 2001-10-30 International Business Machines Corporation Fluorine-free barrier layer between conductor and insulator for degradation prevention

Also Published As

Publication number Publication date
CN1106030C (zh) 2003-04-16
JP3245104B2 (ja) 2002-01-07
US6066577A (en) 2000-05-23
US6214730B1 (en) 2001-04-10
SG65024A1 (en) 1999-05-25
MY127478A (en) 2006-12-29
US5930655A (en) 1999-07-27
KR100332272B1 (ko) 2002-06-20
JPH10144793A (ja) 1998-05-29
CN1182956A (zh) 1998-05-27
KR19980041870A (ko) 1998-08-17
US6310300B1 (en) 2001-10-30

Similar Documents

Publication Publication Date Title
TW346654B (en) Fluorine barrier layer between conductor and insulator for degradation prevention
AU3572297A (en) A capacitor and methods of forming a capacitor
EP0664560A3 (en) Method of forming an insulating layer.
EP0666992A4 (en) IMPROVED METHOD FOR SUPPRESSING REVERBERATION.
EP0629549A3 (en) Lightning protection and improved electrical conductivity composite.
IL126614A0 (en) Composition barrier film and method for preventing contact dermatitis
AU7065396A (en) Electron generating apparatus, image forming apparatus, and method of manufacturing and adjusting the same
EP0641011A3 (en) Electron beam device.
EP0661718A3 (en) Method and device for erasing flash-EEPROM memories.
GB2294474B (en) Method for forming an aluminium or aluminium alloy composite material.
EP0617432A3 (en) Composite electrical insulator and method of making it.
EP0680075A4 (en) ELECTRODE FOR THE PRODUCTION OF PLASMA, ELECTRODE BURIAL ELEMENT, AND METHOD FOR MANUFACTURING THE ELECTRODE AND THE ELEMENT.
AU7265894A (en) Electrically insulating seal insert, corresponding seal and method for the manufacture of such inserts
EP0610036A3 (en) Spectrometry method and apparatus therefor.
HK1018709A1 (en) Method for preventing contamination by lead from metallic piping devices
AU3553599A (en) Method and apparatus for enhancing adhesion between barrier layer and metal layer formed by plating
AU661822B2 (en) Method for electric protection of metal object, grounding electrode for implementing the method and composition for grounding electrode
TW358986B (en) Metal layer patterns of a semiconductor device and a method for forming the same
AU5522494A (en) Method for forming tough, electrical insulating layer on surface of copper material
GR1002648B (el) Μεθοδος με την οποια επιτυγχανεται απομιμηση παντος τυπου σχεδιου επι μεταλλικων επιφανειων μετα του αναλογου μηχανολογικου εξοπλισμου.
ZA99517B (en) Apparatus and method for digital telephony.
EP0653782A3 (en) Process for reforming an insulating layer.
EP0607691A3 (en) Method for forming a layer.
AU8896198A (en) A method and an apparatus for manufacturing an electrical insulator
GB9920236D0 (en) System and method for digital telephones on h.323 networks

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent