CN102664193A - 导电结构及制造方法、薄膜晶体管、阵列基板和显示装置 - Google Patents
导电结构及制造方法、薄膜晶体管、阵列基板和显示装置 Download PDFInfo
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Abstract
本发明提供了一种导电结构及制造方法、薄膜晶体管、阵列基板和显示装置。其中所述导电结构包括:由铜或铜合金形成的铜层;用于阻挡所述铜层的铜离子向外扩散的阻挡层;用于阻挡外部离子扩散至所述铜层的防扩散层,所述防扩散层设置在所述铜层与所述阻挡层之间。本发明利用多层导电结构阻止外部离子扩散进入铜层以及铜层铜离子的向外扩散,从而减少离子扩散对铜金属层的电学性能和化学耐腐蚀性能的不良影响,同时,由于阻挡层与衬底基板或半导体层之间具有良好的粘附性,能够提高导电结构的粘合稳固程度;并且,该导电结构中的各个层都具有类似的刻蚀选择性,有利于对多层导电结构的刻蚀/图案化处理。
Description
技术领域
本发明涉及电子器件制造技术领域,具体涉及一种导电结构及其制造方法、薄膜晶体管、阵列基板和显示装置。
背景技术
薄膜晶体管阵列基板可以用于液晶显示器和有机发光显示器中。其中,液晶显示器通常包括薄膜晶体管阵列基板和彩色滤光膜基板,以及设置在两个基板之间的液晶层。当两个基板之间加入电场时,液晶分子排列发生改变,从而可以改变光线的透射比。有机发光显示器则通过使用有机场致发光材料来显示图像。有机发光显示器的像素通常包括向有机场致发光材料提供电流的驱动薄膜晶体管和控制驱动薄膜晶体管开启或关闭的开关薄膜晶体管。
随着显示器件尺寸的增大以及显示性能要求的提高,要求栅极线和数据线具有更低的电阻。目前主流的铝配线由于电阻系数较高,已经不能满足显示性能的要求。而铜的电阻系数比铝的电阻系数低的多,因此,使用铜作为栅极线和数据线将成为今后的主流选择。
然而,铜离子具有较强的渗透性,很容易扩散到非晶硅或硅层中,另外在对金属导电层进行刻蚀或在剥离光刻胶过程中产生的铜离子,也可能渗入到非晶硅层,从而影响非晶硅层(如薄膜晶体管)的性能。此外,硅离子和其他金属离子也容易扩散到铜导电结构内,从而使铜导电结构的电阻系数增大并降低其化学耐腐蚀性。
发明内容
有鉴于此,本发明实施例的目的之一是提供一种导电结构,能够阻止外部离子扩散进入铜层以及铜层铜离子的向外扩散,从而减少离子扩散带来的不良影响。
为解决上述技术问题,本发明实施例提供方案如下:
一种导电结构,包括:
由铜或铜合金形成的铜层;
用于阻挡所述铜层的铜离子向外扩散的阻挡层;
用于阻挡外部离子扩散至所述铜层的防扩散层,所述防扩散层设置在所述铜层与所述阻挡层之间。
优选地,上述导电结构中,所述阻挡层的材料为钼合金,所述防扩散层的材料为钼。。
优选地,上述导电结构中,所述钼合金为MoNb、MoW、MoTi和MoZr中的任意一种或两种以上的混合物。
优选地,上述导电结构中,所述钼合金中除Mo以外的元素的原子百分比在0.001at%至50at%之间。
本发明实施例还提供了一种薄膜晶体管,包括栅电极、源电极和漏电极,所述栅电极、源电极和漏电极中的至少一者以上所述的导电结构。
本发明实施例还提供了一种薄膜晶体管阵列基板,包括:
基板;
形成在所述基板上的薄膜晶体管阵列、栅极线和数据线,所述薄膜晶体管阵列包括多个薄膜晶体管,所述薄膜晶体管包括栅电极、源电极和漏电极;
在由所述栅极线和所述数据线交叉界定出的像素区域还形成有像素电极;
其中,所述栅极线与对应的栅电极连接,所述数据线与对应的源电极连接,所述像素电极与对应的漏电极连接;
所述数据线、源电极、栅极线、栅电极和漏电极中的至少一者采用以上所述的导电结构。
本发明实施例还提供了一种显示装置,包括以上所述的薄膜晶体管阵列基板。
本发明实施例还提供了一种导电结构的制造方法,包括:
在基底上形成一用于阻挡铜离子向所述基底扩散的阻挡层;
在所述阻挡层上形成一用于阻挡经由所述阻挡层向上扩散的离子的防扩散层;
在所述防扩散层上形成一铜层,所述铜层的材料为铜或铜合金。
优选地,上述方法中,
进一步采用钼合金作溅射源,通过溅射工艺,形成所述阻挡层;
进一步采用钼作为溅射源,通过溅射工艺,形成所述防扩散层;
进一步采用铜或铜合金作为溅射源,通过溅射工艺,形成所述铜层;
其中,所述钼合金的材料为MoNb、MoW、MoTi和MoZr中的任意一种或两种以上的混合物。
本发明提供的导电结构及其制造方法,其中所述导电结构具有多层结构,利用该多层结构阻止外部离子扩散进入铜层以及铜层铜离子的向外扩散,从而减少离子扩散对铜金属层的电学性能和化学耐腐蚀性能的不良影响以及铜离子扩散对基底等的影响;该导电结构中的阻挡层,与玻璃基板等衬底基板或半导体层之间具有良好的粘附性,能够提高导电结构的粘合稳固程度;并且,该多层导电结构中的各个层都具有类似的刻蚀选择性,有利于对多层导电结构的刻蚀/图案化处理。本发明提供的薄膜晶体管、阵列基板和显示装置,由于采用了上述的导电结构,因而也具有上述有益效果。
附图说明
图1为本发明实施例提供的一种导电结构的结构示意图;
图2为本发明实施例提供的一种薄膜晶体管阵列基板的结构示意图。
其中:
1为基底
2a为阻挡层
2b为防扩散层
2c为铜层
5为栅极
6为栅极绝缘层
7为本征半导体层
8为欧姆接触半导体层
9a为数据线
9b为源电极
9c为漏电极
10为保护层
11为像素电极
12为过孔
13为衬底基板
具体实施方式
由于铜离子的易扩散特性,本发明抛弃了单独使用铜导电结构的做法,而是使用多层导电结构,以减少或避免铜层的铜离子的向外扩散,以及减少或避免外部离子向铜层的扩散。并且,本发明的多层导电结构,还能够克服现有的铜导电结构对于绝缘基板(例如玻璃基板或半导体层)具有较低粘附性而容易发生膜的脱落的问题。
为使本发明的目的、技术方案和优点更加清楚,下面将结合附图及具体实施例对本发明进行详细描述。
本实施例提供了一种多层导电结构,该多层导电结构在被图案化时能被可靠的图案化从而形成良好的侧部轮廓。如图1所示,该导电结构包括:
由铜或铜合金形成的铜层2c;
用于阻挡所述铜层2c的铜离子向外扩散的阻挡层2a;
用于阻挡外部离子扩散至所述铜层2c的防扩散层2b,所述防扩散层2b设置在所述铜层2c与所述阻挡层2a之间。
上述结构中,所述阻挡层2a可以形成在一基底1之上。其中,基底1可以为玻璃基板、塑料基板等衬底基板,也可以为电子元器件的某一或某几个膜层,比如薄膜晶体管的栅绝缘层、半导体层、钝化层等。所述基底1可以为单层,也可以为两层及两层以上。并且,所述衬底1可以同时包含电子器件的不同区域,比如在采用该导电结构制作阵列基板的漏电极时,所述阻挡层2a可以同时形成在有源层和栅绝缘层之上(即此时有源层和栅绝缘层同时构成了基底1)。
通过以上结构,所述防扩散层2b能够阻挡外部离子(如阻挡层2a中的离子或基底1中的离子)扩散进入铜层2c,以保证铜层的导电性能及化学耐腐蚀性;同时铜层2c中的铜离子也将被阻挡层2a所阻挡,难以扩散至基底1中,从而能够减少或避免对基底1的影响。
作为一种优选实施方式,本实施例中,所述阻挡层2a的材料为钼合金。所述钼合金可以从MoNb、MoW、MoTi和MoZr中的任意一种,还可以是从以上多种中的两种以上的物质所组成的混合物。
采用钼合金的阻挡层2a,与基底1(如衬底基板或半导体层)之间具有良好的粘附性,能够加强基底1与导电结构之间的粘附,从而能够提高导电结构与基底1之间结合的稳固性;阻挡层2a还能够防止铜离子扩散到基底1内,并且呈现出与防扩散层2b、铜层2c相类似的刻蚀选择性,从而有利于在多层结构的刻蚀/图案化过程中对它们同时进行蚀刻处理。
本实施例中,在采用钼合金形成所述阻挡层2a时,所述钼合金中除Mo以外的元素的原子百分比在0.001at%至50at%之间。例如,在所述钼合金为MoNb时,则钼合金中Nb的原子百分比在0.001at%至50at%之间;在所述钼合金采用MoNb和MoTi时,则钼合金中Nb和Ti二者的原子百分比之和在0.001at%至50at%之间。
为了防止阻挡层2a中的金属离子扩散到铜层2c中,导致铜层2c电学性能和化学耐腐蚀性能的下降,上述结构在阻挡层2a和铜层2c之间沉积一层防扩散层2b。防扩散层2b为具有和阻挡层2a、铜层2c相类似的晶体结构材料,能够保证阻挡层2a与防扩散层2b之间界面、防扩散层2b与铜层2c之间界面的粘附性,同时还具有与阻挡层2a和铜层2c类似的刻蚀选择性。具体的来说,防扩散材料为钼(Mo),钼(Mo)为体心立方的晶体结构,和钼合金(例如MoNb)具有相似的晶体结构,和具有面心立方晶体结构的铜同属于立方晶系,从而能够保证良好的界面性能。采用上述方法形成的导电结构,具有良好的界面特性和刻蚀性能;该多层导电结构在被图案化时,能够被可靠的图案化从而形成良好的侧部轮廓。并且,当该导电结构应用于具体电子器件时,阻挡层会与其他膜层发生接触,此时防扩散层2b也可以防止与阻挡层接触的其他层中的金属离子扩散到铜层2c中。
本实施例的导电结构,能减少或避免被铜层2c被腐蚀和氧化,且能够紧密地附着在基底上,同时有效克服金属离子或其他杂质对铜层的扩散所导致的铜层电学性能和化学耐腐蚀性能的下降问题。
相应的,本实施例还提供了一种制造图1所示导电结构的方法,该方法包括:
首先,在基底1上形成一阻挡层2a,该阻挡层2a用于阻挡铜离子向所述基底扩散;
然后,在所述阻挡层2a上形成一防扩散层2b,该防扩散层2b用于阻挡经由所述阻挡层向上扩散的离子;
再在所述防扩散层2b上形成一铜层2c,所述铜层2c的材料为铜或铜合金。
这里,所述阻挡层2a、防扩散层2b和铜层2c,均可以通过溅射工艺形成,其中,所述阻挡层2a采用钼合金作溅射源,所述防扩散层2b采用钼作溅射源,铜层2c采用铜或铜合金作溅射源。其中,所述钼合金的材料具体可以是MoNb、MoW、MoTi和MoZr中的任意一种或两种以上的混合物。以上各层也可以采用其他方式形成,如化学蒸镀方式或物理沉积方式等,此处不再赘述。
在形成以上结构后,本实施例还可以对上述结构做进一步图案化处理,例如光刻胶涂布、曝光显影以及刻蚀等处理,得到最终所需要的图案。
上述导电结构,可以应用于薄膜晶体管、薄膜晶体管阵列基板中。因此,本发明实施例还提供了一种薄膜晶体管,该薄膜晶体管通常可以包括栅电极、源电极和漏电极,其中所述栅电极、源电极和漏电极中的至少一者采用以上所述的导电结构。所述薄膜晶体管采用上述导电结构外的其他部分以及薄膜晶体管的整体结构,可以采用现有技术中的任何技术方案,此处不赘述。
本发明实施例还提供了一种薄膜晶体管阵列基板,该阵列基板通常可以包括:
基板;
形成在所述基板上的薄膜晶体管阵列、栅极线和数据线,所述薄膜晶体管阵列包括多个薄膜晶体管,所述薄膜晶体管包括栅电极、源电极和漏电极;
在由所述栅极线和所述数据线交叉界定出的像素区域还形成有像素电极;
其中,所述栅极线与对应的栅电极连接,所述数据线与对应的源电极连接,所述像素电极与对应的漏电极连接;
其中,在该阵列基板上,所述数据线、源电极、栅极线、栅电极和漏电极中的至少一者采用以上所述的导电结构。
本实施例中,薄膜晶体管阵列基板中,栅极线和栅电极组成栅极导电结构,数据线、源电极和漏电极组成数据导电结构。栅极线形成于基板上并沿着第一方向延伸,数据线形成在栅极绝缘层之上并沿着第二方向延伸,这里,第一方向可以与第二方向垂直。漏电极与源电极间隔设置。像素电极形成在由栅极线和数据线交叉界定出的像素区域中,并电连接至漏电极。
本实施例中,栅极导电结构和数据导电结构中的任一单元,如栅电极、栅极线或漏电极等,都可以采用图1所示的导电结构。
以下将结合附图2,对本发明实施例的一种薄膜晶体管阵列基板作更为详细的说明。
图2所示的阵列基板,可以应用于液晶显示器或有机发光显示器,该阵列基板包括一衬底基板13,配置在该衬底基板13上的至少一栅极导电结构5。这里,该栅极导电结构5包括栅电极和栅极线,栅电极和/或栅极线可以采用图1所示的导电结构,即包括阻挡层、防扩散层和铜层。此时,该阻挡层形成于该衬底基板13上,该阻挡层材质为钼合金(例如MoNb、MoW、MoTi、MoZr等中的一种或多种),其中,合金中Nb(或者W、Ti、Zr等)的原子百分比在0.001at%至50at%的范围内。该阻挡层的厚度由所需要的界面情况和刻蚀情况来决定,具体的,可以为至之间。该防扩散层形成于该阻挡层上,防扩散层材料为钼(Mo),防扩散层的厚度由所需要的界面情况和刻蚀情况来决定,具体的,可以为至之间。该铜层形成在该防扩散层上,材料可以是铜金属或者铜合金。
上述由阻挡层、防扩散层和铜层组成的栅极导电结构可以克服现有技术中铜导线与衬底基板之间粘附性不佳的问题,由钼合金构成的阻挡层可以提高铜层与衬底基板之间的粘附性,同时阻止铜离子向衬底基板的扩散;并且,采用钼(Mo)材料形成的防扩散层材料,可以阻止阻挡层中Nb(或者W、Ti、Zr等)离子向铜层的扩散,从而防止由上述离子扩散所造成铜金属层的电学性能和化学耐腐蚀性能下降的问题,保证铜金属层的低电阻值特性。同时,该阻挡层、防扩散层和铜层在进行刻蚀制程时具有类似的被刻蚀特性,使得刻蚀易形成良好的图形,减少制程成本。
图2所示的阵列基板,还包括一配置于该衬底基板13上的栅极绝缘层6,该栅极绝缘层6覆盖该栅极导电结构5。一通道元件(即有源层)配置于该栅极绝缘层6上,包括一本征半导体层7和一欧姆接触半导体层8。该欧姆接触半导体层8配置于该本征半导体层7上。当然,所述有源层也可以包括有机半导体,或金属氧化物半导体(如IGZO)等。
图2所示的阵列基板,还包括至少一数据导电结构,该数据导电结构配置在该通道元件上。该数据导电结构包含数据线9a、源电极9b和漏电极9c。该数据线9a配置在栅极绝缘层6上。该源电极9b和漏电极9c配置在该通道元件上,并且该源电极9b电连接至数据线9a,漏电极9c与源电极9b间隔设置。该数据线9a、源电极9b和漏电极9c中的任一一者或两者以上均可以采用图1中所示的导电结构,即包括阻挡层、防扩散层和铜层。此时,该阻挡层形成于栅极绝缘层6或所述通道元件上,该阻挡层材质为钼合金(例如MoNb、MoW、MoTi、MoZr等中的一种或多种),其中,合金中Nb(或者W、Ti、Zr等)的原子百分比在0.001at%至50at%的范围内。阻挡层的厚度由所需要的界面情况和刻蚀情况来决定,具体的,为至之间。该防扩散层形成与该阻挡层上,防扩散层材料为钼(Mo),防扩散的厚度由所需要的界面情况和刻蚀情况来决定,具体的,为至之间。该铜层形成在该防扩散层上,材料可以是铜金属层或者铜合金层。
上述由阻挡层、防扩散层和铜层组成的数据导电结构可以克服铜导线与半导体层之间界面粘附性不佳的问题。由钼合金构成的阻挡层,可以克服铜导线与半导体层之间界面粘附性不佳的问题,并且可以阻止铜金属层与半导体之间铜原子与硅原子的相互扩散,减少或避免离子扩散对半导体层和铜层的电学性能的不良影响。并且,采用钼(Mo)形成的防扩散层能够阻止阻挡层中Nb(或者W、Ti、Zr等)离子向铜层扩散,防止降低铜金属层的电学性能和化学耐腐蚀性能,保证铜金属层的低电阻值。同时,该阻挡层、防扩散层和铜层在进行刻蚀制程时具有类似的被刻蚀特性,使得刻蚀易形成良好的图形,减少制程成本。
图2所示的阵列基板,还包括一保护层10,该保护层10配置在该数据线9a、源电极9b和漏电极9c及栅极绝缘层6上;一像素电极11配置于该保护层10上,并可以通过一过孔12电性连接至该漏电极9c。
本发明实施例所述的阵列基板,采用上述导电结构外的其他部分以及薄膜晶体管阵列基板的整体结构,并不局限于上述所述的方案,而是可以采用现有技术中的任何技术方案来实现,比如还可以加入公共电极形成ADS型的阵列基板,还可以制成Color Filter on Array(COA)形式的阵列基板等,此处不赘述。
本发明实施例还提供一种显示装置,其中,该显示装置使用了如上述实施例所述的任意一种薄膜晶体管阵列基板。所述显示装置可以为:液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅是本发明的实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (10)
1.一种导电结构,其特征在于,包括:
由铜或铜合金形成的铜层;
用于阻挡所述铜层的铜离子向外扩散的阻挡层;
用于阻挡外部离子扩散至所述铜层的防扩散层,所述防扩散层设置在所述铜层与所述阻挡层之间。
2.如权利要求1所述的导电结构,其特征在于,所述阻挡层的材料为钼合金,所述防扩散层的材料为钼。
3.如权利要求1或2所述的导电结构,其特征在于,所述钼合金为MoNb、MoW、MoTi和MoZr中的任意一种或两种以上的混合物。
4.如权利要求3所述的导电结构,其特征在于,
所述钼合金中除Mo以外的元素的原子百分比在0.001at%至50at%之间。
6.一种薄膜晶体管,其特征在于,包括栅电极、源电极和漏电极,所述栅电极、源电极和漏电极中的至少一者采用权利要求1至5任一项所述的导电结构。
7.一种薄膜晶体管阵列基板,其特征在于,包括:
基板;
形成在所述基板上的薄膜晶体管阵列、栅极线和数据线,所述薄膜晶体管阵列包括多个薄膜晶体管,所述薄膜晶体管包括栅电极、源电极和漏电极;
在由所述栅极线和所述数据线交叉界定出的像素区域还形成有像素电极;
其中,所述栅极线与对应的栅电极连接,所述数据线与对应的源电极连接,所述像素电极与对应的漏电极连接;
所述数据线、源电极、栅极线、栅电极和漏电极中的至少一者采用权利要求1至5任一项所述的导电结构。
8.一种显示装置,其特征在于,包括权利要求7所述的薄膜晶体管阵列基板。
9.一种导电结构的制造方法,其特征在于,包括:
在基底上形成一用于阻挡铜离子向所述基底扩散的阻挡层;
在所述阻挡层上形成一用于阻挡经由所述阻挡层向上扩散的离子的防扩散层;
在所述防扩散层上形成一铜层,所述铜层的材料为铜或铜合金。
10.如权利要求9所述的方法,其特征在于,
进一步采用钼合金作溅射源,通过溅射工艺,形成所述阻挡层;
进一步采用钼作为溅射源,通过溅射工艺,形成所述防扩散层;
进一步采用铜或铜合金作为溅射源,通过溅射工艺,形成所述铜层;
其中,所述钼合金的材料为MoNb、MoW、MoTi和MoZr中的任意一种或两种以上的混合物。
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