CN103531594B - 一种阵列基板和显示器件 - Google Patents

一种阵列基板和显示器件 Download PDF

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CN103531594B
CN103531594B CN201310528849.1A CN201310528849A CN103531594B CN 103531594 B CN103531594 B CN 103531594B CN 201310528849 A CN201310528849 A CN 201310528849A CN 103531594 B CN103531594 B CN 103531594B
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copper
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CN103531594A (zh
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姚琪
张锋
曹占锋
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BOE Technology Group Co Ltd
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    • H01L27/1218Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract

本发明公开了一种阵列基板和显示器件,其中的阵列基板包括玻璃基板,在玻璃基板上设置有第一缓冲层,金属薄膜设置在第一缓冲层上方,第一缓冲层和金属薄膜之间还设置有第二缓冲层。通过在金属薄膜和第一缓冲层之间增加设置一层第二缓冲层,加热条件下,利用铜合金中除了铜之外的其他元素会析出到金属表面,退火后形成阻挡铜金属向半导体层扩散的第二缓冲层,避免金属元素的扩散影响半导体的特性,同时也能防止半导体材料中的物质扩散到金属薄膜中,能够增加金属薄膜与玻璃基板的附着能力,还能提高金属薄膜与第一缓冲层的结合能力。

Description

一种阵列基板和显示器件
技术领域
本发明涉及显示技术领域,特别涉及一种阵列基板和显示器件。
背景技术
为满足大尺寸液晶显示器的发展趋势,在进行TFT-LCD(Thin Film Transistor-Liquid Crystal Display,薄膜场效应晶体管液晶显示器)面板的制作过程中一般使用铜(Cu)作为阵列基板的栅线。
在阵列基板的加工工艺过程中,在基板衬底(一般用玻璃)的表面沉积形成金属薄膜(Cu薄膜),之后还要经过涂光刻胶形成光刻膜,紫外线透过掩膜板照射光刻膜,经过曝光显影得到需要形状的图形,再对基板表面进行刻蚀,形成栅线。再形成绝缘层、半导体薄膜,重复薄膜沉积和刻蚀,形成不同材料不同形状的薄膜。
在玻璃的表面直接进行金属薄膜的沉积,由于金属Cu和玻璃直接接触时的附着能力较差,影响金属薄膜的沉积效果。另外金属Cu还可能扩散并通过绝缘层,还影响半导体的特性。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是如何增强金属Cu和玻璃之间的附着力,防止金属Cu向绝缘层扩散。
(二)技术方案
为解决上述技术问题,本发明提供了一种阵列基板,所述阵列基板包括玻璃基板,其特征在于,在所述玻璃基板上设置有第一缓冲层,所述金属薄膜设置在所述第一缓冲层上方,所述第一缓冲层和所述金属薄膜之间还设置有第二缓冲层。
进一步地,所述第二缓冲层、所述第一缓冲层和所述玻璃基板关 于所述金属薄膜对称设置。
进一步地,所述第一缓冲层的厚度为
进一步地,所述第二缓冲层的厚度为
进一步地,所述第一缓冲层的材质为钼、钛或钼合金。
进一步地,所述钼合金为钼钛、钼钽、钼钨中的一种。
进一步地,所述第二缓冲层的材质为铜合金。
进一步地,所述铜合金为铜与以下任意一种元素组成的铜二元合金:钼、镁、铝、钽、钨、钙、铌、银、镓或锰。
进一步地,所述铜合金为铜与以下任意两种元素组成的铜三元合金:钼、镁、铝、钽、钨、钙、铌、银、镓或锰。
为解决上述问题,本发明也提供了一种显示器件,其中包括权利要求上述的阵列基板。
(三)有益效果
本发明实施例的一种阵列基板,包括玻璃基板,在玻璃基板上设置有第一缓冲层,金属薄膜设置在第一缓冲层上方,第一缓冲层和金属薄膜之间还设置有第二缓冲层。通过在金属薄膜和第一缓冲层之间增加设置一层第二缓冲层,加热条件下,利用铜合金中除了铜之外的其他元素会析出到金属表面,退火后形成阻挡铜金属向半导体层扩散的第二缓冲层,避免金属元素的扩散影响半导体的特性,同时也能防止半导体材料中的物质扩散到金属薄膜中,能够增加金属薄膜与玻璃基板的附着能力,还能提高金属薄膜与第一缓冲层的结合能力。本发明还提供了基于上述阵列基板的显示器件。
附图说明
图1是本发明实施例提供的阵列基板的结构图;
图2是本发明实施例提供的阵列基板的另一种结构图;
图3是本实发明实施例提供的铜合金退火前后对比图;
图4是本发明实施例提供的阵列基板退火前后对比图;
图5是本发明实施例提供的另一种阵列基板退火前后对比图。
具体实施方式
下面结合附图和实施例,对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明,但不用来限制本发明的范围。
目前显示器制作行业内在使用金属Cu做栅线时,通常采用钛(Ti)、钼(Mo)、钼钛合金(MoTi)和其他钼合金等做阵列基板的缓冲层。但是现有技术中的缓冲层只有一层,另外,由于金属薄膜和缓冲层的材料不一样,刻蚀速度不相同,刻蚀所用的总时间多数是在花在腐蚀缓冲层上,缓冲层的刻蚀速率较慢,而金属薄膜的刻蚀速率较快,导致刻蚀后的坡度角很难控制。
本发明实施例提供了一种阵列基板,如图1所示,阵列基板包括玻璃基板00,其特征在于,在玻璃基板00上设置有第一缓冲层10,金属薄膜30设置在第一缓冲层10上方,第一缓冲层10和金属薄膜30之间还设置有第二缓冲层20。
上述阵列基板通过在金属薄膜和第一缓冲层之间增加设置一层第二缓冲层,即用两层缓冲层代替原来的一层缓冲层,加热条件下,利用铜合金中除了铜之外的其他元素会析出到金属表面,退火后形成阻挡铜金属向半导体层扩散的第二缓冲层,避免金属元素的扩散影响半导体的特性,同时也能防止半导体材料中的物质扩散到金属薄膜中,能够增加金属薄膜与玻璃基板的附着能力,还能提高金属薄膜与第一缓冲层的结合能力。
优选地,本实施例中的第二缓冲层20、第一缓冲层10和玻璃基板00还可以关于金属薄膜30对称设置。上述给出了玻璃基板上金属电极层的结构依次为第一缓冲层10、第二缓冲层20、金属薄膜30,其中的金属薄膜30为铜或铜合金。进一步地,本实施例中玻璃基板上金属电极层的结构还可以依次为:第一缓冲层10、第二缓冲层20、金属薄膜30、第二缓冲层20、第一缓冲层10,最后在靠近两侧的第一缓冲层外 侧均有玻璃基板00,如图2所示。
优选地,本实施例对于图1和图2中的两种结构中的第一缓冲层10的厚度为为了不影响后续加工工艺的刻蚀效果,要尽量减小第一缓冲层的厚度,本实施例更优选的第一缓冲层10的厚度为第一缓冲层10的材质一般为钼(Mo)、钛(Ti)或钼合金。优选地,本实施例中优选的钼合金为钼钛合金(MoTi)、钼钽合金(MoTa)、钼钨合金(MoW)中的一种,除此之外还可以是其它钼合金。
优选地,本实施例对于图1和图2中的两种结构中的第二缓冲层20的厚度为材质为铜合金。其中的铜合金为铜(Cu)与以下任意一种元素组成的铜二元合金:钼(Mo)、镁(Mg)、铝(Al)、钽(Ta)、钨(W)、钙(Ca)、铌(Nb)、银(Ag)、镓(Ga)或锰(Mn)。或者铜合金为铜与以下任意两种元素组成的铜三元合金钼(Mo)、镁(Mg)、铝(Al)、钽(Ta)、钨(W)、钙(Ca)、铌(Nb)、银(Ag)、镓(Ga)或锰(Mn)。
现有技术中铜与玻璃基板直接接触,附着能力比较差,通过设置铜合金材质的第二缓冲层20,再结合第一缓冲层10能够增强金属薄膜30与玻璃基板00的附着能力。第一缓冲层10用户实现第二缓冲层20的铜合金能够更好地与玻璃基板00附着,防止第二缓冲层20中铜合金中的铜的扩散,同时还能防止IGZO(Indium Gallium Zinc Oxide,铟镓锌氧化物)等氧化物半导体中的其他物质扩散到金属铜的里面。
本实施例中的阵列基板上的金属电极层的加工步骤流程如下:
首先在玻璃基板上形成铜电极材料层前,可以先在玻璃基板上形成的Mo、Ti,或者Mo合金等第一缓冲层,用于第二缓冲层Cu合金更好的与玻璃附着。更有选的厚度为因为第一缓冲层的厚度要尽量小,以免影响后续刻蚀效果。
之后,在第一缓冲层上形成的Cu合金的第二缓冲层, Cu合金材料可以是Cu和Mo、Mg、Al、Ta、W、Nb、Ag、Ga、Mn等中任意一种组成的铜二元合金,也可以是Cu和上述金属中两种组成的铜三元合金。金属电极层结构可以是缓冲层(包括第一缓冲层和第二缓冲层)、金属薄膜,也可以是缓冲层(包括第一缓冲层和第二缓冲层)、金属薄膜、缓冲层,其中缓冲层为第一缓冲层在外部,靠近玻璃基板,而第二缓冲层的铜合金在内部,靠近金属铜。
镀膜完成后,先进行曝光然后是刻蚀工艺,形成图形后进行退火,将铜合金中的非铜材料扩散到界面。其中Cu合金(以CuMo合金为例)在退火前后的变化如图3所示,可以看出退火之后,Mo元素靠近第二缓冲层的上下两表面,而Cu元素分布在上下两层Mo元素之间,位于第二缓冲层的中部。其中图1中所示的阵列基板的铜合金退火前后对比图如图4所示,图2中所示的阵列基板的铜合金退火前后对比图如图5所示,图4和图5中非铜元素扩散到界面的部分用90表示。
综上所述,本实施例提供的阵列基板通过在金属薄膜和玻璃基板之间设置材质不同的第二缓冲层和第一缓冲层,利用铜合金中除了铜之外的其他元素会析出到金属表面,退火后形成阻挡铜金属向半导体层扩散的第二缓冲层,避免金属元素的扩散影响半导体的特性,同时也能防止半导体材料中的物质扩散到金属薄膜中,能够增加金属薄膜与玻璃基板的附着能力,还能提高金属薄膜与第一缓冲层的结合能力。进一步地,现有技术中一层缓冲层的材质与本发明改进后的第一缓冲层材质相同,但是改进后的结构中还包括第二缓冲层,由于第二缓冲层为铜合金材质,铜合金的电化学特性与金属铜相似,更容易形成符合要求的坡度角,因此进行刻蚀的时候刻蚀速度不会相差很大,对于刻蚀后的坡度角比较容易控制。
进一步地,基于上述阵列基板,本实施例中还提供了一种显示器件,其中包括上述阵列基板。
以上实施方式仅用于说明本发明,而并非对本发明的限制,有关技术领域的普通技术人员,在不脱离本发明的精神和范围的情况下,还可以做出各种变化和变型,因此所有等同的技术方案也属于本发明的范畴,本发明的专利保护范围应由权利要求限定。

Claims (8)

1.一种阵列基板,所述阵列基板包括玻璃基板,其特征在于,在所述玻璃基板上设置有第一缓冲层,金属薄膜设置在所述第一缓冲层上方,所述第一缓冲层和所述金属薄膜之间还设置有第二缓冲层;
其中,所述第二缓冲层为铜合金层,其在退火后表面具有非铜材料层,所述非铜材料层与所述第一缓冲层接触,所述非铜材料层的材质为铜合金中的非铜材料;
其中,所述第二缓冲层、所述第一缓冲层和所述玻璃基板关于所述金属薄膜对称设置。
2.如权利要求1所述的阵列基板,其特征在于,所述第一缓冲层的厚度为
3.如权利要求1所述的阵列基板,其特征在于,所述第二缓冲层的厚度为
4.如权利要求1所述的阵列基板,其特征在于,所述第一缓冲层的材质为钼、钛或钼合金。
5.如权利要求4所述的阵列基板,其特征在于,所述钼合金为钼钛、钼钽、钼钨中的一种。
6.如权利要求1所述的阵列基板,其特征在于,所述铜合金为铜与以下任意一种元素组成的铜二元合金:钼、镁、铝、钽、钨、钙、铌、银、镓或锰。
7.如权利要求1所述的阵列基板,其特征在于,所述铜合金为铜与以下任意两种元素组成的铜三元合金:钼、镁、铝、钽、钨、钙、铌、银、镓或锰。
8.一种显示器件,其特征在于,所述显示器件中包括权利要求1-7中任一项所述的阵列基板。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531594B (zh) * 2013-10-30 2016-08-24 京东方科技集团股份有限公司 一种阵列基板和显示器件
CN106847928B (zh) * 2017-02-06 2020-06-19 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板和显示装置
CN106981426B (zh) * 2017-04-06 2020-04-03 京东方科技集团股份有限公司 薄膜晶体管的制备方法、显示装置
US10556823B2 (en) 2017-06-20 2020-02-11 Apple Inc. Interior coatings for glass structures in electronic devices
CN109791933A (zh) * 2017-08-15 2019-05-21 深圳市柔宇科技有限公司 膜层结构和显示面板
CN111246662A (zh) * 2018-11-29 2020-06-05 欣兴电子股份有限公司 载板结构及其制作方法
CN111244034A (zh) * 2020-01-17 2020-06-05 Tcl华星光电技术有限公司 阵列基板及其制造方法
US20230043951A1 (en) * 2020-09-07 2023-02-09 Boe Technology Group Co., Ltd. Array substrate and manufacturing method therefor, display panel, and backlight module
CN112992934B (zh) * 2021-02-07 2023-05-09 Tcl华星光电技术有限公司 阵列基板及制备方法、显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1687837A (zh) * 2005-06-02 2005-10-26 友达光电股份有限公司 铜导线结构及其制造方法
CN101090123A (zh) * 2006-06-16 2007-12-19 台湾薄膜电晶体液晶显示器产业协会 具铜导线结构的薄膜晶体管及其制造方法
CN102629609A (zh) * 2011-07-22 2012-08-08 京东方科技集团股份有限公司 阵列基板及其制作方法、液晶面板、显示装置
CN102664193A (zh) * 2012-04-01 2012-09-12 京东方科技集团股份有限公司 导电结构及制造方法、薄膜晶体管、阵列基板和显示装置
CN103219389A (zh) * 2013-03-21 2013-07-24 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050224977A1 (en) * 2004-01-29 2005-10-13 Yusuke Yoshimura Wiring substrate and method using the same
CN103000627A (zh) * 2012-12-06 2013-03-27 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN103531594B (zh) * 2013-10-30 2016-08-24 京东方科技集团股份有限公司 一种阵列基板和显示器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1687837A (zh) * 2005-06-02 2005-10-26 友达光电股份有限公司 铜导线结构及其制造方法
CN101090123A (zh) * 2006-06-16 2007-12-19 台湾薄膜电晶体液晶显示器产业协会 具铜导线结构的薄膜晶体管及其制造方法
CN102629609A (zh) * 2011-07-22 2012-08-08 京东方科技集团股份有限公司 阵列基板及其制作方法、液晶面板、显示装置
CN102664193A (zh) * 2012-04-01 2012-09-12 京东方科技集团股份有限公司 导电结构及制造方法、薄膜晶体管、阵列基板和显示装置
CN103219389A (zh) * 2013-03-21 2013-07-24 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置

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