TW335543B - Row decoder with level translator - Google Patents

Row decoder with level translator

Info

Publication number
TW335543B
TW335543B TW085114095A TW85114095A TW335543B TW 335543 B TW335543 B TW 335543B TW 085114095 A TW085114095 A TW 085114095A TW 85114095 A TW85114095 A TW 85114095A TW 335543 B TW335543 B TW 335543B
Authority
TW
Taiwan
Prior art keywords
voltage
row decoder
level translator
output signal
voltage range
Prior art date
Application number
TW085114095A
Other languages
English (en)
Inventor
P Mcadams Hugh
Koelling Jeffery
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW335543B publication Critical patent/TW335543B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
TW085114095A 1995-05-05 1996-11-18 Row decoder with level translator TW335543B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/435,689 US5696721A (en) 1995-05-05 1995-05-05 Dynamic random access memory having row decoder with level translator for driving a word line voltage above and below an operating supply voltage range

Publications (1)

Publication Number Publication Date
TW335543B true TW335543B (en) 1998-07-01

Family

ID=23729402

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085114095A TW335543B (en) 1995-05-05 1996-11-18 Row decoder with level translator

Country Status (5)

Country Link
US (2) US5696721A (zh)
EP (1) EP0741386B1 (zh)
JP (3) JP4436897B2 (zh)
KR (1) KR100468549B1 (zh)
TW (1) TW335543B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009037A (en) * 1997-09-25 1999-12-28 Texas Instruments Incorporated Dynamic logic memory addressing circuits, systems, and methods with reduced capacitively loaded predecoders
EP0933784A1 (en) * 1997-12-31 1999-08-04 STMicroelectronics S.r.l. High voltage driver circuit for the decoding phase in multilevel non-volatile memory devices.
KR100268446B1 (ko) * 1998-08-07 2000-10-16 윤종용 트리플 웰 구조를 갖는 반도체 메모리 장치
US6278297B1 (en) 1999-09-14 2001-08-21 Texas Instruments Incorporated Row decoder with switched power supply
KR100368312B1 (ko) * 1999-12-27 2003-01-24 주식회사 하이닉스반도체 워드라인 디코더
KR100481857B1 (ko) 2002-08-14 2005-04-11 삼성전자주식회사 레이아웃 면적을 줄이고 뱅크 마다 독립적인 동작을수행할 수 있는 디코더를 갖는 플레쉬 메모리 장치
US6785186B2 (en) * 2002-08-21 2004-08-31 Micron Technology, Inc. Design of an high speed xdecoder driving a large wordline load consuming less switching current for use in high speed syncflash memory
US7006389B2 (en) * 2003-12-12 2006-02-28 Micron Technology, Inc. Voltage translator for multiple voltage operations
KR100582422B1 (ko) * 2004-05-15 2006-05-22 에스티마이크로일렉트로닉스 엔.브이. 낸드 플래시 메모리 소자
KR101064186B1 (ko) * 2005-08-10 2011-09-14 삼성전자주식회사 레벨쉬프터와, 이를 갖는 표시장치
US7450454B1 (en) 2007-05-09 2008-11-11 Freescale Semiconductor, Inc. Low voltage data path in memory array
JP2008287826A (ja) * 2007-05-21 2008-11-27 Panasonic Corp 半導体記憶装置
JP5191766B2 (ja) * 2008-03-24 2013-05-08 ルネサスエレクトロニクス株式会社 デコーダ回路
US7859919B2 (en) * 2008-08-27 2010-12-28 Freescale Semiconductor, Inc. Memory device and method thereof
JP5202248B2 (ja) * 2008-11-26 2013-06-05 パナソニック株式会社 半導体記憶装置
KR101749009B1 (ko) 2013-08-06 2017-06-19 애플 인크. 원격 디바이스로부터의 활동에 기초한 스마트 응답의 자동 활성화

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US4417325A (en) * 1981-07-13 1983-11-22 Eliyahou Harari Highly scaleable dynamic ram cell with self-signal amplification
JPS5922359A (ja) * 1982-07-29 1984-02-04 Nec Corp 集積化半導体記憶装置
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US5324982A (en) * 1985-09-25 1994-06-28 Hitachi, Ltd. Semiconductor memory device having bipolar transistor and structure to avoid soft error
US5238860A (en) * 1987-07-10 1993-08-24 Kabushiki Kaisha Toshiba Semiconductor device having different impurity concentration wells
DE3886283T2 (de) * 1987-07-10 1994-05-11 Toshiba Kawasaki Kk Halbleiterbauelement mit Bereichen unterschiedlicher Störstellenkonzentration.
JPH02168494A (ja) * 1988-12-21 1990-06-28 Nec Corp 半導体記憶回路
GB2243233A (en) * 1990-04-06 1991-10-23 Mosaid Inc DRAM word line driver
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KR940002859B1 (ko) * 1991-03-14 1994-04-04 삼성전자 주식회사 반도체 메모리장치에서의 워드라인 구동회로
JP3128262B2 (ja) * 1991-05-28 2001-01-29 株式会社東芝 半導体集積回路装置
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KR960000836B1 (ko) * 1991-11-21 1996-01-13 삼성전자주식회사 반도체 메모리 장치의 워드라인 구동회로
KR0113252Y1 (ko) * 1991-12-24 1998-04-14 문정환 워드라인 전압 공급회로
JPH05189968A (ja) * 1992-01-16 1993-07-30 Mitsubishi Electric Corp 半導体記憶装置
KR940003026A (ko) * 1992-07-13 1994-02-19 김광호 트리플웰을 이용한 반도체장치
KR960006373B1 (ko) * 1992-10-31 1996-05-15 삼성전자주식회사 반도체 메모리 장치의 워드라인 구동회로
JPH06223568A (ja) * 1993-01-29 1994-08-12 Mitsubishi Electric Corp 中間電位発生装置
US5410508A (en) * 1993-05-14 1995-04-25 Micron Semiconductor, Inc. Pumped wordlines
JPH06333386A (ja) * 1993-05-20 1994-12-02 Fujitsu Ltd 半導体記憶装置
JP3150503B2 (ja) * 1993-08-06 2001-03-26 株式会社日立製作所 半導体装置
JP3667787B2 (ja) * 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置
US5650346A (en) * 1994-08-29 1997-07-22 United Microelectronics Corporation Method of forming MOSFET devices with buried bitline capacitors

Also Published As

Publication number Publication date
US5696721A (en) 1997-12-09
JP5314086B2 (ja) 2013-10-16
JPH09106677A (ja) 1997-04-22
KR100468549B1 (ko) 2005-01-29
EP0741386A2 (en) 1996-11-06
JP2007328906A (ja) 2007-12-20
US5792682A (en) 1998-08-11
JP4436897B2 (ja) 2010-03-24
JP2011210362A (ja) 2011-10-20
EP0741386B1 (en) 2011-09-21
EP0741386A3 (en) 2004-02-25

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees