ES8609848A1 - Un circuito de variacion de fase en un circuito logico - Google Patents
Un circuito de variacion de fase en un circuito logicoInfo
- Publication number
- ES8609848A1 ES8609848A1 ES545591A ES545591A ES8609848A1 ES 8609848 A1 ES8609848 A1 ES 8609848A1 ES 545591 A ES545591 A ES 545591A ES 545591 A ES545591 A ES 545591A ES 8609848 A1 ES8609848 A1 ES 8609848A1
- Authority
- ES
- Spain
- Prior art keywords
- output
- circuit
- ecl
- control
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00163—Layout of the delay element using bipolar transistors
- H03K2005/00176—Layout of the delay element using bipolar transistors using differential stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00163—Layout of the delay element using bipolar transistors
- H03K2005/00182—Layout of the delay element using bipolar transistors using constant current sources
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Pulse Circuits (AREA)
- Networks Using Active Elements (AREA)
- Logic Circuits (AREA)
Abstract
CIRCUITO MODIFICADOR DE FASE EN UN CIRCUITO LOGICO. CONSTA DE: UNA PUERTA ECL (11) QUE COMPRENDE OCHO TRANSISTORES (1, 2, 3, 4, 6, 7, 8, 9), UNA FUENTE DE CORRIENTE (5), UN CONDENSADOR (10), UN TERMINAL DE ENTRADA (14) UN TERMINAL DE SALIDA (15), DOS FUENTES DE ALIMENTACION Y UNA FUENTE DE ALIMENTACION; UNA PUERTA DE CONTROL (12) DE EMISORES QUE COMPRENDE, SEIS TRANSISTORES (1A, 2A, 3A, 6A, 7A, 8A), UNA FUENTE DE CORRIENTE (5), DOS FUENTES DE ALIMENTACION, UNA FUENTE DE ALIMENTACION Y UN TERMINAL DE ENTRADA (16) Y UN CONDENSADOR ADICIONAL (13).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15820884A JPS6135609A (ja) | 1984-07-28 | 1984-07-28 | 位相可変回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
ES545591A0 ES545591A0 (es) | 1986-09-01 |
ES8609848A1 true ES8609848A1 (es) | 1986-09-01 |
Family
ID=15666641
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES545591A Expired ES8609848A1 (es) | 1984-07-28 | 1985-07-26 | Un circuito de variacion de fase en un circuito logico |
Country Status (9)
Country | Link |
---|---|
US (1) | US4717843A (es) |
EP (1) | EP0176184B1 (es) |
JP (1) | JPS6135609A (es) |
KR (1) | KR890005233B1 (es) |
AU (1) | AU560278B2 (es) |
BR (1) | BR8503564A (es) |
CA (1) | CA1250349A (es) |
DE (1) | DE3570025D1 (es) |
ES (1) | ES8609848A1 (es) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62250713A (ja) * | 1986-04-23 | 1987-10-31 | Fujitsu Ltd | 可変遅延回路 |
IT1218193B (it) * | 1986-12-12 | 1990-04-12 | Grass Valley Group | Circuito di compensazione del ritardo di commutazione in interdizione ad esempio di diodi led |
US5548236A (en) * | 1987-02-20 | 1996-08-20 | Pixel Instruments | Phase shifting apparatus and method with frequency multiplication |
JPS63238713A (ja) * | 1987-03-26 | 1988-10-04 | Oki Electric Ind Co Ltd | 遅延回路 |
US4812687A (en) * | 1988-07-13 | 1989-03-14 | International Business Machines Corporation | Dual direction integrating delay circuit |
US5343348A (en) * | 1991-04-03 | 1994-08-30 | Victor Company Of Japan, Ltd. | Actuator for displacing a magnetic head |
JP2594062Y2 (ja) * | 1991-12-05 | 1999-04-19 | 株式会社アドバンテスト | 微小可変遅延回路 |
US5376849A (en) * | 1992-12-04 | 1994-12-27 | International Business Machines Corporation | High resolution programmable pulse generator employing controllable delay |
US7132868B2 (en) | 2001-06-27 | 2006-11-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5382142A (en) * | 1976-12-27 | 1978-07-20 | Fujitsu Ltd | Clock distributing system |
JPS5391443A (en) * | 1977-01-20 | 1978-08-11 | Kubota Ltd | Hot-water controlling apparatus for hot-water tank |
JPS56156026A (en) * | 1980-05-02 | 1981-12-02 | Hitachi Ltd | Composite logical circuit |
JPS58108824A (ja) * | 1981-12-23 | 1983-06-29 | Fujitsu Ltd | Ecl型遅延回路 |
JPS594231A (ja) * | 1982-06-30 | 1984-01-11 | Hitachi Ltd | 高速論理回路 |
-
1984
- 1984-07-28 JP JP15820884A patent/JPS6135609A/ja active Granted
-
1985
- 1985-07-18 CA CA000487051A patent/CA1250349A/en not_active Expired
- 1985-07-24 AU AU45310/85A patent/AU560278B2/en not_active Ceased
- 1985-07-24 KR KR1019850005294A patent/KR890005233B1/ko not_active IP Right Cessation
- 1985-07-24 US US06/758,391 patent/US4717843A/en not_active Expired - Fee Related
- 1985-07-25 EP EP85305296A patent/EP0176184B1/en not_active Expired
- 1985-07-25 DE DE8585305296T patent/DE3570025D1/de not_active Expired
- 1985-07-26 BR BR8503564A patent/BR8503564A/pt not_active IP Right Cessation
- 1985-07-26 ES ES545591A patent/ES8609848A1/es not_active Expired
Also Published As
Publication number | Publication date |
---|---|
CA1250349A (en) | 1989-02-21 |
AU560278B2 (en) | 1987-04-02 |
US4717843A (en) | 1988-01-05 |
ES545591A0 (es) | 1986-09-01 |
EP0176184A1 (en) | 1986-04-02 |
JPH0220171B2 (es) | 1990-05-08 |
JPS6135609A (ja) | 1986-02-20 |
KR860001643A (ko) | 1986-03-20 |
AU4531085A (en) | 1986-02-06 |
KR890005233B1 (ko) | 1989-12-18 |
DE3570025D1 (en) | 1989-06-08 |
EP0176184B1 (en) | 1989-05-03 |
BR8503564A (pt) | 1986-04-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 20020506 |