GB1410627A - Binary frequency divider circuit - Google Patents

Abstract

1410627 FET logic divider circuit CENTRE ELECTRONIQUE HORLOGER SA 21 Nov 1972 [22 Nov 1971] 53710/72 Heading H3T A logic circuit Fig. 9 works as a binary frequency divider and includes three complementary F.E.T. stages at least one having an output E which is permitted to float under certain conditions. It may also be selectively connected to the power terminals by F.E.T.s 5, 9 or 8, 10. An input signal I and internally generated signals A, D, F interact as follows. Assuming I, E to be 0 and A, D, F to be 1, then when I goes to 1 F.E.T. 12 terms on and conducts through F.E.T. 10 which is held on by A to make D go to 0. This turns on F.E.T. 9, and when I returns to 0, F.E.T. 5 goes on and E is connected to the positive terminal through 5, 9 so that E and F become 1. When I goes to 1 again, F.E.T. 2 turns on and since E holds on F.E.T.4, A is earthed to become 0. A being 0 turns on F.E.T. 13 and D becomes 1. When I again, goes to 0, F.E.T.1 turns on to make A become I, and A and D hold on F.E.T.s 10, 8 respectively to make E become 0 again, this being the assumed starting condition. Capacitors CA, CD, CE, CF provide the storage needed for dynamic operation. A static circuit is disclosed (Fig. 8, not shown) from which the Fig. 9 dynamic cicuit is said to be derived by deletion of F.E.T.s shown to be unnecessary by the truth table.