TW328595B - Integrated circuit memory using fusible links in a scan chain - Google Patents

Integrated circuit memory using fusible links in a scan chain

Info

Publication number
TW328595B
TW328595B TW086101910A TW86101910A TW328595B TW 328595 B TW328595 B TW 328595B TW 086101910 A TW086101910 A TW 086101910A TW 86101910 A TW86101910 A TW 86101910A TW 328595 B TW328595 B TW 328595B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
circuit memory
scan chain
fusible links
memory
Prior art date
Application number
TW086101910A
Other languages
English (en)
Inventor
A Wheelus Richard
D Haverkos Todd
W Jones Kenneth
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW328595B publication Critical patent/TW328595B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/835—Masking faults in memories by using spares or by reconfiguring using programmable devices with roll call arrangements for redundant substitutions

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
TW086101910A 1996-04-29 1997-02-18 Integrated circuit memory using fusible links in a scan chain TW328595B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/641,151 US5677917A (en) 1996-04-29 1996-04-29 Integrated circuit memory using fusible links in a scan chain

Publications (1)

Publication Number Publication Date
TW328595B true TW328595B (en) 1998-03-21

Family

ID=24571152

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086101910A TW328595B (en) 1996-04-29 1997-02-18 Integrated circuit memory using fusible links in a scan chain

Country Status (5)

Country Link
US (1) US5677917A (zh)
EP (1) EP0805451A3 (zh)
JP (1) JP3968148B2 (zh)
KR (1) KR100484584B1 (zh)
TW (1) TW328595B (zh)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668818A (en) * 1996-08-06 1997-09-16 Hewlett-Packard Co. System and method for scan control of a programmable fuse circuit in an integrated circuit
TW389908B (en) * 1998-01-16 2000-05-11 Winbond Electronics Corp Patching method capable of reducing the additional leakage current caused by manufacturing defects
US6268228B1 (en) 1999-01-27 2001-07-31 International Business Machines Corporation Electrical mask identification of memory modules
JP2000311496A (ja) * 1999-04-28 2000-11-07 Nec Corp 冗長アドレス設定回路及びこれを内蔵した半導体記憶装置
DE19921868C2 (de) * 1999-05-11 2001-03-15 Siemens Ag Schaltungsanordnung zur Kontrolle von Zuständen einer Speichereinrichtung
KR100376265B1 (ko) * 1999-12-29 2003-03-17 주식회사 하이닉스반도체 모스 구조의 안티퓨즈를 이용한 메모리 리페어 회로
US7173867B2 (en) * 2001-02-02 2007-02-06 Broadcom Corporation Memory redundancy circuit techniques
US8164362B2 (en) * 2000-02-02 2012-04-24 Broadcom Corporation Single-ended sense amplifier with sample-and-hold reference
US6433405B1 (en) * 2000-03-02 2002-08-13 Hewlett-Packard Company Integrated circuit having provisions for remote storage of chip specific operating parameters
DE10018013A1 (de) * 2000-04-11 2001-10-18 Infineon Technologies Ag Integrierte Halbleiterschaltung, insbesondere Halbleiter-speicheranordnung und Verfahren zum Betrieb derselben
US6671834B1 (en) * 2000-07-18 2003-12-30 Micron Technology, Inc. Memory redundancy with programmable non-volatile control
US6829737B1 (en) 2000-08-30 2004-12-07 Micron Technology, Inc. Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results
KR100389040B1 (ko) * 2000-10-18 2003-06-25 삼성전자주식회사 반도체 집적 회로의 퓨즈 회로
DE10063688A1 (de) 2000-12-20 2002-07-18 Infineon Technologies Ag Schaltungsanordnung zur Ansteuerung einer programmierbaren Verbindung
KR100384061B1 (ko) * 2001-02-12 2003-05-14 삼성전자주식회사 반도체 메모리 장치에 적용되는 센스 증폭기의 제로 마진인에이블 조절 장치 및 방법
US6981175B2 (en) * 2001-09-28 2005-12-27 Infineon Technologies Ag Memory and method for employing a checksum for addresses of replaced storage elements
KR100405595B1 (ko) * 2001-10-31 2003-11-14 엘지전자 주식회사 소자 퓨징 장치
KR100443508B1 (ko) * 2001-12-21 2004-08-09 주식회사 하이닉스반도체 반도체 메모리 모듈
US6603690B1 (en) * 2002-03-06 2003-08-05 International Business Machines Corporation Low-power static column redundancy scheme for semiconductor memories
US6943560B1 (en) * 2002-06-27 2005-09-13 Cypress Semiconductor Corp. Method to facilitate testing of laser fuses
US6943575B2 (en) * 2002-07-29 2005-09-13 Micron Technology, Inc. Method, circuit and system for determining burn-in reliability from wafer level burn-in
DE60222891T2 (de) * 2002-08-13 2008-07-24 Stmicroelectronics S.R.L., Agrate Brianza Nichtflüchtige Speichervorrichtung und Selbstreparatur-Verfahren
JP4048884B2 (ja) * 2002-09-10 2008-02-20 セイコーエプソン株式会社 ヒューズ回路及び表示駆動回路
US6882583B2 (en) * 2003-04-30 2005-04-19 International Business Machines Corporation Method and apparatus for implementing DRAM redundancy fuse latches using SRAM
US7145370B2 (en) * 2003-09-05 2006-12-05 Impinj, Inc. High-voltage switches in single-well CMOS processes
JP3843974B2 (ja) * 2003-09-29 2006-11-08 セイコーエプソン株式会社 表示駆動回路
US7162673B2 (en) * 2003-11-14 2007-01-09 Integrated Device Technology, Inc. Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing
US7242614B2 (en) * 2004-03-30 2007-07-10 Impinj, Inc. Rewriteable electronic fuses
US7177182B2 (en) * 2004-03-30 2007-02-13 Impinj, Inc. Rewriteable electronic fuses
US7388420B2 (en) * 2004-03-30 2008-06-17 Impinj, Inc. Rewriteable electronic fuses
US7283390B2 (en) 2004-04-21 2007-10-16 Impinj, Inc. Hybrid non-volatile memory
KR100618696B1 (ko) 2004-04-28 2006-09-08 주식회사 하이닉스반도체 인식 정보를 갖는 메모리 장치
US8111558B2 (en) * 2004-05-05 2012-02-07 Synopsys, Inc. pFET nonvolatile memory
US7257033B2 (en) * 2005-03-17 2007-08-14 Impinj, Inc. Inverter non-volatile memory cell and array system
US7679957B2 (en) * 2005-03-31 2010-03-16 Virage Logic Corporation Redundant non-volatile memory cell
JP2006331571A (ja) * 2005-05-27 2006-12-07 Matsushita Electric Ind Co Ltd 半導体装置
US7395470B2 (en) * 2005-06-09 2008-07-01 International Business Machines Corporation Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain
JP4899557B2 (ja) * 2006-03-17 2012-03-21 富士通セミコンダクター株式会社 半導体装置
US8122307B1 (en) 2006-08-15 2012-02-21 Synopsys, Inc. One time programmable memory test structures and methods
KR100800383B1 (ko) * 2006-08-18 2008-02-01 삼성전자주식회사 시프트 레지스터 및 시프트 레지스터에 전기적 퓨즈를적용하는 방법
JP5102473B2 (ja) * 2006-10-02 2012-12-19 インターナショナル・ビジネス・マシーンズ・コーポレーション 多目的ｅヒューズ・マクロのシステムおよび方法
KR20080035208A (ko) * 2006-10-18 2008-04-23 삼성전자주식회사 퓨즈 커팅 정보들을 순차적으로 출력하는 반도체 장치 및테스트 시스템
US7707466B2 (en) * 2007-02-23 2010-04-27 Freescale Semiconductor, Inc. Shared latch for memory test/repair and functional operations
US7719896B1 (en) 2007-04-24 2010-05-18 Virage Logic Corporation Configurable single bit/dual bits memory
US8041210B2 (en) * 2007-04-30 2011-10-18 Finisar Corporation Parallel high-speed communication links with redundant channel architectures
US7560965B2 (en) * 2007-04-30 2009-07-14 Freescale Semiconductor, Inc. Scannable flip-flop with non-volatile storage element and method
US7894261B1 (en) 2008-05-22 2011-02-22 Synopsys, Inc. PFET nonvolatile memory
JP5422259B2 (ja) * 2009-05-18 2014-02-19 新日本無線株式会社 トリミング回路
KR101718458B1 (ko) * 2010-11-15 2017-03-22 삼성전자 주식회사 퓨즈 어레이를 갖는 반도체 장치 및 그 동작방법
US10044371B2 (en) * 2015-08-28 2018-08-07 Qualcomm Incorporated Systems and methods for repair rate control for large erasure coded data storage
CN109147857B (zh) * 2017-06-15 2020-11-13 华邦电子股份有限公司 熔丝阵列和存储器装置
US20190250208A1 (en) * 2018-02-09 2019-08-15 Qualcomm Incorporated Apparatus and method for detecting damage to an integrated circuit
CN113436660B (zh) 2020-03-23 2022-05-24 长鑫存储技术有限公司 锁存电路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4346459A (en) * 1980-06-30 1982-08-24 Inmos Corporation Redundancy scheme for an MOS memory
JPS59210596A (ja) * 1983-05-13 1984-11-29 Hitachi Ltd 半導体記憶装置
US4853946A (en) * 1986-11-14 1989-08-01 Picker International, Inc. Diagonostic service system for CT scanners
JPH07105159B2 (ja) * 1989-11-16 1995-11-13 株式会社東芝 半導体記憶装置の冗長回路
KR940007241B1 (ko) * 1992-03-09 1994-08-10 삼성전자 주식회사 반도체 메모리 장치의 로우 리던던시장치
US5365310A (en) * 1993-07-30 1994-11-15 Xerox Corporation Remote diagnosis of copy quality defects
JP3530574B2 (ja) * 1994-05-20 2004-05-24 株式会社ルネサステクノロジ 半導体記憶装置
US5668818A (en) * 1996-08-06 1997-09-16 Hewlett-Packard Co. System and method for scan control of a programmable fuse circuit in an integrated circuit

Also Published As

Publication number Publication date
EP0805451A3 (en) 1999-03-10
EP0805451A2 (en) 1997-11-05
JP3968148B2 (ja) 2007-08-29
KR100484584B1 (ko) 2005-08-10
US5677917A (en) 1997-10-14
JPH1055698A (ja) 1998-02-24
KR970071844A (ko) 1997-11-07

Similar Documents

Publication Publication Date Title
TW328595B (en) Integrated circuit memory using fusible links in a scan chain
EP0615253A3 (en) Semiconductor memory with built-in burn-in test.
EP0602973A3 (en) Test procedure and integrated circuit architecture with mixed signals.
DE69528399D1 (de) Verbesserungen an Schmelz- und Antischmelzsicherungen für integrierte Schaltungen
DE69323681D1 (de) Stressprüfung für Speichernetzwerke in integrierten Schaltungen
TW330294B (en) Built-in self test of memory embedded in a logic circuit
DE69400884T2 (de) Fassung zum Testen von integrierten Schaltkreisen
GB2316180B (en) System and method for scan control of a programmable fuse circuit in an integrated circuit
EP0615251A3 (en) Semiconductor memory with built-in parallel bit check mode.
TW352466B (en) Apparatus and method for testing integrated circuit
IL124782A0 (en) High impedance test mode for jtag
DE68911614D1 (de) Gedächtnislegierung und Schutzvorrichtung für elektrische Stromkreise unter Verwendung dieser Legierung.
EP0706217A3 (en) Contacts with improved electromigration properties and their manufacture
EP0979417A4 (en) SINGLE STAGE TWIN FASHION TEST DEVICE FOR INTEGRATED CIRCUIT
AP9801233A0 (en) Portable fertility tester
DE69312263T2 (de) Testverfahren und -anordnung für integrierte Leistungsschaltungen
EP0310111A3 (en) Memory incorporating logic lsi and method for testing the same lsi
EP1018026A4 (en) LOAD CIRCUIT FOR TESTER FOR INTEGRATED CIRCUIT
EP0628830A3 (en) Device for reliability testing of semiconductor lasers.
DE69530110T2 (de) Auswurfvorrichtung für eine elektronische speicherkarte und dessen verwendung
ZA200100234B (en) Immunoassay testing kit and containers.
GB2285351B (en) Striker pin device for an electric fuse
EP0654672A3 (en) Test device for integrated circuits.
KR940021410U (ko) 번인(Burn-In) 테스트모드 발생회로
SG78307A1 (en) Ic test handler Ic test handler

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees