TW317635B - - Google Patents
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- Publication number
- TW317635B TW317635B TW085105205A TW85105205A TW317635B TW 317635 B TW317635 B TW 317635B TW 085105205 A TW085105205 A TW 085105205A TW 85105205 A TW85105205 A TW 85105205A TW 317635 B TW317635 B TW 317635B
- Authority
- TW
- Taiwan
- Prior art keywords
- address
- cycle
- write
- signal
- input
- Prior art date
Links
- 230000015654 memory Effects 0.000 claims description 37
- 230000000630 rising effect Effects 0.000 claims description 17
- 230000001360 synchronised effect Effects 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims 6
- 239000000872 buffer Substances 0.000 description 20
- 238000000034 method Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 14
- 230000006870 function Effects 0.000 description 9
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 3
- 230000002079 cooperative effect Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2218—Late write
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
- Memory System (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07124709A JP3102301B2 (ja) | 1995-05-24 | 1995-05-24 | 半導体記憶装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW317635B true TW317635B (enExample) | 1997-10-11 |
Family
ID=14892169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW085105205A TW317635B (enExample) | 1995-05-24 | 1996-05-01 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5761150A (enExample) |
| JP (1) | JP3102301B2 (enExample) |
| KR (6) | KR960042730A (enExample) |
| TW (1) | TW317635B (enExample) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5838631A (en) | 1996-04-19 | 1998-11-17 | Integrated Device Technology, Inc. | Fully synchronous pipelined ram |
| US6320785B1 (en) * | 1996-07-10 | 2001-11-20 | Hitachi, Ltd. | Nonvolatile semiconductor memory device and data writing method therefor |
| CN1130575C (zh) | 1997-05-16 | 2003-12-10 | 保谷株式会社 | 具有抗反射膜的塑料光学器件以及用来使抗反射膜的厚度均一的机构 |
| US6075730A (en) * | 1997-10-10 | 2000-06-13 | Rambus Incorporated | High performance cost optimized memory with delayed memory writes |
| US6115320A (en) | 1998-02-23 | 2000-09-05 | Integrated Device Technology, Inc. | Separate byte control on fully synchronous pipelined SRAM |
| JP4107716B2 (ja) * | 1998-06-16 | 2008-06-25 | 株式会社ルネサステクノロジ | Ｆｉｆｏ型記憶装置 |
| KR100270959B1 (ko) * | 1998-07-07 | 2000-11-01 | 윤종용 | 반도체 메모리 장치 |
| KR100283470B1 (ko) * | 1998-12-09 | 2001-03-02 | 윤종용 | 반도체 메모리 장치의 어드레스 발생회로 |
| US7069406B2 (en) * | 1999-07-02 | 2006-06-27 | Integrated Device Technology, Inc. | Double data rate synchronous SRAM with 100% bus utilization |
| TW522399B (en) * | 1999-12-08 | 2003-03-01 | Hitachi Ltd | Semiconductor device |
| US6501698B1 (en) * | 2000-11-01 | 2002-12-31 | Enhanced Memory Systems, Inc. | Structure and method for hiding DRAM cycle time behind a burst access |
| US7403446B1 (en) * | 2005-09-27 | 2008-07-22 | Cypress Semiconductor Corporation | Single late-write for standard synchronous SRAMs |
| WO2008002645A2 (en) * | 2006-06-28 | 2008-01-03 | Cypress Semiconductor Corporation | Memory device and method for selective write based on input data value |
| KR101033464B1 (ko) | 2008-12-22 | 2011-05-09 | 주식회사 하이닉스반도체 | 반도체 집적 회로 |
| US8644088B2 (en) | 2010-10-28 | 2014-02-04 | Hynix Semiconductor Inc. | Semiconductor memory device and semiconductor system including the same |
| US20180189374A1 (en) * | 2016-12-30 | 2018-07-05 | Arrow Devices Private Limited | System and method for fast reading of signal databases |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5172379A (en) * | 1989-02-24 | 1992-12-15 | Data General Corporation | High performance memory system |
| US5258952A (en) * | 1990-12-14 | 1993-11-02 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with separate time-out control for read and write operations |
| JP3179788B2 (ja) * | 1991-01-17 | 2001-06-25 | 三菱電機株式会社 | 半導体記憶装置 |
| US5587961A (en) * | 1996-02-16 | 1996-12-24 | Micron Technology, Inc. | Synchronous memory allowing early read command in write to read transitions |
| JP2005007598A (ja) * | 2003-06-16 | 2005-01-13 | Aoki Technical Laboratory Inc | 細口筒状容器の射出延伸ブロー成形方法及び容器 |
-
1995
- 1995-05-24 JP JP07124709A patent/JP3102301B2/ja not_active Expired - Lifetime
-
1996
- 1996-05-01 TW TW085105205A patent/TW317635B/zh not_active IP Right Cessation
- 1996-05-21 US US08/651,873 patent/US5761150A/en not_active Expired - Lifetime
- 1996-05-23 KR KR1019960017604A patent/KR960042730A/ko not_active Abandoned
-
2004
- 2004-12-23 KR KR1020040111063A patent/KR100574108B1/ko not_active Expired - Lifetime
-
2005
- 2005-10-17 KR KR1020050097447A patent/KR100694440B1/ko not_active Expired - Lifetime
- 2005-10-17 KR KR1020050097450A patent/KR100783049B1/ko not_active Expired - Fee Related
-
2007
- 2007-06-08 KR KR1020070056051A patent/KR100915554B1/ko not_active Expired - Lifetime
-
2009
- 2009-01-28 KR KR1020090006544A patent/KR100945968B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08321180A (ja) | 1996-12-03 |
| KR20090028585A (ko) | 2009-03-18 |
| KR100694440B1 (ko) | 2007-03-12 |
| KR960042730A (ko) | 1996-12-21 |
| US5761150A (en) | 1998-06-02 |
| KR20070108293A (ko) | 2007-11-09 |
| KR100574108B1 (ko) | 2006-04-26 |
| KR100783049B1 (ko) | 2007-12-07 |
| KR20070108331A (ko) | 2007-11-09 |
| KR100945968B1 (ko) | 2010-03-09 |
| JP3102301B2 (ja) | 2000-10-23 |
| KR100915554B1 (ko) | 2009-09-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |