JP3102301B2 - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JP3102301B2
JP3102301B2 JP07124709A JP12470995A JP3102301B2 JP 3102301 B2 JP3102301 B2 JP 3102301B2 JP 07124709 A JP07124709 A JP 07124709A JP 12470995 A JP12470995 A JP 12470995A JP 3102301 B2 JP3102301 B2 JP 3102301B2
Authority
JP
Japan
Prior art keywords
address
write
register
cycle
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP07124709A
Other languages
English (en)
Japanese (ja)
Other versions
JPH08321180A (ja
Inventor
正剛 行武
欽哉 光本
隆志 秋岡
▲将▼弘 岩村
秋山　　登
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP07124709A priority Critical patent/JP3102301B2/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to TW085105205A priority patent/TW317635B/zh
Priority to US08/651,873 priority patent/US5761150A/en
Priority to KR1019960017604A priority patent/KR960042730A/ko
Publication of JPH08321180A publication Critical patent/JPH08321180A/ja
Application granted granted Critical
Publication of JP3102301B2 publication Critical patent/JP3102301B2/ja
Priority to KR1020040111063A priority patent/KR100574108B1/ko
Priority to KR1020050097450A priority patent/KR100783049B1/ko
Priority to KR1020050097447A priority patent/KR100694440B1/ko
Priority to KR1020070056051A priority patent/KR100915554B1/ko
Priority to KR1020090006544A priority patent/KR100945968B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2218—Late write

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP07124709A 1995-05-24 1995-05-24 半導体記憶装置 Expired - Lifetime JP3102301B2 (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP07124709A JP3102301B2 (ja) 1995-05-24 1995-05-24 半導体記憶装置
TW085105205A TW317635B (enExample) 1995-05-24 1996-05-01
US08/651,873 US5761150A (en) 1995-05-24 1996-05-21 Synchronous memory with pipelined write operation
KR1019960017604A KR960042730A (ko) 1995-05-24 1996-05-23 반도체기억장치
KR1020040111063A KR100574108B1 (ko) 1995-05-24 2004-12-23 반도체기억장치
KR1020050097447A KR100694440B1 (ko) 1995-05-24 2005-10-17 반도체기억장치
KR1020050097450A KR100783049B1 (ko) 1995-05-24 2005-10-17 반도체기억장치
KR1020070056051A KR100915554B1 (ko) 1995-05-24 2007-06-08 반도체기억장치
KR1020090006544A KR100945968B1 (ko) 1995-05-24 2009-01-28 반도체기억장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07124709A JP3102301B2 (ja) 1995-05-24 1995-05-24 半導体記憶装置

Publications (2)

Publication Number Publication Date
JPH08321180A JPH08321180A (ja) 1996-12-03
JP3102301B2 true JP3102301B2 (ja) 2000-10-23

Family

ID=14892169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07124709A Expired - Lifetime JP3102301B2 (ja) 1995-05-24 1995-05-24 半導体記憶装置

Country Status (4)

Country Link
US (1) US5761150A (enExample)
JP (1) JP3102301B2 (enExample)
KR (6) KR960042730A (enExample)
TW (1) TW317635B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6250758B1 (en) 1997-05-16 2001-06-26 Hoya Corporation Plastic optical devices having antireflection film and mechanism for equalizing thickness of antireflection film

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US6320785B1 (en) * 1996-07-10 2001-11-20 Hitachi, Ltd. Nonvolatile semiconductor memory device and data writing method therefor
US6075730A (en) * 1997-10-10 2000-06-13 Rambus Incorporated High performance cost optimized memory with delayed memory writes
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
JP4107716B2 (ja) * 1998-06-16 2008-06-25 株式会社ルネサステクノロジ Ｆｉｆｏ型記憶装置
KR100270959B1 (ko) * 1998-07-07 2000-11-01 윤종용 반도체 메모리 장치
KR100283470B1 (ko) * 1998-12-09 2001-03-02 윤종용 반도체 메모리 장치의 어드레스 발생회로
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
TW522399B (en) * 1999-12-08 2003-03-01 Hitachi Ltd Semiconductor device
US6501698B1 (en) * 2000-11-01 2002-12-31 Enhanced Memory Systems, Inc. Structure and method for hiding DRAM cycle time behind a burst access
US7403446B1 (en) * 2005-09-27 2008-07-22 Cypress Semiconductor Corporation Single late-write for standard synchronous SRAMs
WO2008002645A2 (en) * 2006-06-28 2008-01-03 Cypress Semiconductor Corporation Memory device and method for selective write based on input data value
KR101033464B1 (ko) 2008-12-22 2011-05-09 주식회사 하이닉스반도체 반도체 집적 회로
US8644088B2 (en) 2010-10-28 2014-02-04 Hynix Semiconductor Inc. Semiconductor memory device and semiconductor system including the same
US20180189374A1 (en) * 2016-12-30 2018-07-05 Arrow Devices Private Limited System and method for fast reading of signal databases

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172379A (en) * 1989-02-24 1992-12-15 Data General Corporation High performance memory system
US5258952A (en) * 1990-12-14 1993-11-02 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with separate time-out control for read and write operations
JP3179788B2 (ja) * 1991-01-17 2001-06-25 三菱電機株式会社 半導体記憶装置
US5587961A (en) * 1996-02-16 1996-12-24 Micron Technology, Inc. Synchronous memory allowing early read command in write to read transitions
JP2005007598A (ja) * 2003-06-16 2005-01-13 Aoki Technical Laboratory Inc 細口筒状容器の射出延伸ブロー成形方法及び容器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6250758B1 (en) 1997-05-16 2001-06-26 Hoya Corporation Plastic optical devices having antireflection film and mechanism for equalizing thickness of antireflection film

Also Published As

Publication number Publication date
JPH08321180A (ja) 1996-12-03
KR20090028585A (ko) 2009-03-18
TW317635B (enExample) 1997-10-11
KR100694440B1 (ko) 2007-03-12
KR960042730A (ko) 1996-12-21
US5761150A (en) 1998-06-02
KR20070108293A (ko) 2007-11-09
KR100574108B1 (ko) 2006-04-26
KR100783049B1 (ko) 2007-12-07
KR20070108331A (ko) 2007-11-09
KR100945968B1 (ko) 2010-03-09
KR100915554B1 (ko) 2009-09-03

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