TW302502B - - Google Patents

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Publication number
TW302502B
TW302502B TW085101777A TW85101777A TW302502B TW 302502 B TW302502 B TW 302502B TW 085101777 A TW085101777 A TW 085101777A TW 85101777 A TW85101777 A TW 85101777A TW 302502 B TW302502 B TW 302502B
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Taiwan
Prior art keywords
etching
wafer
item
patent application
crystal
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TW085101777A
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English (en)
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Siemens Ag
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • ing And Chemical Polishing (AREA)
  • Weting (AREA)

Description

經濟部中央標準局負工消費合作社印裝 SQ2502 A7 B7五、發明説明（'） 本發明僳閧於在晶圓形式之半導體基板上製造高密度 積體電路之方法，其中晶圓受琢磨而變薄，以便可以切成 各別之晶片，由於琢磨過程在晶圖背面所造成之損傷區 域可再利用一種於受保護之晶圓正面上進行且在切割之 前即已進行之蝕刻而加以消除。 具有半導體組件之矽晶圓製造過程結束之後，晶圓将受 琢磨而變薄以便可切割成各別之晶片。此種琢磨過程在 晶圓背面精煉的裂缝上覆上一受干擾而處在欠張力狀況 之矽表面。若此晶圓琢磨得很薄（例如，用於晶片卡時< 2 0 0 u m ),則其可隨後藉切割而斷開或切割後因此亦很容 易折斷。干擾和張力在這裡亦具有作用，它們是由切鋸 本身在切割邊緣上産生。 為了防止不受控制且提早之斷開，晶圓背面迄今為止 一般均在數微米之濕蝕刻中進行清除，故此張力可去除 由此所造成之損傷區域。晶圓正面一般則受到厚（大約 l〇〇um)箔層之保護，箔層在晶圓邊緣必須^全不透水，使 在塗上箔層之前不需要在晶圓上另外再塗漆，否則就必 須預先另外塗漆以便在濕蝕刻中防止邊綠晶片之損顔。 但這些方法有一些重大的缺點：在背面濕蝕刻之後，化 學藥劑必須再被沖洗且晶圓須以旋轉脱水之方式使其乾 燥，這在琢磨變薄後之晶圓上會導致晶圓斷裂，此外，由 於環境保護之原因，濕化學法應盡可能避免。為了去除 切割邊綠上之張力及干擾，直到現在仍無方法可行，此乃 因濕化學之矽蝕刻藥劑亦會損傷未受保護之鋁墊（pad)。 (請先閱讀背面之注意事項再填寫本頁) .丄 、-° 本紙張又度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 修正 補充 五、發明説明（> ) 本發明之目的為提供本文開頭所述技g之方法以改進 上述之缺點β 此目的將藉開頭所述技藝之方法而得以逹成，即，此種蝕 刻使用蝕刻氣體中之氟化物以進行微波電漿蝕刻或高頻 激發之下游《漿蝕刻法。 本發明之進一步構造敘述在申誚專利範園各附屬項中。 本發明随後將依據實施例及唯一的圔式作詳細說明。 /圈式簡單說明如下： ‘ \J 画1在連接方式和切面上潁示一種單一晶國之蝕刻設 備以進行本發明之方法。 侬據本發明之方法，其有利之處為：以現有之霣漿蝕刻 設備，例如，Tokuda CDE7,CDE8或 Gasonics IPC即可進行 蝕刻。此外，此種新方法較便宜且對琛境有利，在有關晶 國之機械負載方面，此種新方法具有較濕化學蝕刻更不 會損傷的處理方式。 此處重要之點可明顯的由該圖（撤波方式）得知：若晶 圓正面受到箔層保護，則晶國以其面朝下之傳統方式输 送且由上受到蝕刻。當然此蝕刻装蘆是有優點的，此受 琢磨而變薄之晶圖可在其上小心地作機械上之處理，例 如其情形可能為：當拄刻設備設計成引導設備且在引入 室中此完好之支架慢慢被抽出或受到通風時，另一支架 卻在工作。 為了在晶圓背面進行矽蝕刻，有各種不同之撤波或高 頻霣漿程序以供使用，這卽可利用化學劑c f4./o2完成，亦 可利用N F 3或S F6 / 02/ N2 ( 4 0 )完成直到現在為止，绾是必 1用中國國家標準（€泌）八4規格（210/297公茇） —.--------裝------訂------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央橾準局員工消費合 經濟部中央標準局員工消費合作社印製 SQ25Q2 A7 B7五、發明説明（々） 須由多値切割開始，使電漿蝕刻方法不會由於長的蝕刻 時間而顯現不經濟性。由於本發明之蝕刻最好是在受損 傷之位置進行或沿箸應力線進行，逭和濕蝕刻不同，因此 只需很短的蝕刻時間（依據琢磨方法和蝕刻化學劑之不 同，此時間在10秒和4分鐘之間相當於大約2Q0U1D之切割） 以便吸收由晶圓或切割邊綠來之應力，前者使自身經由 測量晶圖之彎曲而受控制，一種受控制之過度蝕刻（over-etching) 最後 可修補 張力在 其端點 産生之 撕裂， 這樣可 達到所需之斷裂強度。 在化學下游蝕刻中，其以已知方式利用電漿産生室之分 割和探針以引導晶圓不會受電場或離子影键，卽實際上 産生一種純粹之化學蝕刻，以此種方式則晶圖不需另外 之正面塗漆以保護邊綠組件。對蝕刻氣體而言，若基於 箔層之防護問題而可使用正面塗漆，則在上述之短暫蝕 刻時間中，在墊（pad)中之鋁根本就不會受損傷且由於高 的f擇性，厚的氣化物/氮化物保護層只€撤受損傷。基 於同樣理由，在未受保護之晶片表面的切割邊緣亦以上 述方法進行蝕刻而受損傷。 若完全不在正面塗上箔層，則此方法亦可找出使用方式 以保護正面，這描述在德國專利申請案號P4405667.2中， 該案號包含在所掲示之各案件中，其中正面保護基本上 是利用其上流動之中性氣體而産生，此種中性氣體可防 止蝕刻氣體之粒子向前推進。 -5 - ---------f .衣------訂------i I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0>< 297公釐）

Claims (1)

  1. 302502 AS B8 C8 D8 六、申請專利範圍 ι· 一種在晶國形式之半導醱基板上製造高密度積體電路 之方法，晶圖在基板上受琢磨而變薄，以便能切斷成各 別之晶κ，在晶圓背面上由於琢磨過程所造成之損傷 區域可再利用在受保護之晶圓正面上進行之切斷之前 即已進行的蝕刻來加以去除，其特擻為， 此種蝕刻埭用蝕刻氣體中之氟化物以進行橄波霣漿蝕刻或 高頻激發之下游電漿蝕刻法。 2. 如申請專利範圍第1項之方法，其中晶圓正面俗利用其 上流動之中性氣體而受到保護》 3. 如申請專利範圍第1或第2項之方法，其中進行蝕刻直 至晶圆之切割邊緣為止。 4. 如申請專利範圍第1或第2項之方法，其中遘取蝕刻時 間使其介於1 〇秒和4分鐘之間。 5. 如申請專利範園第3項之方法，其中選取蝕刻時間使其 介於1 0秒和4分鐘之間。 (請先閱讀背面之注意事項再填寫本頁) 丄 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS〉Α4規格（210Χ2ς»7公釐）
TW085101777A 1995-02-21 1996-02-13 TW302502B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19505906A DE19505906A1 (de) 1995-02-21 1995-02-21 Verfahren zum Damage-Ätzen der Rückseite einer Halbleiterscheibe bei geschützter Scheibenvorderseite

Publications (1)

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TW302502B true TW302502B (zh) 1997-04-11

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TW085101777A TW302502B (zh) 1995-02-21 1996-02-13

Country Status (7)

Country Link
US (1) US5693182A (zh)
EP (1) EP0729176B1 (zh)
JP (1) JPH08250456A (zh)
KR (1) KR100424421B1 (zh)
AT (1) ATE217119T1 (zh)
DE (2) DE19505906A1 (zh)
TW (1) TW302502B (zh)

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Also Published As

Publication number Publication date
EP0729176B1 (de) 2002-05-02
EP0729176A2 (de) 1996-08-28
DE59609139D1 (de) 2002-06-06
DE19505906A1 (de) 1996-08-22
KR960032631A (ko) 1996-09-17
KR100424421B1 (ko) 2004-06-05
EP0729176A3 (de) 1997-11-12
US5693182A (en) 1997-12-02
JPH08250456A (ja) 1996-09-27
ATE217119T1 (de) 2002-05-15

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