KR960032631A - 기판의 앞면을 보호하면서 반도체 기판의 후면을 데미지 에칭하는 방법 - Google Patents

기판의 앞면을 보호하면서 반도체 기판의 후면을 데미지 에칭하는 방법 Download PDF

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KR960032631A
KR960032631A KR1019960004025A KR19960004025A KR960032631A KR 960032631 A KR960032631 A KR 960032631A KR 1019960004025 A KR1019960004025 A KR 1019960004025A KR 19960004025 A KR19960004025 A KR 19960004025A KR 960032631 A KR960032631 A KR 960032631A
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substrate
etching
front surface
protected
protecting
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KR1019960004025A
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KR100424421B1 (ko
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요제프 마투니
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알베르트 발도르프 · 롤프 옴케
지멘스 악티엔게젤샤프트
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

개별 칩으로 절삭하기 전에, 에칭가스에 플루오르 화합물을 사용하면서 마이크로파 또는 고주파 여기된 다운스트림 플라즈마 에칭방법으로서 얇게 연삭된 기판의 데미지 에칭을 수행한다. 이로 인해 연삭된 후면에서 뿐만 아니라 절삭에지에서의 스트레스 및 장애가 제거될 수 있다.

Description

기판의 앞면을 보호하면서 반도체 기판의 후면을 데미지 에칭하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 방법을 실시하는데 적합한 개별 기판 에칭 장치의 개략적인 단면도.

Claims (4)

  1. 개별 칩으로 절삭하기 위해서, 기판을 얇게 연삭하고, 연삭 공정에서 야기된 기판 후면상의 데미지 구역을 기판 앞면을 보호하면서 절삭 전에 에칭함으로써 다시 제거하는 방식으로 구성된, 디스크형 반도체 기판상에 고집적 회로를 만드는 방법에 있어서, 에칭가스에 플루오르 화합물을 사용하면서 마이크로파 또는 고주파 여기된 다운 스트림 플라즈마 에칭방법으로서 에칭을 수행하는 것을 특징으로 하는 기판의 앞면을 보호하면서 반도체 기판의 후면을 데미지 에칭하는 방법.
  2. 제1항에 있어서, 기판 앞면이 그 위로 흐르는 천연가스에 의해 보호되는 것을 특징으로 하는 기판의 앞면을 보호하면서 반도체 기판의 후면을 데미지 에칭하는 방법.
  3. 제1항 또는 2항에 있어서, 에칭이 기판의 절삭에지내로 까지 이루어지는 것을 특징으로 하는 기판의 앞면을 보호하면서 반도체 기판의 후면을 데미지 에칭하는 방법.
  4. 제1항 내지 3항 중 어느 한 항에 있어서, 에칭시간이 10초 내지 4분 사이로 선택되는 것을 특징으로 하는 기판의 앞면을 보호하면서 반도체 기판의 후면을 데미지 에칭하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960004025A 1995-02-21 1996-02-21 기판의앞면을보호하면서반도체기판의후면을데미지에칭하는방법 KR100424421B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19505906A DE19505906A1 (de) 1995-02-21 1995-02-21 Verfahren zum Damage-Ätzen der Rückseite einer Halbleiterscheibe bei geschützter Scheibenvorderseite
DEP19505906.9 1995-02-21

Publications (2)

Publication Number Publication Date
KR960032631A true KR960032631A (ko) 1996-09-17
KR100424421B1 KR100424421B1 (ko) 2004-06-05

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KR1019960004025A KR100424421B1 (ko) 1995-02-21 1996-02-21 기판의앞면을보호하면서반도체기판의후면을데미지에칭하는방법

Country Status (7)

Country Link
US (1) US5693182A (ko)
EP (1) EP0729176B1 (ko)
JP (1) JPH08250456A (ko)
KR (1) KR100424421B1 (ko)
AT (1) ATE217119T1 (ko)
DE (2) DE19505906A1 (ko)
TW (1) TW302502B (ko)

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Also Published As

Publication number Publication date
EP0729176A2 (de) 1996-08-28
EP0729176B1 (de) 2002-05-02
KR100424421B1 (ko) 2004-06-05
DE19505906A1 (de) 1996-08-22
TW302502B (ko) 1997-04-11
DE59609139D1 (de) 2002-06-06
JPH08250456A (ja) 1996-09-27
US5693182A (en) 1997-12-02
ATE217119T1 (de) 2002-05-15
EP0729176A3 (de) 1997-11-12

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