TW296470B - - Google Patents

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Publication number
TW296470B
TW296470B TW084105789A TW84105789A TW296470B TW 296470 B TW296470 B TW 296470B TW 084105789 A TW084105789 A TW 084105789A TW 84105789 A TW84105789 A TW 84105789A TW 296470 B TW296470 B TW 296470B
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TW
Taiwan
Prior art keywords
porous dielectric
layer
porous
patent application
conductor
Prior art date
Application number
TW084105789A
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English (en)
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Texas Instruments Inc
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Publication of TW296470B publication Critical patent/TW296470B/zh

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    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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    • Y10S148/118—Oxide films

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A7 ____ B7 五、發明説明（ΤΪ ~~~~〜S- C發明領域〕 本發明大體上有關於半導饉裝置上電介質之製造，且更 特别有關於使用由多孔電介質材料形成之電氣絶緣體以減 少半導體裝置上電容性耦合之方法及結構。 (發明背景〕 半導體廣泛使用於黨子裝置例如電腦及電視之積雅電路 中。此等積體電路典型地在單一矽晶片上組合許多電晶難 以實施複雜之功能並儲存资料。半導體及電子裝置製造者 以及最终使用者意欲積體電路能在較小封裝中以較少時間 完成較多操作，而消耗較少功率。然而，諸多此等需求彼 此對立。例如，僅缩小特定電路尺寸由0 5微米至0 25微 米’會增加功率消耗30%。類似地，操作連度加倍大雅上 將功率消耗加倍。縮小化大體上亦於攜帶信號通過晶片之 導禮間造成增加之電容性耦合或串擾（crosstalk)。此作 用不但限制可達成之速度且降低用於確保正常裝置操作之 雜訊界限。 一種減少功率消耗及串擾作用之方式係•減少分隔導嫌之 绝緣體或電介質之介電常數。最普遍之半導體電介質大概 係二氧化矽，其介電常數大約爲3.9。相較於此，空氣（ 經濟部中央標準局貝工消費合作社印製 I I 装 訂 ί請先閲讀背面之注意事項再填寫本頁j 包含部分眞空）之介電常數稍微超過1.0。因此，已發展 出許多電容減少技術’以至少部分以空氣取代固雅電介質 〇 1991年1月22日頒予Kaanta等人之美國專利第4 987 1〇1 號描述一種製造氣體（空氣 > 電介質之方法，其包含：沉 本紙張尺度適用中國國家橾準（CMS ) A4規格（210X297公釐） A7 A7 經濟部中央標準局負工消費合作社印裝 B7 ................ 五、發明説明（2 ) 積可移除付料之臨時層於支持物（例如導雜）之間，以封 蓋之絶緣層覆蓋此臨時層，於封蓋中開啓出入孔，經由此 等出入孔取出可移除材料，然後封閉出入孔。此方法不方 便，部分a爲其須於設計規則中考慮出入孔位置且於電路 設計期間考慮對準誤差預估，並須额外處理步樣，以產生 且接著封塞諸孔。此方法亦會產生大量無償值之區域，其 本質上無益於處理機械應力與熱散逸。 1992年4月7曰頒予Sakamoto之美國專利第5,1〇3,288號 描述一種多層接線結構，其藉由使用50%至80%有孔率（有 孔率係空心結構之百分比〉及大約5毫微米（nm)至50毫微 米之微孔尺寸之有孔電介質以減少電容。此結構典型地係 如下形成：沉積酸性氧化物與基本氧化物之混合物，以熱 處理將基本氧化物沉澱，然後將基本氧化物溶解除去。將 此結構所有基本氧化物除去可能有問題，因爲浸濾 (leaching)劑可能無法達到小凹處之基本氧化物。再者， 所描述之於基本氧化物（含有鈉及鋰）中使用之數個元素 大體上於半導體產業中被視爲污染物，且’因此通常於生產 環境中予以避免。使用此方法僅產生極小之微孔（小於10 毫微米）係困難者，但此要件於次微米製程繼績朝向十分 之一微米或更小尺十餘】時仍然存在。 另一種於半導體基底（此處使用之名詞"基底"係廣義地 含有任何於所欲之導體/絶緣體層之前形成之層）上形成 多孔電介質薄膜之方法，係於1987年3月24日頒予Br inker 等人之美國專利第4,652,467號中描述。此專利揭露一種 本紙張尺度適用巾國國家辟（CNS) A4規格（21Gx 297公羡） (請先聞讀背面之注意事項再填寫本頁) 袈- 訂 經濟部中央標準局員工消費合作社印裝 ' " A7 _B7 五、發明説明（3 ) 溶膠凝膠（sol-gel)技術，用以沉積具有控制之有孔率及 微孔尺寸（直徑〉之多孔薄膜，其中將溶液沉積在基底r上 ，予以凝膠化，然後經由蒸發除去溶劑予以交聨並稠密化 (densified)，從而留下多孔電介質。此方法以薄膜之拥 密化作爲主要目標，其揭露者遠離低介電常數之應用。由 此方法形成之電介質典型係15¾至50%有孔率，於乾燥期間 具有至少20¾之永久薄膜厚度減少。較高之有孔率（例如 40-50%)僅能於微孔尺寸大體上對於微電路應用係太大者 處達成。此等材料通常稱爲乾凝膝（xerogel)，儘管最终 結構並非凝膠，而係固醴材料之開放孔（此等孔大體上係 交連者，而非隔離者）多孔結構。 〔發明概要〕 本發明提供用作爲半導體绝緣體之混合多孔/非多孔電 介質之新穎結構及方法。此結構將低介電常數（ί[大禮上 小於3.0且較佳小於2.0)多孔材料與非多孔電介質材料結 合，使能增強上述兩者所欲之特點，作爲在形成於半導雜 裝置上諸導體間減少非所欲電容之主要目’的。此處所認知 之問題之一係不易製造具有於多孔層之後形成之有效結構 之裝置。利用本發明方法，值管多個多孔層係可能者，而 此裝置之構造可由順序成層技術完成。 此處所認知之多孔電介質之其他問題含有：相較於固雜 二氧化矽爲減少之機械強度及熱傳導性；通道形成典型須 求之異向性（方向性〉蝕刻之困難；於多孔層頂部形成樣 式化層之困難；諸多微孔（且尤其矽石（silica))電介質 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） ^^1 I mt 1^1 ^^^1 ! I ί Ι— m n ^^^1 n^i. « < - 夺 、-* (請先閲讀背面之注意事項再填寫本頁} 經濟部中央標準局員工消费合作社印製 2^6470 at Β7 五、發明説明（4 ) 之親水性（需水性）本質；以及習知多孔電介質形成方法 大禮上不適於實際之次微米裝置構造。此處揭示之方法_及 結構可解決該等及其他問題。 本發明提供一種構建半導體裝置之方法，其主要目的係 減少形成在該裝置上諸導體間之非所欲之電容。因此，該 方法包含：提供一層形成在半導體基底上之樣式化導體， 以及形成多孔電介質層填滿樣式化導體間之間隙並覆芨樣 式化之導體。該方法復包含：移除多孔電介質層之一頂部 部分，以露出至少該導體之頂部。該方法又包含：沉積非 多孔電介質層，覆蓋導體及多孔層。此非多孔層較佳係由 以例如化學氣相沉積或一些其他非液體技術一致形成之底 部次層以及以旋轉附著（spin-〇n)之玻璃或類似平面化技 術形成之頂部次層所組成。該方法復包含形成一或多個填 充金屬之通道貫穿非多孔層，以提供電氣接觸至樣式化之 導體，且在此結構頂部上形成第二導體層。 本發明亦提供具有減少之層内電容之用於半導體裝置之 結構，包含至少第一及第二導雜，形成在•.半導雜基底上， 以及多孔電介質在第-及第二導體間。此多孔電介質較佳 具有導想高度之7G%至聽之平均高度。此多孔電介質較 佳亦具有小於80毫微米（nm)(更佳爲介於2毫微米與烈毫 微米之間）之平均微孔直徨。此多孔電介質較佳亦具有介 於30%與95¾之間（更佳爲介於5〇%與75%之間）之有孔率。 步包含非多孔電介質層其沉積在導雜與多孔 電介質之頂部上，且於導體上測量時較佳係導體高度之至 ^^^1 m In mmn n ^^1 I ^i— n (請先閲讀背面之注意事項再填寫本頁) 6 ~
A7 B7 五、發明説明（5 ) 少 50%。 〔圖式簡述〕 本發明之各種特徵及優點可參考下列圖式而能徹底瞭解 ，其中： 圖1顯示本發明之一典型實施例之諸步驟方塊圖； 圖2A-2D顯示塡充溶劑之孔在溶劑蒸發之前及溶劑蒸發 期間之剖面圖； 圖3A-3D顯示一半導體裝置一部分之剖面圖，描繪本發 明之一實施例應用至典型裝置之數步驟； 圖4A-4C顯示另一半導體裝置之剖面圖，描繪本發明之 兩個個别應用； 圖5顯示依本發明方法形成之另一結構之剖面圖，其具 有相當厚之多孔電介質以及相當薄之非多孔電介質； 圖6A-6H顯示具有由兩個次層形成非多孔電介質之又一 半導體裝置之剖面圖； 圖7顯示含有鈍化層以避免多孔電介質層直接接觸導體 之半導體裝置之剖面圖；以及 1 圖8A-8D顯示以電介質分隔物附於導體頂部之半導體裝 置之剖面圖。 經濟部中央標準局員工消費合作社印製 ---：---：----^ 裝— (請先閱讀背面之注意事項再填寫本頁) 〔較佳實施例詳細説明〕 本發明之典型實施例係以圖1中顯示之步驟組成之多孔 電介質方法予以描述，但並非所有顯示之步驟於一特定實 施例中係需求者。又，於數個步驟中之材料可予以替換， 以達成各種效果，且處理參數例如時間、溫度、壓力以及 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29*7公釐） 經濟部中央標準局員工消费合作社印製 A7 _______B7 五、發明説明（6 ) 有關成分之濃度可具有寬廣之變化範固。總之，產生類似 多孔層之另一方法可取代圈i之方法。於圈i中，各種前 導體（precursor)溶液（其中一些在特定實例中詳細描述 )可予以混合，然後施加至基底上，該基底上已形成—層 樣式化導體。此施加方法可爲例如在限制溶劑蒸發之控制 環境中之旋轉附著技術。在至少一實施例中此施加之目的 係形成一層前導物，其至少實質填滿相鄰導體間之空隙。 此前導物溶液在基底上予以凝膠化，此處理典型須1分鐘-至12小時’依據凝膠化之溶液及方法而定。濕凝膠可随時 間而老化（age)，通常大約一夭（雖可能短得多），在—或 多個控制之溫度下。若此濕凝膠含有水，可使用一或多個 洗滌步驟以於凝膠上實施溶劑交換，從而除去水但留下濕 態之凝膠。溶劑可爲質子性（protic)(例如乙醇）或非質 子性（aprotic)(例如丙鲷或己烷）溶劑。然後，以一種 方法例如將此結構沉浸在含有表面修飾劑與可溶解修飾劑 之溶劑之混合物中，使濕凝膠與表面修飾劑（其作用將於 下文解釋）反應。此溶劑亦須與已存在於濕凝膠中之溶劑 互溶（miscible)。接著，可使用另一溶劑交換以自此結構 除去多餘之表面修飾劑。此溶劑可自凝膠中蒸發，留下多 孔電介質結構。如薄膜於乾燥期間實質上未稠密化，則乾 燥之凝膠本質上呈現與濕凝膠相同之結構（乾燥之薄膜厚 度實質上輿濕凝膠薄膜厚度相同）。最後，此多孔電介質 可@以一非多孔絶緣層及蓋，如^實例中描述者。 參考圖2A，其顯示濕凝膠結構10中單一微孔12之剖面圖 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） --------- 袈！ . - (請先閱讀背面之注意事項再填寫本頁) -訂 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（7 ) ，以液禮微孔流體14填滿微孔12。H2B顯示相同之微孔進 行微孔流體之蒸發。以彎月面（meniscus) 18之形成描緣·相 位變化（自液體至蒸氣），其顯示於蒸發期間在液體微孔 流禮14與蒸氣16之間形成新月形狀（crescent-shaped)之 界限。此彎月面係指示微孔流雜之表面張力在微孔壁上產 生向内（通常，雖一些流體會向外>|力。此毛細管壓力 P係有關於微孔流體表面張力Ts、接觸角度q(流體弯月 面接觸微孔表面之角度）以及微孔半徑*/，其方程式爲 2TjC〇sfl 自此方程式可顯然易知於乾燥期間保持極小微孔（小7 )之 困難，因爲每當半徑7減半，微孔壁上壓力會加倍。不幸 地，適於諸導髏間使用之多孔電介質必須含有至少小於導 鱧間間隙之尺寸等級之微孔（例如，就〇.2微米間除而言 ，*/大約爲10毫微米）。因此，增加微孔尺寸以減輊毛細 管壓力於微電子應用中受到限制◊另一方面，僅使微孔因 毛細管壓力而崩潰即造成過度之收缩，且•電介質相對應稠 密化，因而無法達成此方法之主要目的（減少介電常數） 並坊礙良好表面黏著。 爲克服單片乾凝膠合成中之毛細管壓力問題，已發展出 氣凝膠技術。大體上，乾凝膠技術之變化在超臨界壓力及 溫度條件下除去濕凝膠之溶劑。藉由在超臨界區域中除去 溶劑’液體溶劑之蒸發不會發生；取而代之者，於實施期 間流體密度固定地變化，自壓縮之液體變化爲過熱之蒸氣 本紙張尺度適用中國國家橾準（CNS〉A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. 0) p 、11 A7 B7 五 經濟部中央標隼局員工消費合作社印製 發明説明（8 ) (請先閲讀背面之注意事項再填寫本頁) ，無可資區别之狀態界限。此技術徹底避免毛細管恩力問 題’因爲微孔中不曾存在狀態變化界限。將氣凝膠技術應 用於半導體製造似乎成問題且昂贵；典型可使用之溶劑具 有高臨界壓力（例如乙酵，924镑/平方叶（psi)，二氧化 破1071 psi)，此使得大部分環境中之應用爲困難者。例 如’此等壓力會傾向於壓碎先前在大氣壓力下覆蓋之多孔 電介質層或者迫使濕凝膠進入剩下未覆蓋之先前多孔電介 質層之微孔中，且須在晶圓之邊緣抑制濕凝膠，以防止凝 膠在乾燥之前被擠出晶圓。然而，在一些條件下可依此方 法形成高度多孔之微孔電介質結構，使得此超臨界技術可 能用於實施本發明。 作爲上述之替代者，本發明含有一些新穎技術，其可在 真空至接近臨界壓力之範固下實施，以大氣壓力爲較佳者 ’因易於處理且與先前之多孔層相容。此等技術中一類似 處係在濕凝膠上實施表面修飾步驟，以另一種類分子取代 微孔壁上相當數目之分子。此表面修飾典型以較穩定之表 面群例如甲基群取代活性表面群例如經基’及烷氧基，從而 於凝银乾燥期間可控制非所欲之縮合反應（及收縮作用） 。圖2C顯示於表面修飾步驟後一微孔之剖面圈；凝膠1〇在 微孔12表面上之部分（標示爲區域2〇)現含有不同之種類 。吾人已發現，於表面修飾期間控制被取代之活性表面群 之百分比可將最終收縮自典型之未修飾之乾凝膠之大收缩 (未控制之收縮）調整至僅數個百分比之收縮，目前爲止 僅以氣凝膠技術可達成。典型地，必須取代大約30¾之活 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇 χ 297公釐） 經濟部中央榡準局員工消費合作社印製 2&647〇 A7 --- B7 五、發明説明（9 ) 性表面群以實質上減少稠密化。又，所選擇之取代表面種 類係由於其舆特定微孔流體結合之潤濕特性；因此，於圈 2D中，彎月面18顯著地較圈28者爲平坦，形成較接近90度 之微孔流體接觸角度。因流體接觸角度接近90度，所以接 觸角度q之餘弦接近0，且方程式1之毛細管壓力P成比 例地減少。吾人相信，表面修飾防止表面縮合反應，且亦 可藉由改變微孔流體接觸角度以減少毛細管壓力，從而.使. 得表面修飾之凝膠中之微孔在乾燥後能較佳地保存。此新 穎之技術能在大氣壓力下產生電介質層，且具有類似於以 超臨界方式乾燥氣凝膠之平均微孔直徑、有孔率以及整體 收缩。 此表面修飾之额外益處係疏水性（hydrophobicity)。吾 人已發現，例如，僅以甲基群取代15%之活性表面群，可 充分地產生疏水性之結構。此對於半導體處理中使用之任 何材料係一重要特徵，而對於多孔材料特别如此。如果留 下之多孔表面係親水性（需水性），則此結構非常類似於 普通家用之海綿，其可保持自身重量數倍"之水。然而，此 極小微孔尺寸使得親水性之多孔電介質迅速地自周園空氣 中收集水分，於裝置製造期間防止此事可能會增加困難。 於凝膠乾燥前使微孔成爲疏水性可避免此等困難。 依據本發明，圈3A-3D顯示半導體裝置於各種製造期間 之剖面圈。於此等實施例之描述期間，晶圓字橐之使用意 謂如傳統半導體處理中使用之晶圓，具有至少併入該處描 繪之半導體裝置。於圖3A中，係顯示三個樣式化導體24 ( -11 - 本紙張尺度通用中國國家標準（CNS ) A4規格（210 X 297公嫠） (請先閲讀背面之注意事項再填寫本頁) 裝- 訂 經濟部中央標準局貝工消費合作社印製 A7 B7 i、發明説明（10 ) 例如鋁及少量铜之合金）形成在绝緣層22上，此絶緣層22 可含有通道或貫穿孔（未顧示 > 以提供導艏24與裝置较低 層間之電氣接觸。前導體溶液26係顯示爲安置在導體24之 間，以例如旋轉附著技術施加至晶圓上。此前導體可由例 如下述2步驟處理所製備。首先，形成原矽酸四乙醏 (TEOS, tetraethylorthosilicate)半溶融材料（stock)， 係將TE0S、乙酵、水及氣化氫之大約1:3:1:0.0007莫耳比 之混合物各成分在固定回流（ref lux)及攝氏60度下挽拌 1.5小時而製得。其次，於此TE0S半溶触材料中加入〇.〇5 莫耳氫氧化銨，各毫升TE0S半溶融材料使用0,1毫升。因 爲氫氧化銨加入該半溶融材料大大地增加凝膠率，此溶液 必須快速施加至晶圓（交換此二步驟係可能者）。於溶液 施加至晶圓後，必須注意以確定薄膜不致過早乾燥；較佳 地，含有溶液/凝膠之晶圓在乾燥階段前之所有時間保持 沉浸在液體中或在飽和之大氣中。凝膠及老化較佳係藉由 使裝置安置在大約攝氏37度之乙酵環境中大約24小時而完 成。接著，較佳使晶圓沉浸在純乙醇中，"可自濕凝膠除去 水分。然後，可實施表面修飾步驟，較佳將晶圓沉浸在含 有大约體積上10¾之三甲基氣基矽垸（TMCS， trimethylchlorosilane)之己垸溶液中。於短暫之反應時 間後，通常將晶圓沉浸在非質子性溶劑（例如丙酮、己烷 )中以除去未反應之表面修飾化合物，且將過多之溶劑排 出◊於此溶劑交換後，溶劑最後可自濕凝膠26處蒸發。此 可製造類似於圖3B之結構，圖3B描繪乾燥之凝膠現在形成 -12 - 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇 X 297公釐） ----^-------— (請先閲讀背面之注意事項再填寫本頁) 訂
經濟部中央標準局員工消費合作社印裝 多孔電介質層:8 ’且亦描绔此方法之典型少量百分比收缩 (乾燥之多孔薄族厚度僅稍微小㈣凝膠厚度卜此及赛 似實施例之-糾係表面修飾之多孔電介質衫疏水性， 然而另-類似之讀臨界方式乾燥之氣凝膠（無表面修飾 )傾向於親水性，除非予以後續處理。 如圈3C中所不者，較佳係以實質非多孔電介質層3〇覆蓋 多孔層28用以密封開放孔之結構，於機械上增強裝置，至· 提供非多孔層用於通道蝕刻及形成進一步之金屬/電介質 層。此非多孔層可由二氧化矽、氮化矽、具有二氧化矽及 氮化矽次層之合成層、矽氧氮化物、有機绝緣體、或類似 材料組成’以例如化學氣相沉積（CVD)或旋轉附著玻璃 (SOG)之方法予以施加。圖3d顯示通道蝕刻貫穿之非多孔 層30並填滿導電材料，以提供填充金屬之通道32，從而提 供裝置用以在導體24與第二層樣式化導體34 (顯示一個） 之間電氣連接。此實施例之非多孔層形成大部分之層間電 介質。雖然固態電介質少量或不能減少層間電容，但可保 持良好之層間機械特性。此係較佳者，因》爲其達成低之層内 電容且同時大體上保持完全固態之層内/層間電介質之機 械特性。此使吾人瞭解，層内電容減少遠較層間電容減少 爲重要。 圖4A-4C顯示具有不同電介質架構之第二實施例。圖4A 顯示類似於圈3C之結構，除了非多孔電介質層30太薄而無 法形成層間電介質。參照圖4B，藉由例如以非凝膠之前導 體溶液塗覆非多孔電介質層30並重覆圖1之步驟，形成第 -13 - 本紙張尺度適用中關家樣準（CNS) Α4· (21()><297公楚） ϋ I n I I n I » I I n n I I ^ - . (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印装 A7 B7 —--—---------- 五、發明説明（12 ) 二多孔電介質層36。如圈4C中顯示者，可在第二多孔層36 上沉積軍蓋層38。軍蓋層38可使用例如類似於產生非灸孔 層30之材料及方法予以形成。此實施例能提供實質上較先 前實施例爲低之層間介電常數，可能犧牲一些結構強度。 然而，非多孔及罩蓋層能有助於控制通道形成。且罩蓋層 能提供堅固基礎用於另外之導電層。 圖5描繪一實施例，僅具有一多孔及一非多孔電介質層 ，而其層内及大部分層間電介質大髏上由多孔層形成。多 孔電介質層28之形成較佳係藉由增加塗佈溶液之沉積深度 將導體完全覆蓋至須用以形成層間電介質之大約深度（自 基底22測量）。此方法須沉積並將溶液凝膠化數次以達到 所需之绝緣體厚度。然後，可依照本發明方法之一乾燥多 孔電介質層28。在多孔層28上可，例如，使用類似於先前 實施例中用以形成非多孔層之材料及方法塗佈非多孔層30 〇 圖6A-6F顯示用於多孔層内電介質之裝置構造之剖面圖 。圖6A再度顯示在基底22上之樣式化導髏’24。藉由例如上 述之一方法，形成多孔電介質層28以填滿介於導體24間之 間隙並覆蓋導體24,其乾燥之結構可能類似於圖6B。圖6C 顯示除去多孔層28之頂部部分後較佳地曝露導鱧24頂部之 結構。此材料之除去可藉由，例如，控制之化學蝕刻，例 如氟化氫（HF)電漿蝕刻，以密切相關於電介質有孔率之濃 度及蝕刻時間而達成。或者，此材料之除去可藉由機械拋 光器使用例如發石（silica)之膠態懸浮液（aqueous -14 - 本紙張尺度適用中國國家標準·（ CNS ) A4g ( 2l〇x297公瘦） (請先閲讀背面之注意Ϋ項再填寫本頁} 策· 訂 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（13 ) colloidal suspension)而完成。此使吾人認清，沉積較 厚之多孔層且蝕刻除去可比以較精確方式僅在導鳢間之間 隙沉積多孔層爲容易（且因此較隹）。圖6D顯示之步驟係 較佳藉由化學氣相沉積（CVD)技術沉積一致之二氧化矽次 層56，例如，直接覆蓋多孔電介質層28及導體24。主要沉 積接近多孔層頂部之乾燥處理之CVD層較旋轉附著之玻璃 (S0G)爲佳，此S0G可能含有會弄濕多孔層28中微孔之溶劑. 。然而，CVD並非特别平面化，且係形成厚電介質之相當 慢之方法。圖6E描繪如何施加非多孔電介質30覆蓋一致之 次層56，例如S0G氧化物，以迅速完成平面化之層間電介 質。 圖6F顯示光罩50沉積及樣式化後之結構。此爲晶圓預備 貫穿屬30及56之通道52之餘刻，如圈6G中所示者。此實施 例之一優點係通道52並未貫穿多孔電介質28，該多孔電介 質係不易猜確樣式化之材料。最後，圖6H劈示填滿金屬之 通道32以及第二樣式化之導體層34,由塡滿金屬之通道32 電連接至樣式化導體24之一。本發明此實無例可提供優異 之層内電容減少、多孔與非多孔電介質間之良好機械結合 、直接構建大量傳統通道形成之技術、以及具有良好機械 及熱轉移特性之平面化非多孔層間電介質。 圖7描繪一實施例，其中多孔電介質層28以相當薄之一 致鈍化層54與導體24隔離，此鈍化層可由例如CVD二氧化 矽所形成。此鈍化層於數個實施例中係有益者。於例如圖 6之實施例中，在多孔電介質28之蝕刻除去期間，可自導 m In I - -- I an· —i I n D - -I - -- . mu nn ^^^1 ^SJ (請先閱讀背面之注意事項再填寫本頁) -15 - A7 ---_B7_ 五、發明説明（14 ) --- 體24之頂部移除層54。 圈8A-8D描繪含有電介質分隔物之另一實施例。於圖8A 中，導體24係以其頂部上之電介質分隔物58予以樣式化。 此分隔物較佳係由非多孔層3〇(顯示於圖8D)中使用之相 同材料所形成。此可藉由沉積導體層、以例如二氧化矽材 料之電介質層予以覆蓋並以一光軍將上迷兩者樣式化而完 成。於圈8B中’已形成多孔電介質層28，以如圖示般校佳 地覆蓋分隔物58。闽8C顯示已除去多孔電介質28之頂部部 分後之裝置。此步樣較佳地曝露分隔物之頂部，且如圖8C 所描繪者，實際亦可能除去分隔物58之頂部部分。最後， 圈8D顯示已沉積非多孔電介質3〇覆蓋此結構以完成層間電 介質後之裝置。此實施例之一優點係加入分隔物可允許除 去多孔電介質之頂部部分，而不致有除去導體一部分之可 能性。此結構亦可形成較低之串擾，如相較於圖6之實施 例。 下表提供與圈式對照之一些實施例之概要。 (請先閲讀背面之注意事項再填寫本I) 裝· 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家榡準（CNS ) M規格（2丨ox297公釐） A7 A7 經濟部中央標準局員工消費合作社印製 B7 五、發明説明（15 ) 圖式 元件 較佳或 特定實例 一般術語 其他替代實例 22 先前層間電 介質 基底 先前形成之半導體裝置 層 24，34 鋁銅合金及 /或对熱材 料 導體 銘、銅、翻、鹤、鈥及 其合金 多晶矽、矽化物、氮化 物、碳化物 26 原矽酸四乙 S旨（TE0S)半 溶融材料 前導體溶 液 微粒溶液或膠態矽、鍺 、鈦、矽酸鋁 比率之原矽酸四乙酯 (TE0S)/甲基三乙氧基 矽烷（MTE0S)半溶融材 料，比率之原矽酸四乙 酯（TE0S.)/(1，2-雙（三 甲氧基了矽垸）乙烷） (BTMSE)·丰溶融材料 28，36 表面修飾之 乾燥凝膠 多孔電介 質層 超臨界乾燥之氣凝膠、 其他微孔多孔電介質 30, 38 二氧化矽 非多孔電 介質層 其他氧化物、摻雜硼或 磷之二氧化矽、氮化矽 、矽氧氮化物 對二甲苯熱塑性聚合膜 (parylene)、聚酿亞胺 、有機氧化物 •^^1 u m n UK —^lt ^ nn m n ^^^1 TJ - 0¾.-吞 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）
296470 五、發明説明（16 ) 32 鋁銅合金及 塡充金屬 /或耐熱材 料 之通道 50 ---—— 54 ---- — 二氧ϋ~ 56 ~—---- 二氧化發 一致之次 層 58 二氧化矽 電介質分 隔物 輿上迷導髏者相同 氮化矽、矽氧氮化物 氮化矽、矽氧氮化物 有機氧化物 與上述非多孔電介質層 者相同 本發明之解析並非受限於此處描迷之特定實施例，因該 等實施例係視爲例示者而非限制者。本發明意欲涵蓋所有 未偏離本發明精神及範疇之方法及結構。例如，熟於此技 藝之人士可於本發明中應用許多其他公開方法之一，即最 初自適當之前導體形成濕凝膠。在不偏離本發明本質下， 可組合一些特定實例之特性。 ， ^^1 H^I nn —^1 HI k tn ml Kn nn In — (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 -18 本紙张尺度適用中國國家標準（CNS ) A4規格（210X297公釐）

Claims (1)

  1. 經濟部中央標準局男工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 1. 一種半導體裝置，其包含： (a) 第一及第二水平相雜之導雅，形成在一基底上； (b) 多孔電介質，介於上述第一及第二導想間，上述 多孔電介質具有平均高度爲上述導體高度之75%至150% ，上述多孔電介質具有範園在30%至95%之有孔率以及小 於80毫微米之平均微孔直徑；以及 (c) 非多孔電介質層，沉積覆蓋上述第一及第二導耀 與上述多孔電介質，上述非多孔層之高度自上述導雜上 測量爲至少上述導鱧高度之50¾，從而在相同水平上導 體間之電容性耦合相較於固態之二氧化矽電介質者爲實 質上減少且實質上保持固態層間電介質之機械特性。 2. 如申請專利範囲第χ項之半導體裝置，其中非多孔電介 質層包含實質上一層間電介質之全部。 3. 如申請專利範圍第1項之半導體裝置，其中多孔電介質 具有範園在50%至75¾之有孔率。 4. 如申請專利範圍第1項之半導體裝置，其中多孔電介質 具有大約範固在2毫微米至25毫微米之•微孔直徑。 5. 如申請專利範圍第1項之半導體裝置，其中多孔電介質 係疏水性。 6. 如申請專利範团第1項之半導體裝置，復包含一鈍化層 覆蓋上迷第一及第二導體之側邊。 7·如申請專利範团第6項之半導體裝置，其中鈍化層係由 選自氮化矽、二氧化矽、矽氧氮化物及該等組合之群之 材料所组成。 -19 - ^紙張尺度適用I) ( 2獻297公董）--- I I I n n n L 裝------訂 (請先閲讀背面之注意事項再填寫本頁) A8 ------ D8__ 六、申請專利^ 一一~~" ' —— 8.如申請專利範面第i項之半導禮裝置，其中導髏係由選 自招、铜、鈇、始、金、鎮、多晶石夕、麵、線、氮化欽 (ΤΠΟ、二矽化鈦（TiSi 2 )及該等組合之群之材料所组 成。 9·如申請專利範圍第i項之半導想裝置，其中非多孔電介 質看係由選自二氧化石夕、氮化石夕、石夕氧氮化物、有機聚 合物及該等組合之群之材料所組成。 io. —種半導體裝置，其包含： U)第一樣式化導體層，形成在一基底上； (b) 多孔電介質層，佔據上述樣式化導體間之剩餘間 隙，上述多孔電介質具有平均高度爲上述導體高度之75 %至150%，上述多孔電介質具有範園在3〇%至95%之有孔 率以及小於80毫微米之平均微孔直徑； (c) 非多孔電介質層，沉積覆蓋上述導醴及上述多孔 電介質層； (d) —或多個塡充金屬之通道，貫穿上述非多孔電介 質層’用以提供電連接至上述第一樣式*化導體；以及 經濟部中央標準局員工消費合作社印袋 m amen Hi m J m ^ >RI-I I fn n w 、T (請先閱讀背面之注意事項再填寫本頁) (e) 至少一第二層導體，形成在上述非多孔電介質層 上且電連接至上述第一導體，從而在上述第一層上導體 間之電容性耦合相較於固態之二氧化矽電介質者爲實質 上減少且實質上保持固態層間電介質之機械特性。 11.如申請專利範圍第1〇項之半導體裝置，其中非多孔電 介質層係由至少一底部次層及一頂部次層所組成，上述 底部次層係一致者且上述頂部次層係平面化者。 -20 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A8 B8 C8 D8 六、申請專利範圍 12.如申請專利範圍第10項之半導體裝置，復包含一鈍化 層覆蓋上述第一樣式化導體之側邊及頂部。 —種構建半導體裝置之方法，包含： U)提供一樣式化導體層，形成在一半導體基底上； (b) 形成一多孔電介質層，填充介於上述樣式化導體 間之間隙並覆蓋上述樣式化導體； (c) 除去上述多孔電介質層之頂部部分；以及 (d) 沉積一非多孔電介質，覆蓋上述導體及上述多孔 電介質層，從而在相同水平上導體間之電容性耦合相較 於固態二氧化矽電介質者爲實質上減少且實質上保持固 態層間電介質之機械特性。 14. 如申請專利範園第13項之方法，復包含產生一或多個 填充金屬之通道，貫穿上述非多孔電介質層，以提供電 氣接觸至上述樣式化導體，並形成一第二導體層覆蓋上 述非多孔電介質層。 15. 如申請專利範園第13項之方法，復包含表面處理上述 多孔電介質，以於除去上述多孔電介質!層之頂部部分之 前使上述多孔電介質成爲疏水性。 16. 如申請專利範圍第13項之方法，復包含在上述多孔電 介質形成步驟前，一致地施加一鈍化層至上述導體。 17. 如申請專利範圍第13項之方法，其中沉積非多孔電介 質層之步驟包含沉積底部及頂部次層，上述底部次層係 一致地沉積且上述頂部次層係一平面化層。 18. 如申請專利範圍第17項之方法，其中底部次層係以化 -21 - 本紙張尺度適用中國國家標準（CNS〉A4規格（210Χ297公釐） (請先閱讀背面之注意事項再填寫本頁) 蒗. 訂 經濟部中央標準局員工消費合作社印製 396470 ll D8 六、申請專利範圍 學氣相沉積方法予以沉積。 19. 如申請專利範園第13項之方法，其中多孔電介質層_之 頂部部分除去步驟包含以機械方式拋光上述半導體裝置 〇 20. 如申請專利範圍第13項之方法，其中上述多孔電介質 層之頂部部分除去步驟曝露上述導體之頂部。 (請先閱讀背面之注意事項再填寫本頁) 、1T 經濟部中央標準局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）
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US5488015A (en) 1996-01-30
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US5747880A (en) 1998-05-05
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KR950034792A (ko) 1995-12-28

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