TW202018906A - 集成電路靜電放電總線結構和相關方法 - Google Patents
集成電路靜電放電總線結構和相關方法 Download PDFInfo
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Abstract
一種集成電路靜電放電總線結構包含一電路區域;多個靜電放電總線;多個接墊群組,相鄰並連接該多個靜電放電總線;一共同靜電放電總線,相鄰該多個接墊群組;以及多個結合線,用來連接該多個接墊群組到該共同靜電放電總線。
Description
本發明係指一種集成電路結構和相關方法,尤指一種集成電路靜電放電總線結構和相關方法。
第1圖為一集成電路靜電放電(electrostatic discharge,ESD)結構1的示意圖。基於特定序列和配置,可將輸入輸出(input/output,I/O)接墊12設置在一電路區域10的周圍,並設置在多個晶片邊緣13的內部,其中輸入輸出接墊12的空間配置可在特定範圍內進行調整。
一般而言,習知技術常使用填充單元(filler cell)F1、F2來填補輸入輸出接墊12之間的空隙,並將填充單元F1、F2連接到一靜電放電總線11(例如,將一布局走線連接到一接地部或一系統電壓),如此可讓電路區域10和填充單元F1、F2的每個部份都連接到連續的靜電放電總線,以提供集成電路靜電放電總線結構1的靜電放電保護功效。
然而,填充單元F1、F2佔據了電路區域10的一部分空間,如此相當於浪費了集成電路靜電放電總線結構1的電路面積。進一步地,在嚴格的布局條件下,集成電路靜電放電總線結構1必須配置為一矩形形狀,如此讓內部電路布局的設計相當不具彈性。再者,當有些電路設計的形狀是不規則形狀並分布在不同區域時,在某些情況下則必須增加電路區域10的面積來容納不規則形狀並分布在不同區域的電路,如此增加了生產成本。
因此,實有必要提供一種集成電路靜電放電總線結構和相關方法,以充分使用電路區域的空間。
因此,本發明的主要目的即在於提供一種集成電路靜電放電總線結構和相關方法。
本發明揭露一種集成電路結構,包含一電路區域;多個靜電放電總線;多個接墊群組,相鄰並連接該多個靜電放電總線;一共同靜電放電總線,相鄰該多個接墊群組;以及多個結合線,用來連接該多個接墊群組到該共同靜電放電總線。
本發明另揭露一種集成電路結構,包含一電路區域;多個靜電放電總線;多個接墊群組,相鄰並連接於該多個靜電放電總線;以及多個結合線,用來連接該多個接墊群組的一個接墊到另一個接墊。
本發明另揭露一種形成集成電路結構的方法,包含形成一電路區域;形成多個接墊群組,該多個接墊群組對應該電路區域的多個不連續邊界;形成一共同靜電放電總線,該共同靜電放電總線相鄰該多個接墊群組;以及經由多個結合線,連接對應該多個接墊群組的多個接墊到該共同靜電放電總線。
本發明另揭露一種形成集成電路結構的方法,包含形成一電路區域;形成多個接墊群組,該多個接墊群組對應該電路區域的多個不連續邊界;以及經由跨越該電路區域的多個結合線的一結合線,連接該多個接墊群組的一個接墊群組到該多個接墊群組的另一個接墊群組。
第2圖為本發明實施例一集成電路靜電放電(electrostatic discharge,ESD)總線結構的示意圖。集成電路靜電放電總線結構2包含一電路區域20、多個靜電放電總線E1、E2、E3、多個接墊群組G1、G2、G3、一共同靜電放電總線24以及多個結合線25。
多個晶片邊緣23可形成電路區域20;舉例來說,四個晶片邊緣23可形成一矩形區域,用來容納電路區域20。電路區域20包含多個不連續邊界B1、B2、B3。多個靜電放電總線E1、E2、E3形成在晶片邊緣23的內部,對應並相鄰多個不連續邊界B1、B2、B3。
多個接墊群組G1、G2、G3形成在內部晶片邊緣23,相鄰並連接到多個靜電放電總線E1、E2、E3。共同靜電放電總線24形成在晶片邊緣23外部,但不限於此。共同靜電放電總線24不一定是一體成形,其可包含多個不連續的靜電放電總線群組。多個結合線25跨越晶片邊緣23,用來連接多個接墊群組B1、B2、B3到共同靜電放電總線24。於一實施例中,共同靜電放電總線24平行多個靜電放電總線E1、E2、E3和多個接墊群組G1、G2、G3。
多個接墊群組G1、G2、G3的每一者包含至少一接墊22,其中接墊22是一輸入輸出接墊,並且連接到一接地部或一系統低電壓。多個結合線25中的至少一者可用來連接至少一接墊22到共同靜電放電總線24。於一實施例中,多個結合線25可用來連接接墊群組G1的多個接墊22到共同靜電放電總線24,如此可提供多個連接路徑,來強化接墊群組G1和共同靜電放電總線24之間的導電性,以提升靜電放電保護的功效。
在此結構下,不連續靜電放電總線E1、E2、E3可經由結合線25,將接墊群組G1、G2、G3的接墊22連接到共同靜電放電總線24,如此可在集成電路靜電放電總線結構中等效地形成一連續靜電放電總線。如此一來,本發明可避免使用習知技術的填充單元。除此之外,不連續靜電放電總線E1和E2(或是E2和E3)之間的空間可用來設置電路元件,以充分使用集成電路靜電放電總線結構2的空間。
舉例來說,第1圖的靜電放電總線11和填充單元F1、F2可替換為第2圖的節省區域SA1、SA2。節省區域SA1相鄰靜電放電總線E1、E2以及接墊群組G1、G2的接墊22。節省區域SA2相鄰靜電放電總線E2、E3以及接墊群組G2、G3的接墊22。於一實施例中,共同靜電放電總線24形成在晶片邊緣23內部,並且相鄰多個接墊群組G1、G2、G3和節省區域SA1和SA2。
第3圖為本發明實施例一集成電路靜電放電總線結構3的示意圖。集成電路靜電放電總線結構3包含一電路區域30、多個靜電放電總線E1、E2、E3,多個接墊群組G1、G2、G3以及多個結合線35。
多個晶片邊緣33可形成電路區域30;舉例來說,四個晶片邊緣33可形成一矩形區域,以容納電路區域30。電路區域30包含多個不連續邊界B1、B2、B3。多個靜電放電總線E1、E2、E3形成在晶片邊緣33內部,並且對應和相鄰多個不連續邊界B1、B2、B3。
多個不連續靜電放電總線E1、E2、E3形成在晶片邊緣33內部,並且相鄰多個不連續邊界B1、B2、B3。多個接墊群組G1、G2、G3形成在晶片邊緣33內部,相鄰和連接到多個靜電放電總線E1、E2、E3。多個結合線35跨越電路區域30,用來連接多個接墊群組G1、G2、G3中的一個接墊群組到另一個接墊群組,例如,一個結合線35可連接接墊群組G1到接墊群組G2,而另一個結合線35可連接接墊群組G2到接墊群組G3。
多個接墊群組G1、G2、G3的每一者包含多個接墊32,其中接墊32是一輸入輸出接墊,並連接到一接地部或一系統低電壓。多個結合線35用來連接一個接墊群組的接墊32到另一個接墊群組的接墊32。多個接墊群組G1、G2、G3的每一者包含一連接接墊(例如,接墊群組G1的最右接墊、接墊群組G2的最左和最右接墊,以及接墊群組G3的最左接墊),而多個結合線35用來連接多個接墊群組中的一個接墊群組的連接接墊到另一個接墊群組的連接接墊。舉例來說,結合線35的一者用來連接接墊群組G1的最右接墊32到接墊群組G2的最左接墊32,而結合線35的另一者用來連接接墊群組G2的最右接墊32到接墊群組G3的最左接墊32,但不限於此。
在此結構下,不連續的靜電放電總線E1、E2、E3可經由連接接墊32來連接到接墊群組G1、G2、G3,如此可等效地形成集成電路靜電放電總線結構3的一連續靜電放電總線。如此一來,本發明可避免使用習知技術的填充單元。除此之外,不連續靜電放電總線E1、E2(或是E2、E3)之間的空間可用來設置電路元件,以充分使用集成電路靜電放電總線結構3的空間。舉例來說,第1圖的靜電放電總線11和填充單元F1、F2可替換為第3圖的節省區域SA1和SA2。因此,電路區域30可容納不規則形狀和區域的電路,而不須增加電路面積,如此可節省生產成本。
第4圖為本發明實施例一集成電路形成流程4的流程圖,包含以下步驟。
步驟40:形成一電路區域。
步驟41:在多個晶片邊緣內部,形成對應電路區域的多個不連續邊界的多個接墊群組。
步驟42:在多個晶片邊緣外部,形成一共同靜電放電總線。
步驟43:經由跨越多個晶片邊緣的多個結合線,連接對應多個接墊群組的多個接墊到共同靜電放電總線。
於步驟40中,形成一電路區域;於步驟41中,在多個晶片邊緣內部,形成對應電路區域的多個不連續邊界的多個接墊群組;於步驟42中,在多個晶片邊緣外部,形成一共同靜電放電總線;以及於步驟43中,經由跨越多個晶片邊緣的多個結合線,連接對應多個接墊群組的多個接墊到共同靜電放電總線。經由集成電路靜電放電總線結構流程4,可等效地形成一連續靜電放電總線,以避免使用習知技術的填充單元。
第5圖為本發明實施例一集成電路形成流程5的流程圖,包含以下步驟。
步驟50:形成一電路區域。
步驟51:在多個晶片邊緣內部,形成對應電路區域的多個不連續邊界的多個接墊群組。
步驟52:在多個晶片邊緣內部,經由跨越電路區域的多個結合線,連接多個接墊群組的一個接墊群組到另一個接墊群組。
於步驟50中,形成一電路區域;於步驟51中,在多個晶片邊緣內部,形成對應電路區域的多個不連續邊界的多個接墊群組;以及於步驟52中,在多個晶片邊緣內部,經由跨越電路區域的多個結合線,連接多個接墊群組的一個接墊群組到另一個接墊群組。經由集成電路靜電放電總線結構流程5,可等效地形成一連續靜電放電總線,以避免使用習知技術的填充單元。
綜上所述,本發明使用結合線來連接多個接墊群組的多個接墊,用來等效地形成一連續靜電放電總線。如此一來,本發明可避免使用習知技術的填充單元。除此之外,不連續靜電放電總線之間的空間可用來設置電路元件,以充分使用集成電路靜電放電總線結構的空間。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
1、2、3:集成電路靜電放電總線結構10、20、30:電路區域F1、F2:填充單元11、E1、E2、E3:靜電放電總線12:輸入輸出接墊22、32:接墊13、23、33:晶片邊緣24:共同靜電放電總線25、35:結合線B1、B2、B3:不連續邊界G1、G2、G3:接墊群組SA1、SA2:節省區域4、5:集成電路形成流程40、41、42、43、50、51、52:步驟
第1圖為習知技術一集成電路靜電放電總線結構的示意圖。 第2圖為本發明實施例一集成電路靜電放電總線結構的示意圖。 第3圖為本發明實施例一集成電路靜電放電總線結構的示意圖。 第4圖為本發明實施例一集成電路形成流程的流程圖。 第5圖為本發明實施例一集成電路形成流程的流程圖。
2:集成電路靜電放電總線結構
20:電路區域
22:接墊
23:晶片邊緣
24:共同靜電放電總線
25:結合線
B1、B2、B3:不連續邊界
E1、E2、E3:靜電放電總線
G1、G2、G3:接墊群組
SA1、SA2:節省區域
Claims (17)
- 一種集成電路結構,包含: 一電路區域; 多個靜電放電總線; 多個接墊群組,相鄰並連接該多個靜電放電總線; 一共同靜電放電總線,相鄰該多個接墊群組;以及 多個結合線,用來連接該多個接墊群組到該共同靜電放電總線。
- 如請求項1所述的集成電路結構,其中該多個接墊群組中的每個接墊群組包含至少一接墊,且該多個結合線用來連接該至少一接墊到該共同靜電放電總線。
- 如請求項1所述的集成電路結構,其中共同靜電放電總線包含多個不連續靜電放電總線群組。
- 如請求項1所述的集成電路結構,其中該共同靜電放電總線形成在該多個晶片邊緣的外部或形成在該多個晶片邊緣的內部。
- 如請求項1所述的集成電路結構,其中該電路區域包含至少一節省區域,該至少一節省區域相鄰該靜電放電總線和該多個接墊群組。
- 如請求項1所述的集成電路結構,其中該共同靜電放電總線平行該多個靜電放電總線。
- 一種集成電路結構,包含: 一電路區域; 多個靜電放電總線; 多個接墊群組,相鄰並連接於該多個靜電放電總線;以及 多個結合線,用來連接該多個接墊群組的一個接墊到另一個接墊。
- 如請求項7所述的集成電路結構,其中該電路區域包含至少一節省區域,至少一節省區域該相鄰該多個靜電放電總線和該多個接墊群組。
- 如請求項7所述的集成電路結構,其中該多個接墊群組中的每個接墊群組包含一連接接墊,且該多個結合線用來連接該多個接墊群組的一個接墊群組的該連接接墊到該多個接墊群組的另一個接墊群組的該連接接墊。
- 一種形成集成電路結構的方法,包含: 形成一電路區域; 形成多個接墊群組,該多個接墊群組對應該電路區域的多個不連續邊界; 形成一共同靜電放電總線,該共同靜電放電總線相鄰該多個接墊群組;以及 經由多個結合線,連接對應該多個接墊群組的多個接墊到該共同靜電放電總線。
- 如請求項10所述的形成集成電路結構的方法,其中該多個接墊群組中的每個接墊群組包含至少一接墊,且該多個結合線用來連接該至少一接墊到該共同靜電放電總線。
- 如請求項10所述的形成集成電路結構的方法,另包含: 在該多個晶片邊緣的外部或在該多個晶片邊緣的內部,形成該共同靜電放電總線。
- 如請求項10所述的形成集成電路結構的方法,其中該共同靜電放電總線is平行該多個靜電放電總線。
- 一種形成集成電路結構的方法,包含: 形成一電路區域; 形成多個接墊群組,該多個接墊群組對應該電路區域的多個不連續邊界;以及 經由跨越該電路區域的多個結合線的一結合線,連接該多個接墊群組的一個接墊群組到該多個接墊群組的另一個接墊群組。
- 如請求項14所述的形成集成電路結構的方法,其中該電路區域包含至少一節省區域相鄰該多個靜電放電總線和該多個接墊群組。
- 如請求項14所述的形成集成電路結構的方法,其中該共同靜電放電總線平行該多個靜電放電總線和該多個接墊群組。
- 如請求項14所述的形成集成電路結構的方法,其中該多個接墊群組中的每個接墊群組包含一連接接墊,且該多個結合線用來連接該多個接墊群組中的該連接接墊到該多個接墊群組中的另一個連接接墊。
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Also Published As
Publication number | Publication date |
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