CN111199891A - 集成电路静电放电总线结构和相关方法 - Google Patents
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Abstract
集成电路静电放电总线结构和相关方法。一种集成电路ESD总线结构包括:电路区域;多个静电放电(ESD)总线;多个焊盘组,邻近于并连接至所述多个ESD总线;公共ESD总线;以及多个结合线,被配置为将所述多个焊盘组连接至所述公共ESD总线。
Description
本申请是申请号为201880002197.9(PCT/CN2018/113271),申请日为2018年11月1日,发明名称为“集成电路静电放电总线结构和相关方法”的中国专利申请的分案申请。
技术领域
本发明涉及集成电路结构和相关方法,并且更具体地,涉及集成电路静电放电总线结构和相关方法。
背景技术
对于如图1中示出的集成电路静电放电(以下简写为ESD)结构1,I/O(输入/输入)焊盘12基于特定顺序和位置放置在多个芯片边缘13内部的电路区域10周围,其中,能够在特定范围内调整I/O焊盘12的放置。
通常,一般将填料单元F1和F2放置在I/O焊盘12之间的空的空间处,并且将填料单元F1和F2连接至静电放电(ESD)总线11(例如,连接至地或系统电压的版图迹线),这使得电路区域10的每一个部分和填料单元F1和F2连接至连续的ESD总线以提供对集成电路ESD总线结构1的ESD保护。
然而,填料单元F1和F2占用的电路区域10的部分对集成电路ESD总线结构来说是浪费的。此外,在具有矩形形状的集成电路ESD总线结构1的严格要求下,其导致内电路版图设计缺乏灵活性。
此外,当存在具有不规则形状和不同区域的电路时,必须增大电路区域10以包含具有不规则形状和不同区域的电路,这增大了生产成本。
因而,期望提供集成电路ESD总线结构和相关的方法,以充分利用电路区域。
发明内容
因此,本发明的目的是提供集成电路静电放电总线结构和相关的方法。
为了实现以上技术目的,根据本发明,提供了一种集成电路静电放电(ESD)总线结构,并且所述结构包括:电路区域;多个静电放电总线;多个焊盘组,邻近于并连接至所述多个ESD总线;公共ESD总线;以及多个结合线,被配置为将所述多个焊盘组连接至所述公共ESD总线。
为了实现以上技术目的,根据本发明,提供了一种集成电路静电放电(ESD)结构,并且所述结构包括:电路区域;多个静电放电(ESD)总线;多个焊盘组;以及多个结合线,被配置为将所述多个焊盘组中的一个焊盘组连接至另一个焊盘组。
为了实现以上技术目的,根据本发明,提供了一种形成集成电路ESD总线结构的方法,并且所述方法包括:形成电路区域;形成多个焊盘组,所述多个焊盘组对应于所述电路区域的多个不连续的边界;形成公共ESD总线;以及通过跨所述多个芯片边缘中的一个芯片边缘的多个结合线将对应于所述多个焊盘组的多个焊盘连接至所述公共ESD总线。
为了实现以上技术目的,根据本发明,提供了一种形成集成电路ESD总线结构的方法,所述方法包括:形成电路区域;形成多个焊盘组,所述多个焊盘组对应于所述电路区域的多个不连续的边界;以及通过跨所述电路区域的多个结合线中的一个结合线将所述多个焊盘组中的一个焊盘组连接至所述多个焊盘组中的另一个焊盘组。
在阅读在各个图和图样中示例的优选实施例的以下详细描述之后,对于本领域技术人员来说,本发明的这些和其它目的将无疑地变得显而易见。
附图说明
图1是根据现有技术的集成电路ESD总线结构的示意图。
图2是根据本发明的实施例的集成电路ESD总线结构的示意图。
图3是根据本发明的实施例的集成电路ESD总线结构的示意图。
图4是根据本发明的实施例的集成电路封装工艺的流程图。
图5是根据本发明的实施例的集成电路封装工艺的流程图。
具体实施方式
图2是根据本发明的实施例的集成电路静电放电(ESD)结构2的示意图。集成电路ESD总线结构2包括电路区域20、多个ESD总线E1、E2和E3、多个焊盘组G1、G2和G3、公共ESD总线24、以及多个结合线25。
电路区域20由多个芯片边缘23形成;例如,四个芯片边缘23形成被配置为包含电路区域20的矩形区域。电路区域20包括多个不连续的边界B1、B2和B3。多个ESD总线E1、E2和E3形成于芯片边缘23内部,对应于并邻近于多个不连续的边界B1、B2和B3。
多个焊盘组G1、G2和G3形成于芯片边缘23内部,邻近于并连接至多个ESD总线E1、E2和E3。公共ESD总线24形成于芯片边缘23外部,这不是限制性的。公共ESD总线24可以不形成于一个块中,并且可以包括多个不连续的ESD总线组。多个结合线25跨芯片边缘23形成,并且被配置为将多个焊盘组G1、G2和G3连接至公共ESD总线24。在一个实施例中,公共ESD总线24平行于多个ESD总线E1、E2和E3以及多个焊盘组G1、G2和G3。
多个焊盘组G1、G2和G3中的每一个焊盘组包括至少一个焊盘22,其中焊盘22是连接至地或系统低电压的输入/输出焊盘。多个结合线25中的至少一个结合线被配置为将所述至少一个焊盘22连接至公共ESD总线24。在一个实施例中,多个结合线25可以被配置为将焊盘组G1的多个焊盘22连接至公共ESD总线24,这提供了多个连接来增强焊盘组G1与公共ESD总线24之间的导电性,以改善ESD保护。
在该结构中,不连续的ESD总线E1、E2和E3可以通过将焊盘组G1、G2和G3的焊盘22经结合线25连接至公共ESD总线24而连接到一起,这等同于形成了用于集成电路ESD总线结构2的连续的ESD总线。结果,本发明可以去掉现有技术的填料单元。另外,不连续的ESD总线E1和E2(或E2和E3)之间的空间可以被配置有电路元件以充分利用集成电路ESD总线结构2。
例如,图1中示出的ESD总线11和填料单元F1和F2被图2中的节省的区域SA1和SA2替代。节省的区域SA1邻近于ESD总线E1和E2以及焊盘组G1和G2的焊盘22。节省的区域SA2邻近于ESD总线E2和E3以及焊盘组G2和G3的焊盘22。在一个实施例中,公共ESD总线24形成于芯片边缘23内部,并且邻近于多个焊盘组G1、G2和G3以及节省的区域SA1和SA2。
图3是根据本发明的实施例的集成电路ESD总线结构3的示意图。集成电路ESD总线结构3包括电路区域30、多个ESD总线E1、E2和E3、多个焊盘组G1、G2和G3、以及多个结合线35。
电路区域30由多个芯片边缘33形成;例如,四个芯片边缘33形成包含电路区域30的矩形区域。电路区域30包括多个不连续的边界B1、B2和B3。多个ESD总线E1、E2和E3形成于芯片边缘33内部,对应于并邻近于多个不连续的边界B1、B2和B3。
多个不连续的ESD总线E1、E2和E3形成于芯片边缘33内部,并邻近于多个不连续的边界B1、B2和B3。多个焊盘组G1、G2和G3形成于芯片边缘33内部,邻近于并连接至多个ESD总线E1、E2和E3。多个结合线35跨电路区域30形成,并且被配置为将多个焊盘组G1、G2和G3从一个组连接至另一个组,例如,一个结合线35可以将焊盘组G1连接至焊盘组G2,并且另一个结合线35可以将焊盘组G2连接至焊盘组G3。
多个焊盘组G1、G2和G3中的每一个焊盘组包括多个焊盘32,其中焊盘32是连接至地或系统低电压的输入/输出焊盘。多个结合线35被配置为将一个组的焊盘32连接至另一组。多个焊盘组G1、G2和G3中的每一个焊盘组包括连接焊盘(例如,焊盘组G1的最右边焊盘、焊盘组G2的最左和最右边焊盘、以及焊盘组G3的最左边焊盘),并且多个结合线35被配置为将多个焊盘组中的一个焊盘组的连接焊盘连接至多个焊盘组中的另一个焊盘组的连接焊盘。例如,结合线35中的一个结合线被配置为将焊盘组G1的最右边焊盘32连接至焊盘组G2的最左边焊盘32,且结合线中的一个结合线被配置为将焊盘组G2的最右边焊盘32连接至焊盘组G3的最左边焊盘32,这不是限制性的。
在该结构中,不连续的ESD总线E1、E2和E3可以通过将焊盘组G1、G2和G3的焊盘32从一个组连接到另一个组而连接到一起,这等同于形成了用于集成电路ESD总线结构3的连续的ESD总线。结果,本发明可以去掉现有技术的填料单元。另外,不连续的ESD总线E1和E2(或E2和E3)之间的空间可以被配置有电路元件以充分利用集成电路ESD总线结构3。例如,图1中示出的ESD总线11和填料单元F1和F2被图3中的节省的区域SA1和SA2替代,并且从而电路区域30可以包含具有不规则形状和不同区域的电路,而不会增大其区域,这节省了生产成本。
图4是根据本发明的实施例的集成电路ESD总线结构工艺4的流程图。
步骤40:形成电路区域。
步骤41:形成对应于多个芯片边缘内部的电路区域的多个不连续的边界的多个焊盘组。
步骤42:在多个芯片边缘外部形成公共ESD总线。
步骤43:通过跨多个芯片边缘的多个结合线将对应于多个焊盘组的多个焊盘连接至公共ESD总线。
在步骤40中,形成电路区域;在步骤41中,形成对应于多个芯片边缘内部的电路区域的多个不连续的边界的多个焊盘组;在步骤42中,形成多个芯片边缘外部的公共ESD总线;以及在步骤43中,通过跨多个芯片边缘的多个结合线将对应于多个焊盘组的多个焊盘连接至公共ESD总线。通过集成电路ESD总线结构工艺4,可以等效地形成连续的ESD总线并且可以省略现有技术的填料单元。
图5是根据本发明的实施例的集成电路ESD总线结构工艺5的流程图。
步骤50:形成电路区域。
步骤51:形成对应于多个芯片边缘内部的电路区域的多个不连续的边界的多个焊盘组。
步骤52:通过跨多个芯片边缘内部的电路区域的多个结合线将多个焊盘组中的一个连接至另一个。
在步骤50中,形成电路区域;在步骤51中,形成对应于多个芯片边缘内部的电路区域的多个不连续的边界的多个焊盘组;并且在步骤52中,通过跨多个芯片边缘内部的电路区域的多个结合线将多个焊盘组中的一个焊盘组和另一个焊盘组连接到一起。通过集成电路ESD总线结构工艺5,可以等效地形成连续的ESD总线并且可以省略现有技术的填料单元。
总之,本发明利用结合线来连接多个焊盘组的多个焊盘,从而等效地形成连续的ESD总线。结果,本发明可以去除现有技术的填料单元。另外,不连续的ESD总线之间的空间可以被配置有电路元件,以充分利用集成电路ESD总线结构。
本领域技术人员将容易地观察到可以在保持本发明的教导的同时进行器件和方法的许多修改和更改。因而,以上公开应当被视为仅由所附权利要求的边界和界限限制。
Claims (15)
1.一种集成电路结构,包括:
电路区域;
多个静电放电ESD总线,所述多个静电放电ESD总线被所述电路区域分隔开;
多个焊盘组,邻近于并连接至所述多个ESD总线;
公共ESD总线,邻近于所述多个焊盘组;以及
所述公共ESD总线与所述多个焊盘组中的至少一个连接。
2.如权利要求1所述的集成电路结构,其中,
所述公共ESD总线包括多个不连续的ESD总线组;并且
所述电路区域包括邻近于所述多个ESD总线和所述多个焊盘组的至少一个节省的区域。
3.如权利要求1所述的集成电路结构,其中,
所述多个焊盘组中的每一个焊盘组包括至少一个焊盘;并且
所述多个结合线被配置为将所述至少一个焊盘连接至所述公共ESD总线。
4.如权利要求1所述的集成电路结构,其中,所述公共ESD总线形成于多个芯片边缘外部或所述多个芯片边缘内部。
5.如权利要求1所述的集成电路结构,其中,所述公共ESD总线平行于所述多个ESD总线。
6.一种集成电路结构,包括:
电路区域;
多个静电放电ESD总线,所述多个静电放电ESD总线被所述电路区域分隔开;
多个焊盘组,邻近于并连接至所述多个ESD总线;以及
多个结合线,被配置为将所述多个焊盘组中的一个焊盘组连接至另一个焊盘组。
7.如权利要求1所述的集成电路结构,其中,
所述电路区域包括邻近于所述多个ESD总线和所述多个焊盘组的至少一个节省的区域;
所述多个焊盘组中的每一个焊盘组包括连接焊盘;并且
所述多个结合线被配置为将所述多个焊盘组中的一个焊盘组的所述连接焊盘连接至所述多个焊盘组中的另一个焊盘组的所述连接焊盘。
8.一种形成集成电路结构的方法,包括:
形成电路区域;
形成多个静电放电ESD总线,所述多个静电放电ESD总线被所述电路区域分隔开;
形成多个焊盘组,所述多个焊盘组对应于所述电路区域的多个不连续的边界;
形成公共静电放电ESD总线,所述公共ESD总线邻近于所述多个焊盘组;以及
通过多个结合线将对应于所述多个焊盘组的多个焊盘连接至所述公共ESD总线。
9.如权利要求8所述的形成集成电路结构的方法,其中,
所述公共ESD总线包括多个不连续的ESD总线组;并且
所述电路区域包括邻近于所述多个ESD总线和所述多个焊盘组的至少一个节省的区域。
10.如权利要求8所述的形成集成电路结构的方法,其中,
所述多个焊盘组中的每一个焊盘组包括至少一个焊盘;并且
所述多个结合线被配置为将所述至少一个焊盘连接至所述公共ESD总线。
11.如权利要求8所述的形成集成电路结构的方法,还包括:
在多个芯片边缘外部或所述多个芯片边缘内部形成所述公共ESD总线。
12.如权利要求8所述的形成集成电路结构的方法,其中,所述公共ESD总线平行于所述多个ESD总线。
13.一种形成集成电路结构的方法,包括:
形成电路区域;
形成多个静电放电ESD总线,所述多个静电放电ESD总线被所述电路区域分隔开;
形成多个焊盘组,所述多个焊盘组对应于所述电路区域的多个不连续的边界;以及
通过跨所述电路区域的多个结合线中的一个结合线将所述多个焊盘组中的一个焊盘组连接至所述多个焊盘组中的另一个焊盘组。
14.如权利要求13所述的形成集成电路结构的方法,其中,
所述电路区域包括邻近于所述多个ESD总线和所述多个焊盘组的至少一个节省的区域;
所述多个焊盘组中的每一个焊盘组包括连接焊盘;并且
所述多个结合线被配置为将所述多个焊盘组中的一个焊盘组的所述连接焊盘连接至所述多个焊盘组中的另一个焊盘组的所述连接焊盘。
15.如权利要求13所述的形成集成电路结构的方法,其中,
所述多个焊盘组中的每一个焊盘组包括连接焊盘;并且
所述多个结合线被配置为将所述多个焊盘组中的一个焊盘组的所述连接焊盘连接至所述多个焊盘组中的另一个焊盘组的所述连接焊盘。
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