WO2022236764A1 - 电子装置 - Google Patents

电子装置 Download PDF

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Publication number
WO2022236764A1
WO2022236764A1 PCT/CN2021/093544 CN2021093544W WO2022236764A1 WO 2022236764 A1 WO2022236764 A1 WO 2022236764A1 CN 2021093544 W CN2021093544 W CN 2021093544W WO 2022236764 A1 WO2022236764 A1 WO 2022236764A1
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WO
WIPO (PCT)
Prior art keywords
voltage
electrostatic discharge
voltage terminal
coupled
die
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Application number
PCT/CN2021/093544
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English (en)
French (fr)
Inventor
陈履安
徐建昌
Original Assignee
迪克创新科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 迪克创新科技有限公司 filed Critical 迪克创新科技有限公司
Priority to PCT/CN2021/093544 priority Critical patent/WO2022236764A1/zh
Priority to CN202180004747.2A priority patent/CN115623874A/zh
Publication of WO2022236764A1 publication Critical patent/WO2022236764A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present application relates to an electronic device, in particular to an electronic device capable of protecting the input and output interfaces on the package from electrostatic discharge.
  • Electrostatic discharge Electrostatic Discharge, ESD refers to the appearance of positive and negative charges on both sides of an insulating medium, and when the charge gradually accumulates, the voltage on both sides of the insulating medium is raised to a level beyond the load of the insulating medium. A phenomenon in which electrical breakdown occurs across an insulating medium, allowing current to pass through it.
  • an electrostatic discharge protection device is generally installed at the input and output interfaces of the chip to provide a discharge path for the electrostatic discharge.
  • a packaged chip may contain multiple dies, and multiple dies may be stacked or parallel. Packaged on a common substrate.
  • One of the objectives of the present application is to disclose an electronic device capable of protecting the input and output interfaces on the package from electrostatic discharge, so as to solve the above problems.
  • An embodiment of the invention provides an electronic device.
  • the electronic device includes a first crystal grain, a second crystal grain and a packaging structure.
  • the first die includes a first voltage terminal, a first circuit, a second voltage terminal, a second circuit, a first electrostatic discharge bus and a first electrostatic discharge protection element.
  • the first voltage terminal is used for providing a first voltage.
  • the first circuit is used for performing a first operation according to at least the first voltage.
  • the second voltage terminal is used for providing a second voltage.
  • the second circuit is used for performing a second operation according to at least the second voltage.
  • the first electrostatic discharge bus is coupled to the first voltage end and the second voltage end.
  • the first electrostatic discharge protection element is coupled between the first voltage terminal and the first electrostatic discharge bus.
  • the second die includes a third voltage terminal, a fourth voltage terminal, a third circuit, a fourth circuit, a second electrostatic discharge bus and a second electrostatic discharge protection element.
  • the third voltage terminal is used for providing a third voltage.
  • the fourth voltage terminal is used for providing a fourth voltage.
  • the third circuit is used for performing a third operation according to at least the third voltage.
  • the fourth circuit is used for performing a fourth operation according to at least the fourth voltage.
  • the second electrostatic discharge bus is coupled to the third voltage end and the fourth voltage end.
  • the second ESD protection element is coupled between the third voltage terminal and the second ESD bus.
  • the encapsulation structure is used to encapsulate the first die and the second die, and the encapsulation structure includes a plurality of electrical contacts.
  • the first electrostatic discharge bus and the second electrostatic discharge bus are inside the packaging structure, and are coupled through a first connection structure between the first die and the second die .
  • the electronic device of the present application can couple the electrostatic discharge buses in different crystal grains through the connection structure between the crystal grains, so as to provide an electrostatic leakage path between multiple voltage terminals of different crystal grains, so it can Protect the input and output interfaces on the package from electrostatic discharge.
  • FIG. 1 is a schematic diagram of the inside of the package of the electronic device of the present invention.
  • FIG. 2 is a schematic diagram of another package interior of the electronic device of the present invention.
  • FIG. 3 is a schematic diagram of another package interior of the electronic device of the present invention.
  • FIG. 4 is a circuit diagram of a first die and a second die of the electronic device shown in FIG. 1 .
  • FIG. 5 is a circuit diagram of an electronic device according to another embodiment of the present invention.
  • FIG. 6 is a circuit diagram of an electronic device according to another embodiment of the present invention.
  • FIG. 7 is a circuit diagram of an electronic device according to another embodiment of the present invention.
  • first and second features are in direct contact with each other; and may also include additional components are formed between the first and second features, such that the first and second features may not be in direct contact.
  • this disclosure may reuse reference symbols and/or labels in various embodiments. Such repetition is for the sake of brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms such as “below”, “below”, “below”, “above”, “above” and the like here may be for the convenience of explaining the The relationship between one component or feature shown with respect to another or more components or features.
  • These spatially relative terms are intended to cover various orientations of the device during use or operation in addition to the orientation depicted in the drawings.
  • the device may be otherwise positioned (eg, rotated 90 degrees or at other orientations) and these spatially relative descriptors should be construed accordingly.
  • FIG. 1 is a schematic diagram of the inside of a package of an electronic device 100 according to an embodiment of the present invention.
  • the electronic device 100 includes a first die 110 , a second die 120 and a packaging structure 130A.
  • the electronic device 100 can be packaged by using a Chip on Wafer on Substrate (CoWoS) packaging method.
  • the first die 110 and the second die 120 can be placed side by side on the substrate S1, and the conductive lines TL are arranged in the substrate S1, and can be correspondingly coupled to the first die 110 and the second die 120.
  • CoWoS Chip on Wafer on Substrate
  • the lower micro-bump (Micro Bump) MB therefore, the first die 110 and the second die 120 can be coupled to each other through the micro-bump MB and the line TL in the substrate S1 to transmit signals.
  • the packaging structure 130A can include a plurality of electrical contacts EP, so the electronic device 100 can be coupled with an external circuit through the electrical contacts EP on the packaging structure 130A.
  • the electrical contact EP can be, for example, a solder ball, but the present invention is not limited thereto.
  • the electrical contact EP can be, for example but not limited to, a metal pin or a metal pad.
  • FIG. 2 is a schematic diagram of another package interior of the electronic device 100 .
  • the electronic device 100 can be packaged by vertically stacking dies.
  • the first die 110 can be stacked above the second die 120, and the first die 110 can be correspondingly coupled to the TSVs in the second die 120 through the micro-bump MB underneath, so that the second die 110
  • the circuits in the first die 110 and the second die 120 can transmit signals to each other inside the package structure 130B.
  • FIG. 3 is a schematic diagram of another package interior of the electronic device 100 .
  • the electronic device 100 can be packaged by bonding dies.
  • the first die 110 can be bonded to the second die 120, and the first die 110 and the second die 120 can be coupled through a wafer hybrid bond and (Wafer Hybrid Bonding) structure HB , so that the circuits in the first die 110 and the second die 120 can transmit signals to each other.
  • wafer hybrid bond and (Wafer Hybrid Bonding) structure HB so that the circuits in the first die 110 and the second die 120 can transmit signals to each other.
  • the present invention does not limit the electronic device 100 to be packaged in the manner shown in FIG. 1, FIG. 2 and FIG.
  • the second die 120 is packaged in the package structure 130C, and the first die 110 and the second die 120 may also be connected through other suitable connection structures.
  • FIG. 4 is a circuit diagram of the first die 110 and the second die 120 .
  • the first die 110 may include a circuit 112 , voltage terminals NVDDA and NVSSA
  • the second die 120 may include a circuit 122 , voltage terminals NVDDB and NVSSB.
  • the voltage terminals NVDDA and NVSSA can provide the power required for the circuit 112 to perform operations
  • the voltage terminals NVDDB and NVSSB can provide the power required for the circuit 122 to perform operations.
  • the circuit 122 can receive the signal SIG1 generated by the circuit 112 through the connection structure CS1 between the first die 110 and the second die 120 .
  • the connecting structure CS1 may include, for example but not limited to, microbump MB and line TL in FIG. 1 , microbump MB and TSV in FIG. 2 , or wafer hybrid bond and structure HB in FIG. 3 .
  • the voltage terminals NVDDA, NVSSA, NVDDB and NVSSB can be respectively coupled to the corresponding electrical contacts EP1 , EP2 , EP3 and EP4 on the package structure 130 to receive external voltages.
  • the first die 110 may include an electrostatic discharge
  • the protection elements ESD1, ESD2, ESD3 and ESD4 provide a leakage path for electrostatic discharge.
  • the voltage terminal NVDDA can be coupled to the voltage terminal NVDDB through the ESD protection element ESD1 and the connection structure CS2, and can be coupled to the voltage terminal NVSSB through the ESD protection element ESD2 and the connection structure CS3.
  • the voltage terminal NVSSA can be coupled to the voltage terminal NVDDB through the ESD protection element ESD3 and the connection structure CS4, and can be coupled to the voltage terminal NVSSB through the ESD protection element ESD4 and the connection structure CS5.
  • the electrostatic charge can be discharged to the voltage terminal NVDDB through the leakage path formed by the electrostatic discharge protection device ESD1 and the connection structure CS2, or through the electrostatic discharge protection device
  • the leakage path formed by the ESD2 and the connection structure CS3 discharges the electrostatic charges to the voltage terminal NVSSB.
  • each ESD leakage path between the first die 110 and the second die 120 must pass through the corresponding connection structures CS2 to B between the first die 110 and the second die 120.
  • more circuits and voltage terminals are included in the first die 110 and the second die 120, more connection structures need to be provided correspondingly to provide ESD leakage paths, which makes the packaging process more complicated. The degree is increased, thereby reducing the yield rate of the electronic device 100 or affecting the performance of the electronic device 100 .
  • FIG. 5 is a circuit diagram of an electronic device 200 according to another embodiment of the present invention.
  • the electronic device 200 includes a first die 210 , a second die 220 and a packaging structure 230 .
  • the first die 210 and the second die 220 can be co-packaged in the same package structure, for example, by using FIG. 1 , FIG. 2 , FIG. 3 or other wafer-level packaging techniques. It should be noted that this is mainly to help readers understand the circuit and component connection relationship inside the electronic device 200, so the actual circuit layer wiring in the package structure is not specifically depicted in FIG. Personnel should be able to realize the corresponding circuit connection relationship in the package structure adopted according to the content in Figure 5 .
  • the first die 210 may include a first voltage terminal NV1 , a second voltage terminal NV2 , a first circuit 212 , a second circuit 214 , a first electrostatic discharge bus B1 and a first electrostatic discharge protection device ESD1 .
  • the first voltage terminal NV1 can provide a first voltage V1, and the first circuit 212 can perform a first operation according to at least the first voltage V1.
  • the second voltage terminal NV2 can provide the second voltage V2, and the second circuit 214 can perform the second operation according to at least the second voltage V2.
  • the first electrostatic discharge bus B1 can be coupled to the first voltage terminal NV1 and the second voltage terminal NV2, and the first electrostatic discharge protection device ESD1 can be coupled between the first voltage terminal NV1 and the first electrostatic discharge bus B1 .
  • the second die 220 may include a third voltage terminal NV3 , a fourth voltage terminal NV4 , a third circuit 222 , a fourth circuit 224 , a second electrostatic discharge bus B2 and a second electrostatic discharge protection device ESD2 .
  • the third voltage terminal NV3 can provide a third voltage V3, and the fourth voltage terminal NV4 can provide a fourth voltage V4.
  • the third circuit 222 can perform the third operation according to at least the third voltage V3, and the fourth circuit 224 can perform the fourth operation according to at least the fourth voltage V4.
  • the second electrostatic discharge bus B2 can be coupled to the third voltage terminal NV3 and the fourth voltage terminal NV4, and the second electrostatic discharge protection device ESD2 can be coupled between the third voltage terminal NV3 and the second electrostatic discharge bus B2 .
  • the first die 210 may further include a third electrostatic discharge protection device ESD3, and the third electrostatic discharge protection device ESD3 may be coupled between the second voltage terminal NV2 and the first electrostatic discharge bus B1
  • the second die 220 may further include a fourth electrostatic discharge protection device ESD4, and the fourth electrostatic discharge protection device ESD4 may be coupled between the fourth voltage terminal NV4 and the second electrostatic discharge bus B2.
  • the first electrostatic discharge bus B1 and the second electrostatic discharge bus B2 can be coupled within the packaging structure 230 through the first connection structure CS1 between the first die 210 and the second die 220.
  • the first connection structure CS1 may include at least one of micro-bumps, TSVs, and wafer hybrid bonds and structures according to the packaging method used.
  • the first circuit 212 and the third circuit 222 can be coupled inside the package structure 230 through the second connection structure CS2 between the first die 210 and the second die 220, and the first circuit 212 and The third circuit 222 can transmit signals through the second connection structure CS2.
  • the second circuit 214 and the fourth circuit 224 are coupled inside the package structure 230 through the third connection structure CS3 between the first die 210 and the second die 220, and the second circuit 214 and the fourth circuit 224 can transmit signals through the third connection structure CS3.
  • the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3 and the fourth voltage terminal NV4 can be coupled to the electrical contacts EP1, EP2, EP3 and EP4 of the package structure 230 to receive The external voltage or the ground terminal coupled to the outside, in this case, if the package structure 230 is in contact with the object or due to other conditions, there is electrostatic charge accumulated on the electrical contact, it may be on the first voltage terminal NV1, Electrostatic discharge events are generated on the second voltage terminal NV2 , the third voltage terminal NV3 and the fourth voltage terminal NV4 .
  • the electrostatic discharge protection components ESD1, ESD2, ESD3, and ESD4 and the electrostatic discharge bus B1, B2 can be connected between the first voltage terminal NV1 and the second voltage terminal NV2 of the first crystal grain 210 and the second voltage terminal NV2 of the second crystal grain 220
  • Multiple leakage paths can be provided between the three voltage terminals NV3 and the fourth voltage terminal NV4, thus reducing or avoiding leakage currents on the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3 and the fourth voltage terminal NV4
  • the electrostatic discharge current passes through the first circuit 212, the second circuit 214, the third circuit 222 and the fourth circuit 224, so that the first circuit 212, the second circuit 214, the third circuit 222 and the fourth circuit 224 are protected.
  • ESD protection can be provided at the I/O interface between the first die 210 and the second die 220, that is, the On-Package Input/Output (OPIO) on the package.
  • OPIO On-Package
  • the electronic device 200 can respectively couple the first voltage terminal NV1 and the second voltage terminal NV2 to the first electrostatic discharge bus B1 through the electrostatic discharge protection elements ESD1 and ESD3, and can respectively pass through the electrostatic discharge protection elements ESD2 and ESD4
  • the third voltage terminal NV3 and the fourth voltage terminal NV4 are coupled to the second electrostatic discharge bus B2, so multiple discharge paths can be provided only through the first connection structure CS1, without the need for the first die 210 and Multiple connection structures are provided between the second dies 220 , thereby simplifying the packaging process and helping to improve the yield of the electronic device 200 .
  • the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3, and the fourth voltage terminal NV4 can provide different operating voltages greater than the ground voltage.
  • the electrostatic discharge protection device ESD1 , ESD2 , ESD3 and ESD4 may include at least one of a diode, an NMOS transistor, a PMOS transistor, a bipolar junction transistor, and a silicon controlled rectifier.
  • the first electrostatic discharge protection device ESD1 is implemented by a diode
  • the anode of the diode can be coupled to the first voltage terminal NV1
  • the cathode of the diode can be coupled to the first electrostatic discharge bus B1 .
  • N-type metal-oxide-semiconductor transistors P-type metal-oxide-semiconductor transistors, or bipolar junction Metal-oxide-semiconductor transistors or bipolar junction transistors are, for example, diode-connected transistors.
  • the first voltage terminal NV1, the second voltage terminal NV2, the third voltage terminal NV3, and the fourth voltage terminal NV4 may be different ground terminals.
  • the electrostatic discharge protection device ESD1 , ESD2, ESD3, and ESD4 may include at least two diodes connected back to back (back-to-back diodes), N-type metal-oxide-semiconductor transistors, P-type metal-oxide-semiconductor transistors, bipolar junction transistors, and silicon controlled rectifiers.
  • the NMOS transistor, the PMOS transistor, and the BJT can be connected in the form of two back-to-back diodes, for example.
  • each of the circuits 212, 214, 222 and 224 can receive at least one set of operating voltage and ground voltage, so other voltage terminals can be included in the first die 210 and the second die 220,
  • the electronic device 200 can also be coupled to different voltage terminals through the electrostatic discharge bus in a similar manner, and the first die 210 and the second die 220 can be connected through the connection structure between the first die 210 and the second die 220 .
  • the electrostatic discharge busses in the two dies 220 are coupled to provide more discharge discharge paths to achieve a more complete protection effect.
  • FIG. 6 is a schematic diagram of an electronic device 300 according to another embodiment of the present invention.
  • the electronic device 300 has a similar structure to the electronic device 200, and can operate according to a similar principle.
  • the first die 310 can also include a fifth voltage terminal NV5, a sixth voltage terminal NV6, a third electrostatic terminal Discharge bus B3, electrostatic discharge protection components ESD5, ESD7, SD9, ESD10 and ESD11.
  • the second die 320 may further include a seventh voltage terminal NV7 , an eighth voltage terminal NV8 , a fourth electrostatic discharge bus B4 , and electrostatic discharge protection elements ESD6 , ESD8 , ESD12 , ESD13 and ESD14 .
  • the fifth voltage terminal NV5 can provide the fifth voltage V5 to the first circuit 312
  • the sixth voltage terminal NV6 can provide the sixth voltage V6 to the second circuit 314
  • the third electrostatic discharge bus B3 can be coupled to the fifth voltage terminal NV5 and the sixth voltage terminal NV6
  • the fifth electrostatic discharge protection device ESD5 can be coupled between the fifth voltage terminal NV5 and the third electrostatic discharge bus B3, and the seventh electrostatic discharge protection device ESD7 can be coupled between the first voltage terminal NV1 and the fifth voltage terminal NV5 between.
  • the ninth electrostatic discharge protection device ESD9 can be coupled between the sixth voltage terminal NV6 and the third electrostatic discharge bus B3, and the tenth electrostatic discharge protection device ESD10 can be coupled between the second voltage terminal NV2 and the sixth voltage terminal Between NV6.
  • the eleventh electrostatic discharge protection device ESD11 can be coupled between the first electrostatic discharge bus B1 and the third electrostatic discharge bus B3.
  • the seventh voltage terminal NV7 can provide the seventh voltage V7 to the third circuit 322
  • the eighth voltage terminal NV8 can provide the eighth voltage V8 to the fourth circuit 324
  • the fourth electrostatic discharge bus B4 can be coupled to the seventh voltage terminal NV7 and the eighth voltage terminal NV8
  • the sixth electrostatic discharge protection device ESD6 can be coupled between the seventh voltage terminal NV7 and the fourth electrostatic discharge bus B4, and the eighth electrostatic discharge protection device ESD8 can be coupled between the third voltage terminal NV3 and the seventh voltage terminal NV7 between.
  • the twelfth electrostatic discharge protection device ESD12 can be coupled between the second electrostatic discharge bus B2 and the fourth electrostatic discharge bus B4 .
  • the thirteenth electrostatic discharge protection element ESD13 can be coupled between the eighth voltage terminal NV8 and the fourth electrostatic discharge bus B4, and the fourteenth electrostatic discharge protection element ESD14 can be coupled between the fourth voltage terminal NV4 and the eighth voltage terminal NV4. between voltage terminals NV8.
  • the third electrostatic discharge bus B3 and the fourth electrostatic discharge bus B4 are inside the packaging structure of the electronic device 300 and pass through the fourth connection structure between the first die 310 and the second die 320 CS4 is coupled.
  • the fifth voltage terminal NV5, the sixth voltage terminal NV6, the seventh voltage terminal NV7 and the eighth voltage terminal NV8 may be different ground terminals, while the first voltage terminal NV1 and the second voltage terminal NV2 ,
  • the third voltage terminal NV3 and the fourth voltage terminal NV4 may be operating voltage terminals. That is, the first voltage V1 may be greater than the fifth voltage V5, the second voltage V2 may be greater than the sixth voltage V6, the third voltage V3 may be greater than the seventh voltage V7, and the fourth voltage V4 may be greater than the eighth voltage V8.
  • the electrostatic discharge buses B1, B2, B3, and B4 and the electrostatic discharge protection devices ESD1 to ESD14 can provide a leakage path between any two voltage terminals of the eight voltage terminals NV1 to NV8, thereby protecting the first Circuit 312, second circuit 314, third circuit 322, and fourth circuit 324 provide more complete protection.
  • the electrostatic discharge protection elements ESD3, ESD12, and ESD13 will be turned on, so that the electrostatic discharge current will flow from the second voltage terminal NV2 flows through the third ESD protection element ESD3, flows into the second die 320 through the first connection structure CS1, and flows into the eighth voltage terminal NV8 through the twelfth ESD protection element ESD12 and the thirteenth ESD protection element ESD13 . In this way, damage to the second circuit 314 and the fourth circuit 324 caused by the electrostatic discharge current passing through the second circuit 314 and the fourth circuit 324 can be avoided.
  • the eleventh ESD protection element ESD11 and the twelfth ESD protection element ESD12 may include N-type metal oxide semiconductor transistors, P-type metal oxide semiconductor transistors or bipolar junction transistors.
  • the eleventh electrostatic discharge protection element ESD11 is arranged between the electrostatic discharge bus BS1 and BS3
  • the twelfth electrostatic discharge protection element ESD12 is arranged between the electrostatic discharge bus BS2 and BS4, so the eleventh The electrostatic discharge protection element ESD11 and the twelfth electrostatic discharge protection element ESD12 have a higher probability of being turned on, and therefore in some embodiments, the eleventh electrostatic discharge protection element ESD11 and the twelfth electrostatic discharge protection element ESD12 can include a response speed Faster active ESD clamps for ESD protection.
  • the active electrostatic discharge clamp can include a detection circuit and a transistor.
  • the detection circuit can detect voltage through components such as resistors and capacitors, and when the voltage is greater than a predetermined value, the transistor will be turned on in real time, so that electrostatic discharge can be quickly formed the leakage path.
  • the first voltage terminal NV1 and the second voltage terminal NV2 can be used to provide different voltages respectively, so they will be coupled to different electrical contacts on the package structure 330 to receive corresponding power supply.
  • the first voltage terminal NV1 and the second voltage terminal NV2 can also be coupled to the package structure 330 The same electrical contacts, at this time the first voltage terminal NV1 and the second voltage terminal NV2 will actually have the same potential, so one of the electrostatic discharge protection devices ESD1 and ESD3 can be omitted, at this time the first voltage terminal NV1 and the second voltage terminal NV2 can be coupled to the electrostatic discharge bus B1 through the same electrostatic discharge protection device.
  • one of the electrostatic discharge protection elements ESD2 and ESD4 can also be omitted.
  • the fifth voltage terminal NV5 and the sixth voltage terminal NV6 are coupled to the same electrical contact to share the same ground terminal, then one of the electrostatic discharge protection elements ESD5 and ESD9 can also be omitted, and So on and so forth.
  • the first electrostatic discharge bus B1, the second electrostatic discharge bus B2, the third electrostatic discharge bus B3 and the fourth electrostatic discharge bus B4 can be in floating state.
  • the electrostatic discharge buses B1, B2, B3 and B4 may also be coupled to the same electrical contacts on the package structure as some of the voltage terminals NV1 to NV8, so that the first die
  • the design of the die 310 and the second die 320 can be simplified, and the discharge speed of the electrostatic discharge inside the electronic device can be further improved.
  • FIG. 7 is a schematic diagram of an electronic device 400 according to another embodiment of the present invention.
  • the electronic device 400 has a similar structure to the electronic device 300 and can operate on a similar principle.
  • the first voltage terminal NV1 and the second voltage terminal NV2 may be coupled to corresponding electrical contacts EP1 and EP2 in the packaging structure 430 to receive the first voltage V1 and the second voltage V2 correspondingly.
  • the fifth voltage terminal NV5 and the sixth voltage terminal NV6 can be coupled to corresponding electrical contacts EP3 and EP4 in the package structure 430 to be coupled to corresponding ground terminals.
  • the first electrostatic discharge bus B1 of the first die 410 may be coupled to the same electrical contact of the package structure 430 as the voltage terminal providing a larger voltage among the first voltage terminal NV1 and the second voltage terminal NV2. point.
  • the third electrostatic discharge bus B3 and one of the fifth voltage terminal NV5 and the sixth voltage terminal NV6 can also be coupled to the same electrical contact of the package structure 430 .
  • the first electrostatic discharge bus B1 and the second voltage terminal NV2 can be jointly coupled to the electrical contact EP2.
  • the third electrostatic discharge bus B3 and the sixth voltage terminal NV6 are also coupled to the second electrical contact EP4 of the package structure 430 .
  • the second voltage terminal NV2 and the first electrostatic discharge bus B1 are actually coupled to the same potential, there is no need to provide an electrostatic discharge protection device between the two, and the sixth voltage terminal NV6 and the third The electrostatic discharge bus B3 is actually coupled to the same potential, so there is no need to provide an electrostatic discharge protection device between the two. That is to say, compared with the first die 310 in FIG.
  • the electrostatic protection elements ESD3, ESD9, and ESD10 can be omitted in the first die 410, while still being able to provide protection between each voltage terminal when an electrostatic discharge event occurs.
  • the leakage path is used to prevent the circuits 412, 414, 422 and 424 in the first die 410 and the second die 420 from being penetrated by the electrostatic discharge current and being damaged.
  • the electrostatic discharge bus lines B1 and B3 can be coupled to the same electrical contacts as the second voltage terminal NV2 and the sixth voltage terminal NV6 respectively, the discharge path can be provided more rapidly during electrostatic discharge without the need for Wait for the electrostatic protection device ESD3, ESD9 or ESD10 to be turned on.
  • the electronic device of the present invention can couple multiple different voltage terminals in each chip to the same electrostatic discharge bus through the electrostatic discharge protection element, and connect the phase terminals through the connection structure between the chips.
  • the electrostatic discharge busses in different dies are coupled, so as to provide electrostatic discharge paths between multiple voltage terminals of different dies, and achieve the protection effect of electrostatic discharge.
  • the electrostatic discharge bus can provide multiple electrostatic discharge paths between different voltage terminals, it can reduce the connection structures required between different dies, simplify the packaging process of electronic devices, and can also Improve the yield rate of electronic devices.

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Abstract

本申请公开了一种电子装置，包括第一晶粒、第二晶粒及封装结构。在第一晶粒中，第一电压端提供第一电路所需的第一电压，第二电压端提供第二电路所需的第二电压，第一静电泄流总线耦接于第一电压端及第二电压端，而第一静电放电保护件耦接于第一电压端及第一静电泄流总线之间。在第二晶粒中，第三电压端提供第三电路所需的第三电压，第四电压端提供第四电路所需的第四电压，第二静电泄流总线耦接于第三电压端及第四电压端，而第二静电放电保护件耦接于第三电压端及第二静电泄流总线之间。第一晶粒及第二晶粒设置在封装结构中，而第一静电泄流总线及第二静电泄流总线是在封装结构的内部，通过第一连接结构相耦接。

Description

电子装置 技术领域
本申请是有关于一种电子装置，尤其涉及一种能够对封装体上输入输出接口进行静电放电保护的电子装置。
背景技术
静电放电(Electro Static Discharge，ESD)是指在某一绝缘介质的两面分别出现正电荷和负电荷，并在电荷逐渐累积使得绝缘介质两面的电压被提升至超出绝缘介质可负荷的程度时，在绝缘介质上发生电击穿，继而使得电流能够通过的现象。
由于现今芯片的尺寸越来越小，因此芯片对于静电放电的耐受力也较低。为避免芯片中的电路在静电放电的过程中遭到破坏，一般会在芯片的输入输出接口处设置静电放电的保护装置以提供静电放电的泄流路径。此外，随着封装技术的进步，目前也已出现了将多个晶粒共同封装的技术，也就是说，一个封装芯片的内部可能包括多个晶粒，而多个晶粒可能以堆栈或并置于共同基板的方式封装。由于晶粒与晶粒之间的输入输出接口在互相连接的过程中，也可能会发生静电放电，因此必须在晶粒与晶粒之间的输入输出接口，也就是封装体上输入输出接口(On-Package Input/Output，OPIO)处设置静电放电保护装置。然而如此一来，将导致封装过程更加复杂，甚至降低整体良率。因此如何有效地对封装体上输入输出接口进行静电放电保护，便成为有待解决的问题。
发明内容
本申请的目的之一在于公开一种能够对封装体上输入输出接口进行静电放电保护的电子装置，来解决上述问题。
本发明的实施例提供一种电子装置。电子装置包括第一晶粒、第二晶粒及封装结构。第一晶粒包括第一电压端、第一电路、第二电压端、第二电路、第一静电泄流总线及第一静电放电保护件。第一电压端用以提供第一电压。第一电路用以依据至少所述第一电压执行第一操作。第二电压端用以提供第二电压。第二电路用以依据至少所述第二电压执行第二操作。第一静电泄流总线耦接于第一电压端及所述第二电压端。第一静电放电保护件耦接于所述第一电压端及所述第一静电泄流总线之间。第二晶粒包括第三电压端、第四电压端、第三电路、第四电路、第二静电泄流总线及第二静电放电保护件。第三电压端用以提供第三电压。第四电压端用以提供第四电压。第三电路用以依据至少所述第三电压执行第三操作。第四电路用以依据至少所述第四电压执行第四操作。第二静电泄流总线耦接于所述第三电压端及所述第四电压端。第二静电放电保护件耦接于所述第三电压端及所述第二静电泄流总线之间。封装结构用以封装所述第一晶粒及所述第二晶粒，所述封装结构包括多个电性触点。所述第一静电泄流总线及所述第二静电泄流总线是在所述封装结构的内部，通过所述第一晶粒及所述第二晶粒之间的第一连接结构相耦接。
本申请的电子装置可通过晶粒之间的连接结构将相异晶粒中的静电泄流总线相耦接，从而在相异晶粒的多个电压端之间提供静电泄流路径，因此可以对封装体上的输入输出接口进行静电放电保护。
附图说明
图1是本发明的电子装置的封装内部示意图。
图2是本发明的电子装置的另一封装内部示意图。
图3是本发明的电子装置的另一封装内部示意图。
图4是图1的电子装置的第一晶粒及第二晶粒的线路图。
图5是本发明另一实施例的电子装置的线路图。
图6是本发明另一实施例的电子装置的线路图。
图7是本发明另一实施例的电子装置的线路图。
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。这些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所 有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
图1是本发明一实施例的电子装置100的封装内部示意图。电子装置100包括第一晶粒110、第二晶粒120及封装结构130A。在图1中，电子装置100可利用基板上晶圆上芯片(Chip on Wafer on Substrate，CoWoS)的封装方式来进行封装。举例来说，第一晶粒110及第二晶粒120可并置于基板S1上，基板S1中布有导电线路TL，并可对应地耦接至第一晶粒110及第二晶粒120下方的微凸块(Micro Bump)MB，因此第一晶粒110及第二晶粒120之间可以通过微凸块MB以及基板S1中的线路TL来互相耦接以传输信号。此外，封装结构130A可包括多个电性触点EP，因此电子装置100可以通过封装结构130A上的电性触点EP与外部的电路相耦接。在图1中电性触点EP可例如为焊接球，然而本发明并不以此为限，在有些其他实施例中，电性触点EP可例如但不限于是金属引脚或金属垫。
图2是电子装置100的另一封装内部示意图。在图2中，电子装置100可利用垂直堆栈晶粒的方式来进行封装。举例来说，第一晶粒110可堆栈在第二晶粒120上方，而第一晶粒110可通过下方的微凸块MB与第二晶粒120中的硅穿孔TSV对应耦接，使得第一晶粒110与第二晶粒120中的电路能够在封装结构130B的内部互相传输信号。
图3是电子装置100的另一封装内部示意图。在图2中，电子装置100可利用黏接晶粒的方式来进行封装。举例来说，第一晶粒110可与第二晶粒120相黏合，而第一晶粒110及第二晶粒120之间可以通过晶圆混合键和(Wafer Hybrid Bonding)结构HB相耦接，使得第一 晶粒110与第二晶粒120中的电路能够互相传输信号。
本发明并不限定电子装置100是以图1、图2及图3中的方式进行封装，在有些实施例中，电子装置100也可以利用其他晶圆级封装的技术将第一晶粒110及第二晶粒120封装于封装结构130C中，而第一晶粒110及第二晶粒120之间也可能会通过其他适合的连接结构来相连接。
图4是第一晶粒110及第二晶粒120的线路图。在图4中，第一晶粒110可包括电路112、电压端NVDDA及NVSSA，而第二晶粒120可包括电路122、电压端NVDDB及NVSSB。在图4中，电压端NVDDA及NVSSA可提供电路112执行操作时所需的电源，而电压端NVDDB及NVSSB可提供电路122执行操作时所需的电源。此外，电路122可通过第一晶粒110及第二晶粒120之间的连接结构CS1接收电路112所产生的信号SIG1。连接结构CS1可例如但不限于包括图1中的微凸块MB及线路TL、图2中的微凸块MB及硅穿孔TSV或图3中的晶圆混合键和结构HB。
此外，在图4中，电压端NVDDA、NVSSA、NVDDB及NVSSB可分别耦接至封装结构130上的对应的电性触点EP1、EP2、EP3及EP4以接收外部电压。在此情况下，为了避免在电压端NVDDA、NVSSA、NVDDB及NVSSB上发生静电放电事件时，静电放电电流流经电路112或122而导致电路112或122损坏，第一晶粒110可包括静电放电保护件ESD1、ESD2、ESD3及ESD4以提供静电放电的泄流路径。
举例来说，电压端NVDDA可通过静电放电保护件ESD1及连接结构CS2耦接至电压端NVDDB，并可通过静电放电保护件ESD2及连接结构CS3耦接至电压端NVSSB。相似地，电压端NVSSA可通过静电放电保护件ESD3及连接结构CS4耦接至电压端NVDDB，并可通过静电放电保护件ESD4及连接结构CS5耦接至电压端NVSSB。如此一来，当电压端NVDDA上产生异常的高电压时，便可通过静电放电保护件ESD1及连接结构CS2所形成的泄流路径，将静 电电荷放电至电压端NVDDB，或通过静电放电保护件ESD2及连接结构CS3所形成的泄流路径，将静电电荷放电至电压端NVSSB。
然而，在图4中，第一晶粒110及第二晶粒120之间的每一条静电放电泄流路径都必须通过第一晶粒110及第二晶粒120之间对应的连接结构CS2至CS5。在此情况下，若第一晶粒110及第二晶粒120中还包括更多电路及电压端，就需要对应地设置更多的连接结构来提供静电放电泄流路径，使得封装程序的复杂度提高，从而降低了电子装置100的良率或影响电子装置100的性能。
图5是本发明另一实施例的电子装置200的线路图，电子装置200包括第一晶粒210、第二晶粒220及封装结构230。在有些实施例中，第一晶粒210及第二晶粒220可例如以图1、图2、图3或其他晶圆级封装的技术以共同封装在同一封装结构中。须注意的是，此处主要是为帮助读者理解电子装置200内部的电路及组件连接关系，因此在图5中并未具体描绘出在封装结构中实际的电路层走线，惟本领域的技术人员应能够依据图5的内容，在所采用的封装结构中实现对应的电路连接关系。
在图5中，第一晶粒210可包括第一电压端NV1、第二电压端NV2、第一电路212、第二电路214、第一静电泄流总线B1及第一静电放电保护件ESD1。
第一电压端NV1可提供第一电压V1，而第一电路212可依据至少第一电压V1执行第一操作。第二电压端NV2可提供第二电压V2，而第二电路214可依据至少第二电压V2执行第二操作。第一静电泄流总线B1可耦接于第一电压端NV1及第二电压端NV2，且第一静电放电保护件ESD1可耦接于第一电压端NV1及第一静电泄流总线B1之间。
第二晶粒220可包括第三电压端NV3、第四电压端NV4、第三电路222、第四电路224、第二静电泄流总线B2及第二静电放电保护件ESD2。
第三电压端NV3可提供第三电压V3，第四电压端NV4可以提供第四电压V4。第三电路222可以依据至少第三电压V3执行第三操作，而第四电路224可依据至少第四电压V4执行第四操作。第二静电泄流总线B2可耦接于第三电压端NV3及第四电压端NV4，而第二静电放电保护件ESD2可耦接于第三电压端NV3及第二静电泄流总线B2之间。
此外，在本实施例中，第一晶粒210还可包括第三静电放电保护件ESD3，第三静电放电保护件ESD3可耦接于第二电压端NV2及第一静电泄流总线B1之间，而第二晶粒220还可包括第四静电放电保护件ESD4，第四静电放电保护件ESD4可耦接于第四电压端NV4及第二静电泄流总线B2之间。
在图5中，第一静电泄流总线B1及第二静电泄流总线B2可在封装结构230的内部，通过第一晶粒210及第二晶粒220之间的第一连接结构CS1相耦接，第一连接结构CS1可依据所使用的封装方式而包括微凸块、硅穿孔及晶圆混合键和结构中的至少一者。再者，第一电路212与第三电路222可在封装结构230的内部，通过第一晶粒210及第二晶粒220之间的第二连接结构CS2相耦接，且第一电路212及第三电路222可通过第二连接结构CS2传输信号。第二电路214与第四电路224是在封装结构230的内部，通过第一晶粒210及第二晶粒220之间的第三连接结构CS3相耦接，且第二电路214及第四电路224可通过第三连接结构CS3传输信号。
在本实施例中，第一电压端NV1、第二电压端NV2、第三电压端NV3及第四电压端NV4可以耦接至封装结构230的电性触点EP1、EP2、EP3及EP4以接收外部电压或耦接至外部的接地端，在此情况下，若因为封装结构230与物体接触或因为其他状况导致在电性触点上有静电电荷累积，就可能会在第一电压端NV1、第二电压端NV2、第三电压端NV3及第四电压端NV4上产生静电放电事件。此时，由于静电放电保护件ESD1、ESD2、ESD3及ESD4及静电泄流总线B1、B2可以在第一晶粒210的第一电压端NV1及第二电压端NV2与第 二晶粒220的第三电压端NV3及第四电压端NV4之间可提供多条泄流路径，因此可以减少或避免在第一电压端NV1、第二电压端NV2、第三电压端NV3及第四电压端NV4上的静电放电电流通过第一电路212、第二电路214、第三电路222及第四电路224，使得第一电路212、第二电路214、第三电路222及第四电路224获得保护。如此一来，便可在第一晶粒210与第二晶粒220之间的输入输出接口处，也就是封装体上输入输出接口(On-Package Input/Output，OPIO)处提供静电放电保护。
此外，由于电子装置200可分别通过静电放电保护件ESD1及ESD3将第一电压端NV1及第二电压端NV2耦接至第一静电泄流总线B1，并可分别通过静电放电保护件ESD2及ESD4将第三电压端NV3及第四电压端NV4耦接至第二静电泄流总线B2，因此仅需要通过第一连接结构CS1就能够提供多条泄流路径，而无须在第一晶粒210及第二晶粒220之间设置多个连接结构，从而简化了封装程序，并有助于提高电子装置200的良率。
在有些实施例中，第一电压端NV1、第二电压端NV2、第三电压端NV3及第四电压端NV4可以提供大于地电压的相异操作电压，在此情况下，静电放电保护件ESD1、ESD2、ESD3及ESD4可包括二极管、N型金氧半晶体管、P型金氧半晶体管、双极结型晶体管及可控硅整流器中的至少一者。举例来说，若第一静电放电保护件ESD1是以二极管来实作，则可将二极管的阳极耦接至第一电压端NV1，并将二极管的阴极耦接至第一静电泄流总线B1。如此一来，在正常情况下，将不会有电流自第一静电泄流总线B1流入第一电压端NV1，而在静电放电事件发生时，且当第一静电泄流总线B1的电压大于第一电压V1并超过二极管的崩溃电压时，第一静电放电保护件ESD1才会导通，而在第一静电泄流总线B1与第一电压端NV1之间形成泄流路径。相似地，在有些实施例中，当利用N型金氧半晶体管、P型金氧半晶体管或双极结型晶体管来实作静电放电保护件时，可将N型金氧半晶体管、P型金氧半晶体管或双极结型晶体管例如以二极管的形式连接(diode-connected transistor)。
此外，在有些其他实施例中，第一电压端NV1、第二电压端NV2、第三电压端NV3及第四电压端NV4可以是相异的接地端，在此情况下，静电放电保护件ESD1、ESD2、ESD3及ESD4可包括背对背连接的两个二极管(back-to-back diodes)、N型金氧半晶体管、P型金氧半晶体管、双极结型晶体管及可控硅整流器中的至少一者，其中N型金氧半晶体管、P型金氧半晶体管、双极结型晶体管可例如以背对背的两个二极管形式来连接。
再者，一般来说，电路212、214、222及224各自可接收到至少一组操作电压及地电压，因此在第一晶粒210及第二晶粒220中还可包括其他的电压端，而电子装置200也可以利用相似的方式通过静电泄流总线耦接至相异的电压端，并通过第一晶粒210及第二晶粒220之间的连接结构将第一晶粒210及第二晶粒220中的静电泄流总线相耦接，以提供更多条放电泄流路径，达到更加完善的保护效果。
图6是本发明另一实施例的电子装置300的示意图。电子装置300与电子装置200具有相似的结构，并可依据相似的原理操作，然而在电子装置300中，第一晶粒310还可包括第五电压端NV5、第六电压端NV6、第三静电泄流总线B3、静电放电保护件ESD5、ESD7、SD9、ESD10及ESD11。第二晶粒320还可包括第七电压端NV7、第八电压端NV8、第四静电泄流总线B4、静电放电保护件ESD6、ESD8、ESD12、ESD13及ESD14。
在第一晶粒310中，第五电压端NV5可以提供第五电压V5至第一电路312，而第六电压端NV6可提供第六电压V6至第二电路314。第三静电泄流总线B3可耦接于第五电压端NV5及第六电压端NV6。第五静电放电保护件ESD5可耦接于第五电压端NV5及第三静电泄流总线B3之间，而第七静电放电保护件ESD7可耦接于第一电压端NV1及第五电压端NV5之间。第九静电放电保护件ESD9可耦接于第六电压端NV6及第三静电泄流总线B3之间，而第十静电放垫保护件ESD10可耦接于第二电压端NV2及第六电压端NV6之间。此外，第十一静电放电保护件ESD11可耦接于第一静电泄流总线B1及第三 静电泄流总线B3之间。
在第二晶粒320中，第七电压端NV7可提供第七电压V7至第三电路322，而第八电压端NV8可提供第八电压V8至第四电路324。第四静电泄流总线B4可耦接于第七电压端NV7及第八电压端NV8。第六静电放电保护件ESD6可耦接于第七电压端NV7及第四静电泄流总线B4之间，而第八静电放电保护件ESD8可耦接于第三电压端NV3及第七电压端NV7之间。此外，第十二静电放电保护件ESD12可耦接于第二静电泄流总线B2及第四静电泄流总线B4之间。第十三静电放电保护件ESD13可耦接于第八电压端NV8及第四静电泄流总线B4之间，而第十四静电放垫保护件ESD14可耦接于第四电压端NV4及第八电压端NV8之间。
在本实施例中，第三静电泄流总线B3及第四静电泄流总线B4是在电子装置300的封装结构内部，通过第一晶粒310及第二晶粒320之间的第四连接结构CS4相耦接。此外，在图5中，第五电压端NV5、第六电压端NV6、第七电压端NV7及第八电压端NV8可以是相异的接地端，而第一电压端NV1、第二电压端NV2、第三电压端NV3及第四电压端NV4可以是操作电压端。也就是说，第一电压V1可大于第五电压V5，第二电压V2可大于第六电压V6，第三电压V3可大于第七电压V7，第四电压V4可大于第八电压V8。
在图6中，静电泄流总线B1、B2、B3及B4及静电放电保护件ESD1至ESD14可以在八个电压端NV1至NV8中任意两个电压端之间提供泄流路径，从而对第一电路312、第二电路314、第三电路322及第四电路324提供更为完整的保护。举例来说，当第二电压端NV2及第八电压端NV8之间出现巨大的电压差时，静电放电保护件ESD3、ESD12及ESD13便会导通，因此静电放电电流将可自第二电压端NV2流经第三静电放电保护件ESD3，并通过第一连接结构CS1流入第二晶粒320，并通过第十二静电放电保护件ESD12及第十三静电放电保护件ESD13流入第八电压端NV8。如此一来，就可以避免静电放电电流通过第二电路314及第四电路324而造成第二电路314 及第四电路324的损坏。
在本实施例中，第十一静电放电保护件ESD11及第十二静电放电保护件ESD12可包括N型金氧半晶体管、P型金氧半晶体管或双极结型晶体管。此外，由于第十一静电放电保护件ESD11是设置在静电泄流总线BS1及BS3之间，而第十二静电放电保护件ESD12是设置在静电泄流总线BS2及BS4之间，因此第十一静电放电保护件ESD11及第十二静电放电保护件ESD12被导通的机率较高，也因此在有些实施例中，十一静电放电保护件ESD11及第十二静电放电保护件ESD12可包括反应速度较快的主动静电放电箝制器来进行静电放电保护。主动静电放电箝制器可包括侦测电路及晶体管，侦测电路可例如通过电阻及电容等组件来侦测电压，而当电压大于预定值时，便会实时导通晶体管，因此可以迅速形成静电放电的泄流路径。
此外，在图6的实施例中，第一电压端NV1及第二电压端NV2可分别用以提供相异的电压，因此会耦接至封装结构330上的相异电性触点以接收对应的电源供应。然而，在有些实施例中，若第一电压端NV1及第二电压端NV2是用以提供相同的电压，则第一电压端NV1及第二电压端NV2也可耦接至封装结构330上的相同电性触点，此时第一电压端NV1及第二电压端NV2实际上会具有相同的电位，因此可将静电放电保护件ESD1及ESD3中的其中一者省略，此时第一电压端NV1及第二电压端NV2可通过相同的静电放电保护件耦接至静电泄流总线B1。相似地，若第三电压端NV3及第四电压端NV4是用以提供相同的电压并耦接至相同的电性触点，则也可将静电放电保护件ESD2及ESD4中的其中一者省略；而若第五电压端NV5及第六电压端NV6是耦接至相同的电性触点以共享相同的接地端，则也可将静电放电保护件ESD5及ESD9中的其中一者省略，并依此类推。
再者，在图6的实施例中，在没有发生静电放电事件时，第一静电泄流总线B1、第二静电泄流总线B2、第三静电泄流总线B3及第四静电泄流总线B4可处在浮接状态。然而，在有些实施例中，静电泄流总线B1、B2、B3及B4也可与电压端NV1至NV8中部分的 电压端共同耦接至封装结构上的相同电性触点，使得第一晶粒310及第二晶粒320的设计能够更加简化，也可进一步提升电子装置内部的静电放电泄流速度。
图7是本发明另一实施例的电子装置400的示意图。电子装置400与电子装置300具有相似的结构，并可依据相似的原理操作。在电子装置400中，第一电压端NV1及第二电压端NV2可以耦接至封装结构430中对应的电性触点EP1及EP2以对应地接收第一电压V1及第二电压V2，此外，第五电压端NV5及第六电压端NV6可耦接至封装结构430中对应的电性触点EP3及EP4以耦接至对应的接地端。在此情况下，第一晶粒410的第一静电泄流总线B1可与第一电压端NV1及第二电压端NV2中提供较大电压的电压端耦接至封装结构430的相同电性触点。对应地，第三静电泄流总线B3也可与第五电压端NV5及第六电压端NV6中的其中一者耦接至封装结构430的相同电性触点。
举例来说，若第二电压V2大于第一电压V1，则第一静电泄流总线B1可与第二电压端NV2共同耦接至电性触点EP2。此时，第三静电泄流总线B3也可与第六电压端NV6耦接至封装结构430的第二电性触点EP4。在此情况下，由于第二电压端NV2与第一静电泄流总线B1实际上会耦接到相同的电位，因此两者之间无须设置静电放电保护件，而第六电压端NV6与第三静电泄流总线B3实际上也会耦接到相同的电位，因此两者之间也无须设置静电放电保护件。也就是说，相较于图6中的第一晶粒310，第一晶粒410中可省略静电保护件ESD3、ESD9及ESD10，而仍然能够在静电放电事件发生时，提供各个电压端之间的泄流路径，以避免第一晶粒410及第二晶粒420中的电路412、414、422及424被静电放电的电流贯穿而受到破坏。此外，由于静电泄流总线B1及B3可分别与第二电压端NV2及第六电压端NV6耦接至相同的电性触点，因此在静电放电时能够更加迅速地提供泄流路径，而无需等待静电保护件ESD3、ESD9或ESD10被导通。
综上所述，本发明的电子装置可以将每一晶粒中的多个相异电压 端通过静电放电保护件耦接至相同的静电泄流总线，并通过晶粒之间的连接结构将相异晶粒中的静电泄流总线相耦接，从而在相异晶粒的多个电压端之间提供静电泄流路径，并达到静电放电的保护效果。此外，由于静电泄流总线可以在相异的电压端之间提供多条静电泄流路径，因此可以减少相异晶粒之间所需的连接结构，使得电子装置的封装程序较为简化，也可提升电子装置的良率。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (16)

  1. 一种电子装置，其特征在于，包括：
    第一晶粒，包括：
    第一电压端，用以提供第一电压；
    第一电路，用以依据至少所述第一电压执行第一操作；
    第二电压端，用以提供第二电压；
    第二电路，用以依据至少所述第二电压执行第二操作；
    第一静电泄流总线，耦接于第一电压端及所述第二电压端；及
    第一静电放电保护件，耦接于所述第一电压端及所述第一静电泄流总线之间；
    第二晶粒，包括：
    第三电压端，用以提供第三电压；
    第四电压端，用以提供第四电压；
    第三电路，用以依据至少所述第三电压执行第三操作；
    第四电路，用以依据至少所述第四电压执行第四操作；
    第二静电泄流总线，耦接于所述第三电压端及所述第四电压端；及
    第二静电放电保护件，耦接于所述第三电压端及所述第二静电泄流总线之间；及
    封装结构，用以封装所述第一晶粒及所述第二晶粒，所述封装结构包括多个电性触点；
    其中所述第一静电泄流总线及所述第二静电泄流总线是在所述封装结构的内部，通过所述第一晶粒及所述第二晶粒之间的第一连接结构相耦接。
  2. 如权利要求1所述的电子装置，其中：
    所述第一晶粒与所述第二晶粒是并置在相同基板上、堆栈在相同 基板上或彼此相黏以共同封装在封装结构中；及
    所述第一连接结构包括微凸块、硅穿孔及晶圆混合键和结构中的至少一者。
  3. 如权利要求1所述的电子装置，其中：
    所述第三电路与所述第一电路是在所述封装结构的内部，通过所述第一晶粒及所述第二晶粒之间的第二连接结构相耦接，且所述第一电路及所述第三电路是通过所述第二连接结构传输信号；及
    所述第二电路与所述第四电路是在所述封装结构的内部，通过所述第一晶粒及所述第二晶粒之间的第三连接结构相耦接，且所述第二电路及所述第四电路是通过所述第三连接结构传输信号。
  4. 如权利要求1所述的电子装置，其中：
    所述第一电压端、所述第二电压端、所述第三电压端及所述第四电压端是为相异的接地端；及
    所述第一静电放电保护件包括背对背连接的两个二极管、N型金氧半晶体管、P型金氧半晶体管、双极结型晶体管及可控硅整流器中的至少一者。
  5. 如权利要求1所述的电子装置，其中：
    所述第一电压、所述第二电压、所述第三电压及所述第四电压是大于地电压的相异操作电压；及
    所述第一静电放电保护件包括二极管、N型金氧半晶体管、P型金氧半晶体管、双极结型晶体管及可控硅整流器中的至少一者。
  6. 如权利要求1所述的电子装置，其中所述第一晶粒还包括第三静电放电保护件，耦接于所述第二电压端及所述第一静电泄流总线之间。
  7. 如权利要求1至6任一项所述的电子装置，其中所述第二晶粒还包括第四静电放电保护件，耦接于所述第四电压端及所述第二静电泄流总线之间。
  8. 如权利要求1所述的电子装置，其中：
    所述第一晶粒还包括：
    第五电压端，用以提供第五电压至所述第一电路；
    第六电压端，用以提供第六电压至所述第二电路；
    第三静电泄流总线，耦接于第五电压端及所述第六电压端；
    第五静电放电保护件，耦接于所述第五电压端及所述第三静电泄流总线之间；
    所述第二晶粒还包括：
    第七电压端，用以提供第七电压至所述第三电路；
    第八电压端，用以提供第八电压至所述第四电路；
    第四静电泄流总线，耦接于第七电压端及第八电压端；
    第六静电放电保护件，耦接于所述第七电压端及所述第四静电泄流总线之间；
    所述第三静电泄流总线及所述第四静电泄流总线是在所述封装结构的内部，通过所述第一晶粒及所述第二晶粒之间的第四连接结构相耦接。
  9. 如权利要求8所述的电子装置，其中：
    所述第五电压端、所述第六电压端、所述第七电压端及所述第八电压端是相异的接地端；及
    所述第一电压大于所述第五电压，所述第二电压大于所述第六电压，所述第三电压大于所述第七电压，所述第四电压大于所述第八电压。
  10. 如权利要求9所述的电子装置，其中：
    所述第一晶粒还包括第七静电放电保护件，耦接于所述第一电压端及所述第五电压端之间；及
    所述第二晶粒还包括第八静电放电保护件，耦接于所述第三电压端及所述第七电压端之间。
  11. 如权利要求9所述的电子装置，其中：
    所述第一静电泄流总线耦接至所述封装结构的所述多个电性触点中的第一电性触点；及
    所述第三静电泄流总线耦接至所述封装结构的所述多个电性触点中的第二电性触点。
  12. 如权利要求11所述的电子装置，其中：
    所述第二电压大于所述第一电压；
    所述第一电性触点是用以接收外部提供的所述第二电压；及
    所述第二电性触点是用以接收外部提供的所述第六电压。
  13. 如权利要求8所述的电子装置，其中：
    所述第一静电泄流总线、所述第二静电泄流总线、所述第三静电泄流总线及所述第四静电泄流总线是处在浮接状态。
  14. 如权利要求8所述的电子装置，其中所述第一晶粒还包括：
    第三静电放电保护件，耦接于所述第二电压端及所述第一静电泄流总线之间
    第九静电放电保护件，耦接于所述第六电压端及所述第三静电泄流总线之间；及
    第十静电放垫保护件，耦接于所述第二电压端及所述第六电压端之间。
  15. 如权利要求8所述的电子装置，其中：
    所述第一晶粒还包括第十一静电放电保护件，耦接于所述第一静电泄流总线及所述第三静电泄流总线之间；及
    所述第二晶粒还包括第十二静电放电保护件，耦接于所述第二静电泄流总线及所述第四静电泄流总线之间。
  16. 如权利要求15所述的电子装置，其中所述第十一静电放电保护件包括N型金氧半晶体管、P型金氧半晶体管、双极结型晶体管及主动静电放电箝制器中的至少一者。
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