TW201923975A - 半導體結構的形成方法 - Google Patents
半導體結構的形成方法 Download PDFInfo
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- TW201923975A TW201923975A TW107137954A TW107137954A TW201923975A TW 201923975 A TW201923975 A TW 201923975A TW 107137954 A TW107137954 A TW 107137954A TW 107137954 A TW107137954 A TW 107137954A TW 201923975 A TW201923975 A TW 201923975A
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- 238000000034 method Methods 0.000 title claims abstract description 101
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 116
- 239000002184 metal Substances 0.000 claims abstract description 116
- 238000000151 deposition Methods 0.000 claims abstract description 75
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- 235000012431 wafers Nutrition 0.000 description 20
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- 239000011733 molybdenum Substances 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
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- 239000010955 niobium Substances 0.000 description 1
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- 125000002524 organometallic group Chemical group 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
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- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
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- 241000894007 species Species 0.000 description 1
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- CXXKWLMXEDWEJW-UHFFFAOYSA-N tellanylidenecobalt Chemical compound [Te]=[Co] CXXKWLMXEDWEJW-UHFFFAOYSA-N 0.000 description 1
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- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
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Abstract
本發明實施例說明改良間隙填充特性的金屬化製程方法。方法包括形成接點開口於氧化物層中,形成阻障層於接點開口中,形成襯墊層於阻障層上,以及形成第一金屬層於襯電層上以部份地填入接點開口。方法亦包括形成第二金屬層於第一金屬層上以填滿接點開口,其中形成第二金屬層的步驟包括以第一射頻功率與直流電功率濺鍍沉積第二金屬層,以第二射頻功率再流動第二金屬層。
Description
本發明實施例關於改良間隙填充的金屬化製程。
在製作積體電路時,由於接點開口所需的幾何形狀,充填接點開口的挑戰性越來越高。如此一來,沉積金屬以充填接點開口時難以不形成空洞或縫隙。接點中的空洞不符需求,因為空洞會增加接點電阻並負面地影響積體電路可信度。
本發明一實施例提供之半導體結構的形成方法,包括:形成接點開口於氧化物層中;沉積阻障層於接點開口中;沉積襯墊層於阻障層上;沉積第一金屬層於襯墊層上,以部份地填入接點開口;以及沉積第二金屬層於第一金屬層上,以填入開口,其中沉積第二金屬層的步驟包括:採用第一射頻功率與直流電功率濺鍍沉積第二金屬層;以及採用第二射頻功率再流動第二金屬層。
100‧‧‧方法
110、120、130、140、150、160、170‧‧‧步驟
200‧‧‧基板
210‧‧‧介電層
220‧‧‧閘極
230‧‧‧高介電常數的介電層
240‧‧‧間隔物
250‧‧‧蓋層
260‧‧‧源極/汲極磊晶層
300‧‧‧接點開口
400‧‧‧金屬
410‧‧‧阻障層
500‧‧‧矽化物層
600‧‧‧襯墊層
700、800‧‧‧金屬層
710‧‧‧開口
900‧‧‧物理氣相沉積反應器
910‧‧‧上表面
915‧‧‧磁體
920、930、980‧‧‧饋通連接器
940‧‧‧鈷靶材
950‧‧‧空間
960‧‧‧晶圓
970‧‧‧靜電座
990‧‧‧線圈磁體
1000‧‧‧金屬接點
圖1係一些實施例中,具有共沉積/再流動步驟的接點金屬化方法其流程圖。
圖2係一些實施例中,具有個別磊晶層埋置於基板上的介電層中的兩個相鄰閘極結構之剖視圖。
圖3係一些實施例中,在形成接點開口於介電層中之後,具有個別磊晶層埋置於基板上的介電層中的兩個相鄰閘極結構之剖視圖。
圖4係一些實施例中,在沉積金屬與阻障層於接點開口中之後,介電層中的接點開口之剖視圖。
圖5係一些實施例中,在形成矽化物於接點開口之底部之後,介電層中的接點開口剖視圖。
圖6係一些實施例中,在沉積襯墊層於接點開口中之後,介電層中的接點開口之剖視圖。
圖7係一些實施例中,在部份沉積鈷層於接點開口中之後,介電層中的接點開口之剖視圖。
圖8係一些實施例中,以共沉積與再流動製程沉積鈷層之後,介電層中的金屬接點之剖視圖。
圖9係一些實施例中,可獨立控制沉積金屬步驟的共沉積與再流動製程之物理氣相沉積反應器的剖視圖。
圖10係一些實施例中,在化學機械平坦化製程之後,介電層中的金屬接點之剖視圖。
可以理解的是,下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸,或兩者之間隔有其他額外構件而非直接接觸。此外,本發明之多種例子中可重複標號,但這些重複僅用以簡化與清楚說明,不代表不同實施例及/或設
置之間具有相同標號之單元之間具有相同的對應關係。
此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。元件亦可轉動90°或其他角度,因此方向性用語僅用以說明圖示中的方向。
用語「名義上(nominal)」是指用於構件或製程步驟所欲的目標,特性數值或參數,在產品的設計階段時己設定好,連同設定所欲數值的上下限範圍。數值的範圍一般來自於製程中的輕微變動或公差(tolerances)。
此處所述的用語「垂直」指的是名義上垂直於基板表面。
在製作晶片時,下層的內連線(又稱作金屬接點)可電性連接一或多場效電晶體的端點(如閘極、源極、及/或汲極端點)至上層內連線。金屬接點的形成方法可為蝕刻層間介電堆疊,以形成一或多個接點開口於電晶體的閘極與源極/汲極區的磊晶層上。將金屬填入接點開口,可形成金屬接點。形成金屬接點的步驟亦可稱作「接點金屬化」。
由於接點開口所需的幾何形狀,充填接點開口的挑戰性越來越高。舉例來說,接點開口的深寬比(由開口的深度與寬度之間的比例定義)可介於約3至約10之間(如6),開口頂部的關鍵尺寸小於約17nm,且開口底部的關鍵尺寸小於約14nm。與此同時,接點深度可大於約60nm。如此一來,金屬
沉積填入接點開口時難以不形成空洞或隙縫。接點中的空洞不符需求,因為空洞會增加接點電阻並負面地影響晶片可信度。舉例來說,後續的化學機械平坦化製程可能露出空洞,端視空洞的尺寸與接點中的位置而定。一旦露出空洞,化學機械平坦化製程的漿液將進入空洞並自接點移除金屬。
在金屬充填製程中,夾斷(pinch-off)為可能產生空洞於接點中的失效機制。當金屬沉積速率高而金屬沉積的時間不足以到達接點底部時,可能開始出現夾斷。如此一來,沉積的金屬累積於接點開口的頂部,而阻止沉積的金屬到達接點的底部。夾斷的另一個原因關於金屬充填製程時的接點輪廓。舉例來說,接點輪廓具有反向的頂部開口,其中開口的頂部關鍵尺寸小於中間的關鍵尺寸與底部的關鍵尺寸。在此例中,當金屬沉積速率夠低時,可能觸發夾斷的問題。
此處所述的實施例關於改良間隙填充的鈷金屬化製程。實施例可用於金屬充填接點,其深寬比可介於約3至約10之間,且其深度大於約60nm。舉例來說(但不限於此),本發明實施例包含共沉積與再流動的物理氣相沉積製程,其採用射頻功率以獨立地控制沉積金屬的沉積與再流動製程。
圖1為一些實施例中,金屬沉積的方法100之流程圖。金屬沉積的方法100說明形成鈷金屬於接點中的方法。舉例來說,接點的深寬比可介於約3至約10之間,且深度大於約60nm。在金屬沉積的方法100之多種步驟之間可進行其他製程步驟,不過此處未詳述其他步驟以求敘述清楚。金屬沉積的方法100並不限於圖1所示的步驟,而可能為其他替代方法。此
外,用於說明方法100的圖式僅用以舉例而不必依比例繪示。為了達到說明目的,可刻意增加一些結構、膜狀物、或幾何形狀。
方法100開始進行步驟110,提供介電層210形成其上的基板200,如圖2所示。在一些實施例中,基板亦稱作晶圓上的鰭狀結構。舉例來說,基板200可為晶圓上的半導體鰭狀物的部份。在一些實施例中,鰭狀物與晶圓的組成可為相同或不同材料。此外,基板200可為基體半導體晶圓上的鰭狀物,或絕緣層上矽晶圓上的鰭狀物。另一方面,基板200的組成可為矽或(i)另一半導體元素如鍺;(ii)半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦;(iii)半導體合金如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦;或(iv)上述之組合。
舉例來說,方法100中的基板200可描述為矽晶圓上的矽鰭狀物(如單晶矽)。本發明實施例亦可採用其他材料,此亦屬本發明實施例精神與範疇。
圖2包含額外結構,比如閘極220、高介電常數的介電層230、間隔物240、蓋層250、與源極/汲極磊晶層260。在一些實施例中,閘極220、高介電常數的介電層230、間隔物240、與蓋層250形成場效電晶體的閘極結構。此外,沿著相鄰的源極/汲極磊晶層之閘極結構可形成場效電晶體的端點。在一些實施例中,可形成較少或額外的閘極結構與源極/汲極磊晶層260於基板200上。因此閘極結構或源極/汲極磊晶層260的數目不限於圖2所示。在一些實施例中,源極/汲極磊晶層260
可為p型的磊晶成長矽鍺堆疊,或n型的摻雜碳之磊晶矽堆疊。在一些實施例中,介電層210可為層間介電層,其組成可為氧化矽、摻雜碳的氧化矽、氮氧化矽、碳氮氧化矽、碳化矽、碳氮化矽、或上述之組合。在一些實施例中,介電層210可為兩種或更多種介電材料的堆疊。介電層210可提供閘極220以及與閘極220相鄰之金屬接點之間的電型隔離。介電層210的沉積方法可為化學氣相沉積製程、可流動的化學氣相沉積製程、物理氣相沉積製程、或熱成長製程。
在一些實施例中,高介電常數的介電層230之沉積方法為原子層沉積,其厚度可介於約10Å至約20Å之間。在一些實施例中,高介電常數的介電層230可為氧化鉿、鉿矽酸鹽為主的材料、或介電常數大於3.9(氧化矽的介電常數,作為標準)的另一介電材料。
閘極220可為多層金屬堆疊,其可包含(i)用於高介電常數的介電層230之蓋層、(ii)一或多個金屬化層、(iii)功函數金屬堆疊、與(iv)金屬充填層。為簡化說明,圖2並未個別地顯示閘極220中的蓋層、一或多個金屬化層、功函數金屬堆疊、與金屬充填層。在一些實施例中,用於高介電常數的介電層230之蓋層之沉積方法為原子層沉積。舉例來說,原子層沉積可控制並成長順應性的層狀物至Å等級。在一些實施例中,用於高介電常數的介電層230的蓋層厚度可介於約5Å至約15Å之間。用於高介電常數的介電層230的蓋層可用以保護高介電常數的介電層230,使其免於後續製程步驟(如形成閘極220之一或多個金屬化層之步驟)的影響。在一些實施例中,用於高介電常
數的介電層230之蓋層可為鈦為主的材料。
閘極220中的金屬化層之數目與種類,取決於電晶體所需的臨界電壓。閘極220中的例示性金屬化層可包含氮化鉭底層與一或多個氮化鈦層。在一些實施例中,氮化鉭底層的沉積方法可為化學氣相沉積。舉例來說(但不限於此),氮化鉭底層的厚度可介於約10Å至約15Å之間。在一些實施例中,一或多個氮化鈦層的形成方法可為原子層沉積或擴散製程。舉例來說,原子層沉積製程所沉積的氮化鈦層厚度可介於約8Å至約12Å之間,而擴散製程所沉積的氮化鈦層較厚(其厚度介於約12Å至約50Å之間)。
在一些實施例中,功函數金屬堆疊可包含鈦/鋁的雙層或鈦鋁合金,其沉積方法均可為原子層沉積製程。舉例來說(但不限於此),功函數金屬堆疊的厚度可介於約20Å至約35Å之間。功函數金屬堆疊可調整金屬閘極的功函數,並影響電晶體的臨界電壓。一或多個氮化鈦層的厚度與數目搭配功函數金屬堆疊,可設定電晶體的臨界電壓。
在一些實施例中,金屬充填層可包含氮化鈦的阻障層與鎢金屬堆疊。氮化鈦阻障層的沉積可為原子層沉積。在沉積鎢金屬堆疊時,氮化鈦阻障層可保護下方的功函數金屬堆疊免於氟化學劑影響。在一些實施例中,氮化鈦阻障層的厚度可介於約40Å至約50Å之間。
在一些實施例中,蓋層250可為氮化物的蝕刻停止層,其於後續形成接點的步驟時可保護閘極220。在一些實施例中,蓋層250可為氮化矽。
在一些實施例中,間隔物240的組成可為介電材料如氧化矽、氮氧化矽、摻雜碳的氮化矽、碳氧化矽、或氮化矽。在一些實施例中,間隔物240的厚度可介於約2nm至約5nm之間。間隔物240可為一或多層相同或不同材料的堆疊。在一些實施例中,在形成源極/汲極磊晶層260於場效電晶體的源極/汲極區的頂部上時,間隔物240可作為對準遮罩。
方法100接著進行步驟120,形成接點開口於介電層210中。舉例來說,圖3顯示介電層210中的接點開口300。接點開口300的形成方法可採用光微影與蝕刻製程圖案化介電層210。舉例來說,可形成光阻塗層於介電層210上。可依據所需圖案顯影光阻。舉例來說,所需圖案可為介電層210中的開口以露出源極/汲極磊晶層260的部份。光阻層的未顯影區域可由濕式或乾式蝕刻製程剝除,以保留顯影光阻的所需圖案於介電層210上。舉例來說,乾蝕刻製程可用於移除光阻圖案之間的介電層210之露出區域。顯影光阻可保護其覆蓋的介電層210之區域免於被乾蝕刻製程的蝕刻化學劑蝕刻。蝕刻製程可為非等向,因此接點開口300的側壁實質上垂直(比如大於80°如87°)。舉例來說(但不限於此),乾蝕刻化學劑可包含碳氟化物氣體的混合物。在蝕刻介電層210的蝕刻製程時,蓋層250可保護閘極220。蝕刻製程亦可蝕刻間隔物240的部份。然而蝕刻對介電層210的選擇性可極高(比如大於5:1),因此介電層210的蝕刻速率大於其他單元如間隔物240的蝕刻速率。在露出源極/汲極磊晶層260時,可終止蝕刻製程。
一些實施例在形成接點開口300時,可部份蝕刻源
極/汲極磊晶層260的上表面。在一些實施例中,在蝕刻源極/汲極磊晶層260的上表面後,可自源極/汲極區的上表面濺鍍源極/汲極材料(如矽鍺),以得再沉積的矽鍺層於接點開口300的底部之側壁表面。圖3並未圖示再沉積的矽鍺層以簡化圖式。
在一些實施例中,接點開口300可為源極/汲極磊晶層260的一者與閘極220之間的共用開口。舉例來說(但不限於此),三維空間中的接點開口300可視作介電層中沿著y方向的溝槽。在一些實施例中,與接點開口300類似的多個接點開口可形成於介電層210中的其他位置。在一些實施例中,與接點開口300類似的接點開口可形成於閘極220上。在一些實施例中,接點開口300的深寬比介於約3至約10之間、頂部關鍵尺寸小於約17nm、底部關鍵尺寸低於約14nm、且深度為約60nm。
在一些實施例中,在進行任何金屬沉積之前先以預清潔製程處理接點開口300,移除可能形成於源極/汲極磊晶層260的上表面上之任何原生氧化物。舉例來說,在製程之間將晶圓暴露至大氣時可能形成原生氧化物,或者在形成接點開口300時形成副產物如原生氧化物。若不移除原生氧化物,可能增加金屬接點電阻。
舉例來說(但不限於此),預清潔製程可為物理蝕刻與化學蝕刻的組合。舉例來說,物理蝕刻可包含氬濺鍍。舉例來說,氬濺鍍可自源極/汲極磊晶層260的上表面移除約30Å至約60Å厚的原生氧化物。由於接點開口300的深寬比(如介於約3與約10之間),氬濺鍍可能不足以自接點開口300的底部移除原生氧化物。化學蝕刻可完成氬濺鍍蝕刻。舉例來說(但不限於
此),化學蝕刻可採用來自氨、三氟化氮、與氫氣之混合物的遠端電漿。電漿與含矽氧化物(如源極/汲極磊晶層260上的原生氧化物)反應以形成可升華的鹽類,且鹽類的升華溫度可介於約100℃至約200℃之間。
方法100接著進行步驟130。在步驟130中,一旦清潔源極/汲極磊晶層260的上表面,則進行原位金屬沉積以形成金屬400與阻障層410於接點開口300中,如圖4所示。在一些實施例中,金屬400可為鈦。舉例來說(但不限於此),可經由採用射頻源的物理氣相沉積製程沉積鈦。射頻物理氣相沉積可改善鈦的底部覆蓋,並在接點開口300的頂角處減緩鈦懸垂或夾斷。在一些實施例中,鈦在接點開口300的底部之沉積厚度,可大於在接點開口300的側壁之沉積厚度。在一些實施例中,鈦厚度介於約100Å至約130Å之間。在一些實施例中,阻障層可為順應係沉積的氮化鈦層,其沉積方法可為沉積溫度介於約300℃至350℃之間的原子層沉積製程。舉例來說(但不限於此),氮化鈦的厚度可介於約15Å至約20Å之間。氮化鈦可避免氧化下方的金屬400(如鈦),必可提供鈷層所用的黏著表面。在一些實施例中,阻障層410不限於氮化鈦而可包含其他材料,比如氮化鉭、氧化銦、氮化鎢、鉭、鈮、鋯、釩、鎢、或釕。
在一些實施例中,可採用快速熱退火製程以形成鈦矽化物於接點開口300的底部。當快速熱退火製程時,金屬400與源極/汲極磊晶層260的上表面中的矽反應形成鈦矽化物。在一些實施例中,快速熱退火的溫度介於約500℃至約600
℃之間。快速熱退火製程可持續約30秒至約200秒。在一些實施例中,快速熱退火製程可採用加熱燈。然而亦可採用其他退火方法如雷射退火。在一些實施例中,單一快速熱退火步驟足以形成鈦矽化物。然而可採用超過一個快速熱退火步驟。圖5顯示快速熱退火製程之後的接點開口300,其形成矽化物層500於源極/汲極磊晶層260上。在一些實施例中,矽化物層500的厚度可介於約5nm至約15nm之間。
在露出矽的區域中,金屬400可與矽反應形成矽化物。在不存在矽的其他區域(比如氧化物層覆蓋的矽、氮化物層、或金屬)只形成少量矽化物或不形成矽化物。額外金屬可用於形成穩定且低電阻的相(如晶粒結構)之矽化物,其包含鈷、鎳、鎢、鉭、或鉬。最終矽化物可分別包含鈷矽化物、鎳矽化物、鎢矽化物、鉭矽化物、或鉬矽化物。退火條件如退火溫度、退火時間、與加熱方式可影響矽化物厚度、組成、與相(如晶粒結構)。一些矽化物需要一或多個退火步驟,以達低電阻的相。
方法100接著進行步驟140,形成襯墊層600於阻障層410上,如圖6所示。在一些實施例中,襯墊層600為鈷層,其厚度介於約70Å至約110Å之間(如90Å)。舉例來說(但不限於此),襯墊層600的沉積方法可為室溫(如約24℃)下的射頻物理氣相沉積製程。在一些實施例中,形成襯墊層時的沉積壓力可介於約50mTorr至約150mTorr之間(如100mTorr)。在一些實施例中,射頻的物理氣相沉積製程可採用高頻的射頻產生器,其操作頻率可介於約40MHz至約45MHz之間,且輸出功率可介於
約500瓦至3000瓦之間。此外,在沉積襯墊層時,施加射頻功率至鈷靶材。在一些實施例中,襯墊層600覆蓋阻障層410。在一些實施例中,襯墊層600並未填滿接點開口300,且其功用為提供後續沉積鈷的成長表面。
方法100接著進行步驟150,沉積金屬層700於襯墊層600上,如圖7所示。金屬層700可填入部份的接點開口300(見圖6)並形成開口710,且開口710小於接點開口300。在一些實施例中,金屬層700為鈷層,其沉積方法可為化學氣相沉積製程,沉積溫度介於約150℃至約200℃之間,且製程壓力低於10Torr(比如介於約2Torr至約5Torr之間)。舉例來說(但不限於此),沉積的鈷層厚度可為約180Å。經由化學氣相沉積法沉積鈷的方法,可採用有機金屬前驅物。
方法100接著進行步驟160,形成金屬層800於金屬層700上以填入圖7的開口710,如圖8所示。在一些實施例中,可同時沉積與再流動金屬層800(比如再流動與共沉積)。在一些實施例中,可在例示性的物理氣相沉積反應器900中進行沉積與再流動金屬層800的步驟,且物理氣相沉積反應器的剖視圖如圖9所示。外部直流與射頻功率產生器(未圖示於圖9)可經由物理氣相沉積反應器900的上表面910上個別的饋通連接器920與930,連接至物理氣相沉積反應器900。鈷靶材940可嵌置於物理氣相沉積反應器900的內側表面上。在一些實施例中,氬電漿可用於自鈷靶材940濺鍍鈷材料。鈷靶材940可與靜電座(electrostatic chuck)970隔有空間950。在製程中,晶圓960可位於靜電座970上。晶圓960可由靜電力固定於靜電座970上。此
外,靜電座970包含加熱器(未圖示於圖9),其可供熱至晶圓960。靜電座970包含饋通連接器980,其可連接至另一外部射頻產生器(未圖示於圖9)。此外部射頻產生器可經由饋通連接器980與靜電座970提供射頻功率至晶圓960。位於物理氣相沉積反應器900之內側側壁表面上的線圈磁體990,可用於調整電漿中的離子物種方向。位於上表面910上的磁體915可限制氬離子更靠近鈷靶材940。在一些實施例中,磁體915與鈷靶材940之間的空間可介於約0.8mm至約1.2mm之間。
上述單元的位置可不同,端視例示性的物理氣相沉積反應器900的設計而定。因此圖9所示的例示性物理氣相沉積反應器900不應侷限本發明實施例。舉例來說,圖9包含例示性的物理氣相沉積反應器900的選定部份,亦可包含其他未圖示的部份。舉例來說,可包含氣體管線、氣體排出管線、電性連接物、加熱器、閥件、額外面板、或外部周邊與設備。
在一些實施例中,在再流動製程中可同時濺鍍金屬層800。在沉積製程時,電漿的氬離子可自鈷靶材940濺鍍鈷材料。在再流動製程時,氬離子撞擊晶圓960的表面,因此可經由再濺鍍製程重置或再流動圖7中開口710內濺鍍的鈷材料。為了輔助再流動製程,可經由靜電座970中的加熱器加熱晶圓960到約300℃至約500℃之間(比如450℃)。在一些實施例中,沉積與再流動製程需平衡以達最佳的間隙填充效能。舉例來說,若沉積速率高而再流動弱,則可能在開口710的入口發生夾斷並形成空洞。相反地,若沉積速率低而再流動強,在共沉積與再流動製程結束時的鈷金屬可能無法填滿開口710。
在一些實施例中,經由獨立之頂部的射頻功率與底部的射頻功率,可分別控制沉積製程與再流動製程。經由對應的饋通連接器930與980,可分別施加獨立之頂部的射頻功率與底部的射頻功率至鈷靶材940與晶圓960。如上所述,對應的外部射頻產生器可提供頂部的射頻功率與底部的射頻功率。舉例來說(但不限於此),功率輸出介於約500瓦至約3000瓦之間的外部射頻產生器可提供頂部的射頻功率,其頻率介於約40MHz至約45MHz之間。功率輸出介於約20瓦至約100瓦之間的另一射頻產生器,可提供頻率介於約10MHz至約15MHz之間的底部的射頻功率。在一些實施例中,底部的射頻與頂部的射頻之間的功率比例可介於約4%至約10%之間,以符合最佳的金屬充填間隙之製程容忍度。底部的射頻與頂部的射頻之間的功率比例,可超出上述提供的製程容忍度(比如介於約4%至約10%之間),端視接點開口而定。如此一來,上述射頻功率的比例僅用以舉例而非侷限本發明實施例。
頂部的射頻功率不足以自鈷靶材940濺鍍材料,因此來自外部的直流電功率產生器之直流電功率可經由饋通連接器920施加至鈷靶材,以吸引氬離子並增加來自鈷靶材940之鈷材料的濺鍍速率。在一些實施例中,直流電功率可介於約200W至約1000W之間。在一些實施例中,沉積鈷金屬的沉積速率取決於直流電與頂部的射頻之間的功率比例,其可大於約25%(如約65%)。在一些實施例中,頂部的射頻功率可調整鈷的沉積速率並改善沉積一致性。在一些實施例中,直流電與射頻之煎的功率比例高時可增加沉積速率並導致夾斷。另一方面,
直流電與頂部的射頻之間的功率比例低會弱化鈷沉積,造成開口710的間隙充填不良。換言之,直流電與頂部的射頻之間的功率比例可影響沉積與再流動之間的平衡。
在一些實施例中,空間950可介於約70mm至約130mm之間,比如介於95mm至105mm之間。在一些實施例中,空間950可作為控制沉積步驟與金屬層800的一致性之另一參數。裝在物理氣相沉積反應器900的內側側壁表面上的線圈磁體990,亦有助於金屬沉積的一致性,並影響再流動製程中氬離子撞擊至晶圓表面上的角度。
在方法100的步驟170中,可進行化學機械平坦化製程以移除介電層210上的金屬層(如金屬400、阻障層410、襯墊層600、金屬層700、與金屬層800),以形成金屬接點1000於源極/汲極磊晶層260上,如圖10所示。化學機械平坦化製程為研磨製程,其採用化學漿液搭配研磨墊以自晶圓的上表面移除導電或介電材料。化學機械平坦化製程可使整個晶圓達到平滑形貌,其上可形成積體電路的額外層狀物。化學機械平坦化製程可為終點式或時控式。在終點式的化學機械平坦化製程中,在偵測到研磨速率不同時即可自動終止研磨。舉例來說,在偵測到欲研磨的層狀物與下方層之間的研磨速率不同時,即可終止研磨。在一些實施例中,化學機械平坦化製程可採用不同的漿液化學劑與研磨墊,以移除沉積在介電層210上的金屬層(如金屬400、阻障層410、襯墊層600、金屬層700、與金屬層800)。
在與前述源極/汲極磊晶層260類似的方式中,金屬接點可形成於金屬閘極(如閘極220)上。此外,可形成共用的金
屬接點於閘極與磊晶層之間,且共用的金屬接點接觸閘極與源極/汲極磊晶層。共用的金屬接點仍屬本發明實施例的精神與範疇,且其形成方法可採用上述方法100的一些或全部步驟。
此處所述的實施例關於改良間隙填充特性的金屬化製程。在一些實施例中,金屬化製程可充填深寬比介於約3至約10且深度大於約60nm的接點孔。舉例來說(但不限於此),金屬化製程包含共沉積與再流動的物理氣相沉積製程。在一些實施例中,經由分別提供獨立之頂部的射頻功率與底部的射頻功率至靶材與晶圓,可分別控制沉積與再流動製程。施加至靶材的直流電功率亦可調整金屬沉積速率。如此一來,一些實施例亦可獨立地控制直流電與頂部的射頻之間的功率比例。
在一些實施例中,方法包括:形成接點開口於氧化物層中;沉積阻障層於接點開口中;沉積襯墊層於阻障層上;以及沉積第一金屬層於襯墊層上,以部份地填入接點開口。方法亦包括沉積第二金屬層於第一金屬層上,以填入開口,其中沉積第二金屬層的步驟包括:採用第一射頻功率與直流電功率濺鍍沉積第二金屬層;以及採用第二射頻功率再流動第二金屬層。
在一些實施例中,沉積第二金屬層的步驟包括製程溫度介於300℃至500℃之間的物理氣相沉積製程。
在一些實施例中,再流動第二金屬層的步驟包括以氬離子撞擊第二金屬層。
在一些實施例中,直流電功率與第一射頻功率之間的比例大於65%。
在一些實施例中,第二射頻功率與第一射頻功率之間的比例介於4%至10%之間。
在一些實施例中,第一射頻功率介於500瓦至3000瓦之間,而第二射頻功率介於20瓦至1000瓦之間。
在一些實施例中,第一射頻功率的頻率介於40MHz至45MHz之間,而第二射頻功率的頻率介於10MHz至15MHz之間。
在一些實施例中,每一襯墊層、第一金屬層、與第二金屬層包括鈷。
在一些實施例中,方法包括提供具有源極/汲極磊晶層於其上的基板;沉積介電層於基板上;蝕刻接點開口於介電層中,以露出源極/汲極磊晶層。方法亦包括沉積阻障層於接點開口中;沉積襯墊層於阻障層上;沉積第一金屬層於襯墊層上,以部份地填入接點開口;以及沉積第二金屬層於第一金屬層上,以填入接點開口,其中沉積第二金屬層的步驟包括施加第一射頻功率至靶材並施加第二射頻功率至基板,以同時濺鍍與再流動第二金屬層。
在一些實施例中,第二射頻功率與第一射頻功率之間的比例介於4%至10%之間。
在一些實施例中,濺鍍包括施加直流電功率至靶材,且直流電功率與第一射頻功率之間的比例大於25%。
在一些實施例中,接點開口的深寬比大於或等於3且小於10。
在一些實施例中,接點開口的深度大於60nm,頂
部的關鍵尺寸小於17nm,且底部的關鍵尺寸小於14nm。
在一些實施例中,沉積第二金屬層的步驟包括溫度介於300℃至500℃之間的物理氣相沉積製程。
在一些實施例中,方法包括提供具有場效電晶體於其上的基板;沉積氧化物層於基板上;蝕刻第一接點開口與第二接點開口於氧化物層中,以分別露出場效電晶體的閘極與源極/汲極磊晶層;沉積阻障層於第一開口與第二開口中;沉積襯墊層於阻障層上;以及沉積第一金屬層於襯墊層上,以部份地填入第一接點開口與第二接點開口中。方法亦包括沉積第二金屬層於第一金屬層上,以填入第一接點開口與第二接點開口,其中沉積第二金屬層的步驟包括濺鍍沉積與再流動第二金屬層,其施加第一射頻功率與直流電功率至靶材,並施加第二射頻功率至接觸基板的靜電座。
在一些實施例中,直流電功率與第一射頻功率之間的比例大於65%。
在一些實施例中,直流電功率介於200瓦至1000瓦之間,第一射頻功率介於500瓦至3000瓦之間,而第二射頻功率介於20瓦至1000瓦之間。
在一些實施例中,每一襯墊層、第一金屬層、與第二金屬層包含鈷。
在一些實施例中,其中靶材與靜電座之間的空間介於95mm至105mm之間。
在一些實施例中,再流動第二金屬層的步驟包括以氬離子濺鍍第二金屬層,以重置第一接點開口與第二接點開
口中的第二金屬層。
應理解的是實施方式的內容(非摘要)可用於解釋申請專利範圍。摘要說明一或多個(但非全部)的實施例,因此不應侷限申請專利範圍。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明實施例作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明精神與範疇,並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
Claims (1)
- 一種半導體結構的形成方法,包括:形成一接點開口於一氧化物層中;沉積一阻障層於該接點開口中;沉積一襯墊層於該阻障層上;沉積一第一金屬層於該襯墊層上,以部份地填入該接點開口;以及沉積一第二金屬層於該第一金屬層上,以填入該開口;其中沉積該第二金屬層的步驟包括:採用一第一射頻功率與一直流電功率濺鍍沉積該第二金屬層;以及採用一第二射頻功率再流動該第二金屬層。
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