CN112530904A - 接触结构及其形成方法 - Google Patents

接触结构及其形成方法 Download PDF

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CN112530904A
CN112530904A CN202011261322.3A CN202011261322A CN112530904A CN 112530904 A CN112530904 A CN 112530904A CN 202011261322 A CN202011261322 A CN 202011261322A CN 112530904 A CN112530904 A CN 112530904A
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silicide
opening
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林瑀宏
傅美惠
林圣轩
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及接触结构及其形成方法。一种结构包括位于衬底上方的介电层、粘合层、硅化物、阻挡层和导电材料。介电层具有至衬底的表面的开口。粘合层沿着开口的侧壁。硅化物位于衬底的表面上。阻挡层位于粘合层和硅化物上，并且阻挡层直接邻接硅化物。导电材料位于开口中的阻挡层上。

Description

接触结构及其形成方法
本申请是于2015年04月08日提交的申请号为201510163064.8的名称为“接触结构及其形成方法”的发明专利申请的分案申请。
优先权声明和交叉引用
本申请要求2014年8月7日提交的标题为“Method of Ti Salicide Formationwith Low Resistance and Resulting Structure”的美国临时申请第62/034,424号的权益，其全部内容结合于此作为参考。
技术领域
本发明涉及集成电路器件，更具体地，涉及接触结构及其形成方法。
背景技术
半导体器件用于各种电子应用中，作为实例，诸如个人计算机、手机、数码相机和其他电子设备中。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻图案化各个材料层以在其上形成电路组件和元件来制造半导体器件。
通常期望半导体器件以较快的速度运行。此外，通常期望减小半导体器件的尺寸以增大器件密度并且允许电子应用的增大的功能。这两个特征有时可能是不能兼得的。当尺寸减小时，半导体器件的一些部件实际上可能导致较慢的速度。期望可以实现较快的速度和减小的尺寸的解决方案。
发明内容
为了解决现有技术中存在的问题，本发明提供了一种结构，包括：介电层，位于衬底上方，所述介电层具有至所述衬底的表面的开口；粘合层，沿着所述开口的侧壁；硅化物，位于所述衬底的表面上；阻挡层，位于所述粘合层和所述硅化物上，并且所述阻挡层直接邻接所述硅化物；以及导电材料，位于所述开口中的所述阻挡层上。
在上述结构中，其中，所述粘合层是钛，所述阻挡层是氮化钛，并且所述硅化物包括钛。
在上述结构中，其中，所述粘合层的厚度介于
Figure BDA0002774730050000021
和
Figure BDA0002774730050000022
之间。
在上述结构中，其中，所述硅化物的厚度介于
Figure BDA0002774730050000023
和
Figure BDA0002774730050000024
之间。
在上述结构中，其中，所述阻挡层的厚度介于
Figure BDA0002774730050000025
和
Figure BDA0002774730050000026
之间。
在上述结构中，其中，所述导电材料是钨。
根据本发明的另一实施例，提供了一种结构，包括：介电层，位于衬底上方，开口穿过所述介电层至所述衬底；钛层，位于所述开口的介电侧壁上；含钛硅化物，位于所述衬底上；氮化钛层，位于所述钛层和所述含钛硅化物上，并且在所述氮化钛层的至少部分和所述含钛硅化物的至少部分之间未设置所述钛层的部分；以及导电材料，位于所述开口中的所述氮化钛层上。
在上述结构中，其中，所述钛层的厚度介于
Figure BDA0002774730050000027
和
Figure BDA0002774730050000028
之间。
在上述结构中，其中，所述含钛硅化物的厚度介于
Figure BDA0002774730050000029
和
Figure BDA00027747300500000210
之间。
在上述结构中，其中，所述氮化钛层的厚度介于
Figure BDA00027747300500000211
和
Figure BDA00027747300500000212
之间。
在上述结构中，其中，所述导电材料是钨。
在上述结构中，其中，所述氮化钛层直接邻接所述含钛硅化物。
根据本发明的又一实施例，提供了一种方法，包括：形成穿过介电层至衬底的开口，所述开口的底面是半导体材料的表面；沿着所述开口的侧壁和在所述半导体材料的表面上形成粘合层；在所述粘合层上形成阻挡层；在形成所述阻挡层之后，使所述粘合层与所述半导体材料反应以形成硅化物；以及在所述开口中的所述粘合层上形成导电材料。
在上述方法中，其中，所述反应包括退火。
在上述方法中，其中，在所述反应之后，所述阻挡层直接邻接所述硅化物。
在上述方法中，其中，形成在所述半导体材料的表面上的所述粘合层的厚度介于
Figure BDA00027747300500000213
和
Figure BDA00027747300500000214
之间。
在上述方法中，其中，所述硅化物的厚度介于
Figure BDA0002774730050000031
和
Figure BDA0002774730050000032
之间。
在上述方法中，其中，所述阻挡层的厚度介于
Figure BDA0002774730050000033
和
Figure BDA0002774730050000034
之间。
在上述方法中，其中，所述导电材料是钨。
在上述方法中，其中，所述粘合层是钛，所述阻挡层是氮化钛，并且所述硅化物包括钛。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图6是根据一些实施例的形成接触结构的中间阶段。
图7是根据一些实施例的接触结构和接触结构形成工艺的示例性应用。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
根据各个实施例提供了接触结构及其形成方法。示出了形成接触结构的中间阶段。讨论了实施例的一些变化。本领域普通技术人员将容易理解在其他实施例的范围内预期的可以做出的其他改变。虽然以特定顺序讨论了方法实施例，但是各种其他方法实施例可以以任何逻辑顺序实施并且可以包括本文中描述的更少或更多的步骤。
图1至图6示出了根据一些实施例的形成接触结构的中间阶段。图1示出了位于衬底20上方的介电层22以及形成为穿过介电层22至衬底20的开口24。衬底20可以是块状半导体衬底、绝缘体上半导体(SOI)衬底、多层或梯度衬底等并且可以是掺杂(例如，掺杂有p型或n型掺杂剂)或未掺杂的。衬底20可以是诸如硅晶圆的晶圆。通常地，SOI衬底包括形成在绝缘层上的半导体材料层。例如，绝缘层可以是埋氧(BOX)层、氧化硅层等。绝缘层提供在诸如硅或玻璃衬底的衬底上。在一些实施例中，衬底20的半导体材料可以包括元素半导体材料，诸如硅、锗等；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。此外，衬底20可以包括外延区，例如，外延区可以增大通过衬底20中的器件的载流子迁移率。例如，晶体管的源极/漏极区可以包括与衬底20的材料不同的材料的外延区。外延区可以是先前为衬底20列举的任何材料。可以形成至外延区的开口24。
介电层22可以包括一个或多个介电层。例如，介电层22可以包括位于衬底20上方的蚀刻停止层和位于蚀刻停止层上方的层间电介质(ILD)。通常地，当形成开口24时，蚀刻停止层提供停止蚀刻工艺的机制。蚀刻停止层由具有与邻近的层不同的蚀刻选择性的介电材料形成，例如，位于下面的衬底20和上面的ILD之间的蚀刻停止层。在实施例中，蚀刻停止层可以由通过诸如化学汽相沉积(CVD)、等离子体增强CVD(PECVD)等的任何合适的方法沉积的SiN、SiCN、SiCO、CN、它们的组合等形成。ILD由诸如磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)等的介电材料形成，并且可以通过诸如CVD、PECVD等的任何合适的方法沉积。介电层22可以包括位于ILD上方的额外的层，诸如硬掩模层、化学机械抛光(CMP)停止层等。
例如，使用可接受的光刻和蚀刻工艺形成穿过介电层22的开口24。该蚀刻可以是任何可接受的蚀刻工艺，诸如反应离子蚀刻(RIE)、中性束蚀刻(NBE)等或它们的组合。该蚀刻可以是各向异性的。该蚀刻可以形成具有基本上垂直的侧壁的开口，但是在一些实施例中，非垂直的侧壁是预期的。
可以实施清洗工艺以去除可能由于开口24中的衬底20的暴露表面的自然氧化而形成的任何不期望的氧化物。在一些实施例中，清洗工艺使用HF基气体或者NF3基和/或NH3基气体。在其他实施例中，实施高温烘烤。可以在存在或不存在HCl气体的情况下实施高温烘烤。烘烤温度可以介于约700℃和约900℃的范围内。烘烤的压力可以介于约10托和约200托的范围内。例如，烘烤持续时间可以介于约30秒和约4分钟的范围内。
在图2中，沿着开口24的表面形成粘合层26。在一些实施例中，粘合层26是诸如由钛、镍、钨、钴、金属合金等构成的金属层。可以使用诸如物理汽相沉积(PVD)、CVD、原子层沉积(ALD)等的可接受的沉积工艺形成粘合层26。在示出的实施例中，粘合层26是通过PVD沉积的钛。在衬底20的表面上形成粘合层26的第一部分261，并且在开口24的侧壁上形成粘合层26的第二部分262。由于PVD沉积，第一部分261的厚度(例如，在垂直于衬底20的表面的方向上)可以大于第二部分262的厚度(例如，在垂直于介电层22的相应的侧壁表面的方向上)。例如，在一些实施例中，第一部分261的厚度为从约
Figure BDA0002774730050000051
至约
Figure BDA0002774730050000052
并且第二部分262的厚度为从约
Figure BDA0002774730050000053
至约
Figure BDA0002774730050000054
在图3中，在粘合层26上形成阻挡层28。在一些实施例中，阻挡层28是诸如包括氮化钛、氮化钽、它们的组合等的金属氮化物层。可以使用诸如CVD、ALD等的可接受的沉积工艺形成阻挡层28。在示出的实施例中，阻挡层28是通过CVD沉积的氮化钛。阻挡层28可以共形地沉积为具有基本上均匀的厚度，但是实施例涉及厚度的一些变化。例如，在一些实施例中，位于第一部分261上的阻挡层28的厚度为从约
Figure BDA0002774730050000055
至约
Figure BDA0002774730050000056
并且位于第二部分262上的阻挡层28的厚度为从约
Figure BDA0002774730050000057
至约
Figure BDA0002774730050000058
应该注意，虽然如此讨论粘合层26和阻挡层28，但是每个粘合层26和阻挡层28均可以独立地或彼此地用作粘合层和/或阻挡层。
在图4中，在衬底20上形成硅化物区30。硅化物区30包括由粘合层26的第一部分261和衬底20的材料之间的反应形成的反应的材料。可以通过使用退火工艺形成硅化物区30。在一些实施例中，退火工艺可以包括将图3的结构放置于约400℃至约900℃的温度下的环境中并且持续约20秒至约180秒。在一些实施例中，硅化物区30的厚度为从约
Figure BDA0002774730050000061
至约
Figure BDA0002774730050000062
在一些实施例中，退火工艺引起衬底20和粘合层26的第一部分261之间的反应，从而使得通过该反应消耗一些或全部的第一部分261。因此，在一些实施例中，阻挡层28的底部可以直接邻接硅化物区30，并且在一些实施例中，没有粘合层设置在阻挡层28的底部和硅化物区30之间。硅化物区30可以包括粘合层26的材料和衬底20的材料。例如，假定粘合层26是钛并且邻接粘合层26(例如，在反应之前)的衬底20是硅，则硅化物区30可以是TiSi。此外，位于开口24的侧壁上的粘合层26的材料(例如，金属)是硅化物区30中的相同的材料(例如，金属)。
在图5中，在开口24中形成导电材料32。导电材料32可以是诸如钨、铜、铝、镍、金、银的金属、金属合金等。可以使用诸如CVD、PVD等的可接受的沉积工艺形成导电材料32。在示出的实施例中，导电材料32是通过CVD沉积的钨。如图所示，导电材料32填充开口24的剩余部分并且形成在介电层22上方。
在图6中，实施诸如CMP的平坦化工艺以去除导电材料32、阻挡层28和粘合层26的过量部分。平坦化工艺在开口24中形成接触件34，其中，介电层22、粘合层26、阻挡层28和接触件34的顶面共平面。
图7示出了图1至图6中讨论的接触结构和接触结构形成工艺的示例性应用。图7示出了诸如鳍式效应晶体管(FET)的电路组件，接触件形成至该电路组件。电路组件可以是p型FET(pFET)或n型FET(nFET)。在示出的实例中，电路组件是平面FET，但是其他实施例涉及三维鳍式FET(FinFET)。各种其他实施例涉及其他电路组件。
图7中的电路组件包括衬底20、隔离区50、栅极电介质52、栅电极54、栅极间隔件56、源极/漏极外延区58、蚀刻停止层60、ILD 62、硅化物区30、粘合层26、阻挡层28、接触件34、蚀刻停止层64、金属间电介质(IMD)66、通孔68和线70。可以如以下所述形成电路组件。
提供衬底20。衬底20诸如先前结合图1讨论的任何衬底。然后在衬底20中形成隔离区50。可以通过蚀刻工艺和/或在衬底20中形成沟槽以及用绝缘材料填充凹槽或沟槽来形成隔离区50。蚀刻可以是诸如RIE、NBE等或它们的组合的任何可接受的蚀刻工艺。该蚀刻可以是各向异性的。绝缘材料可以是诸如氧化硅的氧化物、氮化物等或它们的组合，并且可以通过高密度等离子体化学汽相沉积(HDP-CVD)、可流动CVD(FCVD)(例如，远程等离子体系统中的CVD基材料沉积以及后固化以使其转变为诸如氧化物的另一材料)等或它们的组合形成。可以使用通过任何可接受的工艺形成的其他绝缘材料。诸如CMP的平坦化工艺可以去除任何过量的绝缘材料并且形成共面的隔离区50的顶面和衬底20的顶面。隔离区50可以限定衬底20中的有源区，电路组件将形成在有源区中。可以在有源区中形成阱。例如，可以注入浓度等于或小于1018cm-3(诸如介于约1017cm-3和约1018cm-3之间)的掺杂剂以形成阱。例如，对于n型电路组件的阱，p型杂质包括硼、BF2等，并且例如对于p型电路组件的阱，n型杂质包括磷、砷等。退火可以用于活化注入的杂质。
随后，在衬底20上形成栅极电介质52和栅电极54。在衬底20上沉积栅极介电材料层。在一些实施例中，栅极介电材料包括氧化硅、氮化硅、高k介电材料、它们的多层等。高k介电材料可以具有大于约7.0的k值，并且可以包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb和它们的组合的金属氧化物或硅酸盐。栅极介电材料层的形成方法可以包括CVD、分子束沉积(MBD)、ALD、PECVD等。栅电极材料层沉积在栅极介电材料层上。栅电极材料可以是掺杂或未掺杂的多晶硅；诸如TiN、TaN、TaC、Co、Ru、Al、它们的组合或它们的多层的含金属材料；或任何其他合适的材料。栅电极材料层的形成方法可以包括CVD、ALD、PECVD等。可以在栅电极材料层上形成掩模层。掩模层可以包括氮化硅、碳氮化硅、CN等并且可以通过CVD、PECVD等沉积。然后可以使用可接受的光刻和蚀刻工艺图案化掩模层、栅电极材料和栅极介电材料以形成掩模(未示出)、栅电极54和栅极电介质52。该蚀刻可以是诸如RIE、NBE等或它们的组合的任何可接受的蚀刻工艺。该蚀刻可以是各向异性的。
然后，可以实施用于轻掺杂源极/漏极(LDD)区(未示出)的注入。图案化的掩模、栅电极54和/或栅极电介质52可以用作用于注入的自对准掩模以在衬底20中形成轻掺杂源极/漏极区。例如，对于p型电路组件，p型杂质包括硼、BF2等，并且例如，对于n型电路组件，n型杂质包括磷、砷等。轻掺杂源极/漏极区可以具有从约1015cm-3至约1016cm-3的杂质的浓度。退火可以用于活化注入的杂质。
然后沿着栅极电介质52和栅电极54形成栅极间隔件56。在衬底20上共形地沉积间隔件材料层。间隔件材料可以是氮化硅、SiCN、它们的组合等并且可以通过CVD、PECVD等沉积。实施各向异性蚀刻以图案化栅极间隔件56。各向异性蚀刻可以去除间隔件材料层的水平部分，从而位于栅电极54和栅极电介质52的侧壁上的间隔件材料层的部分作为栅极间隔件56保留。该蚀刻可以是诸如RIE、NBE等或它们的组合的任何可接受的蚀刻工艺。
然后，形成源极/漏极外延区58。可以在衬底20中形成凹槽。凹进可以包括对衬底20的材料具有选择性的蚀刻，其中，例如，通常不蚀刻栅极间隔件56、位于栅电极54上的掩模以及隔离区50。因此，可以在未由栅极间隔件56和栅极电介质52覆盖并且位于隔离区50外部的衬底的有源区中限定凹槽。蚀刻工艺可以是诸如干或湿以及各向同性或各向异性的任何合适的蚀刻工艺。诸如通过金属有机CVD(MOCVD)、分子束外延(MBE)、液相外延(LPE)、汽相外延(VPE)、选择性外延生长(SEG)等或它们的组合在凹槽中外延生长源极/漏极外延区58。源极/漏极外延区58可以包括任何可接受的材料。可以适合于n型电路组件的示例性材料可以包括硅、SiC、SiCP、SiP等。可以适合于p型电路组件的示例性材料可以包括SiGe、SiGeB等。源极/漏极外延区58可以具有从衬底20的顶面凸起的表面并且可以具有小平面。
源极/漏极外延区58可以注入有掺杂剂以形成源极/漏极区，类似于用于形成轻掺杂源极/漏极区的先前讨论的工艺，随后进行退火。例如，对于p型电路组件，p型杂质包括硼、BF2等，并且例如，对于n型电路组件，n型杂质包括磷、砷等。源极/漏极区可以具有介于约1019cm-3和约1021cm-3之间的杂质浓度。在其他实施例中，可以在生长期间原位掺杂源极/漏极外延区58，或者通过与注入掺杂剂结合的原位掺杂来掺杂源极/漏极外延区58。
随后可以诸如通过各向异性蚀刻去除栅电极54上方的掩模(如果存在)和栅极间隔件56的上部。该蚀刻可以是诸如RIE、NBE等或它们的组合的任何可接受的蚀刻工艺。如图7所示，在蚀刻之后，可以形成栅极间隔件56、栅电极54和栅极电介质52。
在衬底20、隔离区、源极/漏极外延区58、栅极间隔件56和栅电极54上方共形地形成蚀刻停止层60。在实施例中，蚀刻停止层60可以由通过诸如CVD、PECVD等的任何合适的方法沉积的SiN、SiCN、SiCO、CN、它们的组合等形成。在蚀刻停止层60上形成ILD 62。ILD 62可以由诸如PSG、BSG、BPSG、USG等的介电材料形成并且可以通过诸如CVD、PECVD等的任何合适的方法沉积。可以诸如通过CMP平坦化ILD 62以具有平坦的顶面。
然后，形成穿过ILD 62和蚀刻停止层60至相应的源极/漏极外延区58的接触结构，每个接触结构包括粘合层26、阻挡层28、硅化物区30和接触件34。在不形成源极/漏极外延区58的其他实施例中，接触结构形成至衬底20。可以如先前结合图1至图6讨论的形成接触结构。
在ILD 62和接触结构上形成蚀刻停止层64。在实施例中，蚀刻停止层64可以由通过诸如CVD、PECVD等的任何合适的方法沉积的SiN、SiCN、SiCO、CN、它们的组合等形成。在蚀刻停止层64上形成IMD 66。IMD 66可以由诸如PSG、BSG、BPSG、USG等的介电材料形成并且可以通过诸如CVD、PECVD等的任何合适的方法沉积。
在IMD 66中形成例如包括线70和通孔68的互连结构。可以通过使用合适的光刻技术形成互连结构。通常地，实施光刻和蚀刻工艺以去除对应于互连结构的IMD 66的部分，从而在IMD 66中限定凹槽和/或开口。在蚀刻工艺之后，可以用诸如金属、元素金属、过渡金属等的一个或多个层的导电材料填充凹槽和/或开口。在一些实施例中，用于填充凹槽和/或开口的导电材料是通过电化学镀(ECP)沉积的铜。可以使用其他导电材料和工艺。
应该注意，互连结构可以包括由诸如钛、氮化钛、钽、氮化钽等的导电材料的一个或多个层形成的阻挡/粘合层。在实施例中，粘合/阻挡层可以包括氮化钽的薄层和随后的钽的薄层。例如，可以通过CVD、PVD等形成氮化钽和钽层。可以实施诸如CMP的平坦化工艺以去除过量的阻挡层材料和/或导电材料。因此形成的互连结构连接至接触结构。可以形成额外的IMD和互连结构。
虽然讨论的图7中的电路组件以可以称为先栅极工艺的工艺形成，但是本领域普通技术人员将容易理解各种改变，从而本文中公开的方面可以应用于后栅极或替代栅极工艺。实施例涉及应用于这样的工艺。
实施例可以实现优势。首先，因为可以避免去除用于硅化的未反应金属的步骤，所以可以简化形成具有硅化物区的接触结构的工艺。此外，因为金属的量(而不是退火的温度或持续时间)可以确定硅化物区的厚度，可以更容易地控制硅化物区的厚度。此外，在阻挡层和硅化物区之间未设置粘合层，从而可以减小电阻。通过减小电阻，可以降低电阻-电容(RC)时间常数，这可以产生更快的器件运行，甚至在减小的尺寸下。可以实现其他优势。
根据实施例，一种结构包括位于衬底上方的介电层、粘合层、硅化物、阻挡层和导电材料。介电层具有至衬底的表面的开口。粘合层沿着开口的侧壁。硅化物位于衬底的表面上。阻挡层位于粘合层和硅化物上，并且阻挡层直接邻接硅化物。导电材料位于开口中的阻挡层上。
根据另一实施例，一种结构包括位于衬底上方的介电层、钛层、含钛硅化物、氮化钛层和导电材料。开口穿过介电层至衬底。钛层位于开口的介电侧壁上。含钛硅化物位于衬底上。氮化钛层位于钛层和含钛硅化物上，并且在氮化钛层的至少部分和含钛硅化物的至少部分之间未设置钛层的部分。导电材料位于开口中的氮化钛层上。
根据又一实施例，一种方法包括形成穿过介电层至衬底的开口，开口的底面是半导体材料的表面；沿着开口的侧壁和在半导体材料的表面上形成粘合层；在粘合层上形成阻挡层；在形成阻挡层之后，使粘合层与半导体材料反应以形成硅化物；以及在开口中的粘合层上形成导电材料。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
介电层，位于衬底上方，所述介电层具有至所述衬底的表面的开口；
粘合层，沿着所述开口的侧壁；
硅化物，位于所述衬底的表面上，所述硅化物中的金属的量大于所述粘合层中的与所述硅化物层的表面积相同的区域中的金属的量；
阻挡层，位于所述粘合层和所述硅化物上，并且所述阻挡层包括直接邻接所述硅化物的第一区和位于所述开口的侧壁上的第二区，所述第一区具有第一厚度并且所述第二区具有第二厚度，所述第一厚度与所述第二厚度的比率为15～50/5～40；以及
导电材料，位于所述开口中的所述阻挡层上，
其中，所述粘合层具有倾斜的侧壁，并且整个所述硅化物包括与所述粘合层相同的金属。
2.根据权利要求1所述的结构，其中，所述粘合层是钛，所述阻挡层是氮化钛，并且所述硅化物包括钛。
3.根据权利要求1所述的结构，其中，所述粘合层的厚度介于
Figure FDA0002774730040000011
和
Figure FDA0002774730040000012
之间。
4.根据权利要求1所述的结构，其中，所述硅化物的厚度介于
Figure FDA0002774730040000013
和
Figure FDA0002774730040000014
之间。
5.根据权利要求1所述的结构，其中，所述第一区的第一厚度为
Figure FDA0002774730040000016
并且所述第二区的第二厚度为
Figure FDA0002774730040000015
6.根据权利要求1所述的结构，其中，所述导电材料是钨。
7.一种半导体结构，包括：
介电层，位于衬底上方，开口穿过所述介电层至所述衬底；
钛层，位于所述开口的介电侧壁上；
含钛硅化物，位于所述衬底上，所述含钛硅化物中的金属的量大于所述钛层中的与所述含钛硅化物的表面积相同的区域中的金属的量；
氮化钛层，包括接触所述钛层的第一区和接触所述含钛硅化物的第二区，并且在所述氮化钛层的所述第二区和所述含钛硅化物的至少部分之间未设置所述钛层的部分，其中，所述第一区具有第一厚度并且所述第二区具有第二厚度，所述第一厚度与所述第二厚度的比率为5～40/15～50；以及
导电材料，位于所述开口中的所述氮化钛层上，
其中，所述钛层具有倾斜的侧壁。
8.一种形成半导体结构的方法，包括：
形成穿过介电层至衬底的开口，所述开口的底面是半导体材料的表面；
沿着所述开口的侧壁和在所述半导体材料的表面上形成粘合层，其中，所述粘合层具有位于所述半导体材料的表面上的第一部分和位于所述开口的侧壁上的第二部分，所述第一部分的厚度大于所述第二部分的厚度；
在所述粘合层上形成阻挡层；
在形成所述阻挡层之后，通过退火使所述粘合层与所述半导体材料反应以形成硅化物；以及
在所述开口中的所述粘合层上形成导电材料，
其中，在所述反应之后，所述阻挡层包括直接邻接所述硅化物的第一区，以及位于所述开口的侧壁上的第二区，
其中，在所述退火期间，通过控制所述粘合层中金属的量来控制所述硅化物区的厚度。
9.一种形成半导体结构的方法，包括：
蚀刻穿过所述介电层以形成开口，其中，所述开口延伸至半导体材料的顶面；
对所述半导体材料的顶面实施清洁工艺；
沿着所述开口的侧壁并且在所述半导体材料的顶面上沉积钛层；
在所述钛层上方沉积氮化钛层，其中，所述氮化钛层包括：
侧壁部分，沿着所述开口的侧壁，其中，所述侧壁部分具有第一厚度；以及
底部部分，位于所述开口的底部处，其中，所述底部部分具有第二厚度；
通过退火使所述钛层与所述半导体材料反应，以形成硅化物，其中，所述氮化钛层的底面接触所述硅化物；以及
在所述开口中沉积所述导电材料，其中，所述导电材料位于所述氮化钛层上，
其中，在所述退火期间，通过控制所述钛层中金属的量来控制所述硅化物的厚度。
10.一种形成半导体结构的方法，包括：
在半导体衬底上形成栅极堆叠件；
在所述栅极堆叠件的侧上外延生长半导体区域；
形成覆盖所述栅极堆叠件和所述半导体区域的蚀刻停止层；
在所述蚀刻停止层上形成层间电介质(ILD)；
蚀刻所述层间电介质和所述蚀刻停止层以形成接触开口，其中，所述半导体区域暴露于所述接触开口；
沉积金属层，所述金属层延伸至所述接触开口中并且接触所述半导体区域；
在所述金属层上方沉积所述金属氮化物，其中，所述金属氮化物层包括：
侧壁部分，沿着所述接触开口的侧壁，其中，所述侧壁部分具有第一厚度；以及
底部部分，位于所述接触开口的底部处，其中，所述底部部分具有第二厚度，所述第二厚度与所述第一厚度的比率为15～50/5～40；
实施退火以使所述金属层的底部部分与所述半导体区域反应以生成硅化物区，其中，所述金属氮化物的底面接触所述硅化物区的顶面；以及
在所述接触开口中填充所述金属，其中，所述金属位于所述金属氮化物层上面，
其中，在所述退火期间，通过控制所述金属层中金属的量来控制所述硅化物区的厚度。
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