CN110718454A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN110718454A
CN110718454A CN201810769212.4A CN201810769212A CN110718454A CN 110718454 A CN110718454 A CN 110718454A CN 201810769212 A CN201810769212 A CN 201810769212A CN 110718454 A CN110718454 A CN 110718454A
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China
Prior art keywords
layer
forming
source
dielectric layer
hole
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CN201810769212.4A
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Inventor
陆毅
肖长永
林艺辉
张琴
王�华
呼翔
朱小娜
江滢
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201810769212.4A priority Critical patent/CN110718454A/zh
Priority to US16/511,747 priority patent/US10847425B2/en
Publication of CN110718454A publication Critical patent/CN110718454A/zh
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Abstract

一种半导体器件及其形成方法，方法包括：提供基底；形成栅极结构、源漏掺杂层和介质层，栅极结构位于基底上，源漏掺杂层位于栅极结构两侧的基底中，介质层位于基底、源漏掺杂层和栅极结构上；在栅极结构的整个顶部表面形成阻挡层，阻挡层被所述介质层覆盖；之后，在栅极结构两侧的介质层中分别形成第一通孔，第一通孔位于源漏掺杂层上；之后，在栅极结构上形成贯穿介质层的第二通孔，且第二通孔暴露出所述阻挡层；之后，对第一通孔底部的源漏掺杂层的表面进行非晶化离子注入；之后，去除第二通孔底部的阻挡层；之后，采用金属硅化工艺在源漏掺杂层的表面形成金属硅化物层。所述方法提高了半导体器件的性能。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体器件及其形成方法。
背景技术
MOS(金属-氧化物-半导体)晶体管，是现代集成电路中最重要的元件之一。MOS晶体管的基本结构包括：半导体衬底；位于半导体衬底表面的栅极结构，所述栅极结构包括：位于半导体衬底表面的栅介质层以及位于栅介质层表面的栅电极层；位于栅极结构两侧半导体衬底中的源漏掺杂区。
MOS晶体管的工作原理是：在栅极结构施加电压，通过调节栅极结构底部沟道的电流来产生开关信号。
然而，现有技术中MOS晶体管构成的半导体器件的性能仍有待提高。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，以提高半导体器件的性能。
为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供基底；形成栅极结构、源漏掺杂层和介质层，所述栅极结构位于基底上，源漏掺杂层位于栅极结构两侧的基底中，介质层位于基底、源漏掺杂层和栅极结构上；在栅极结构的整个顶部表面形成阻挡层，所述阻挡层被所述介质层覆盖；形成阻挡层后，在栅极结构两侧的介质层中分别形成第一通孔，第一通孔位于源漏掺杂层上；形成第一通孔后，在栅极结构上形成贯穿介质层的第二通孔，且第二通孔暴露出所述阻挡层；形成第二通孔和阻挡层后，对第一通孔底部的源漏掺杂层的表面进行非晶化离子注入；进行所述非晶化离子注入后，去除第二通孔底部的阻挡层；去除第二通孔底部的阻挡层后，采用金属硅化工艺在源漏掺杂层的表面形成金属硅化物层。
可选的，所述阻挡层的材料和介质层的材料不同；所述阻挡层的材料包括SiN、SiOCN、SiBCN或SiCN。
可选的，所述阻挡层的厚度为3纳米～5纳米。
可选的，所述介质层包括第一层间介质层和第二层间介质层；形成所述栅极结构、源漏掺杂层和介质层的方法包括：在所述基底上形成伪栅极结构；在伪栅极结构两侧的基底中分别形成源漏掺杂层；在基底、伪栅极结构和源漏掺杂层上形成第一层间介质层，第一层间介质层覆盖伪栅极结构的侧壁且暴露出伪栅极结构的顶部表面；形成第一层间介质层后，去除伪栅极结构，在第一层间介质层中形成栅开口；在所述栅开口中形成栅极结构；在栅极结构和第一层间介质层上形成第二层间介质层；在形成第二层间介质层之前形成所述阻挡层，所述第二层间介质层还位于阻挡层上。
可选的，所述栅极结构的顶部表面和第一层间介质层的顶部表面齐平；所述阻挡层位于第一层间介质层和所述栅极结构的顶部表面；所述第一通孔还贯穿源漏掺杂层上的阻挡层；形成所述阻挡层的工艺为沉积工艺。
可选的，所述栅极结构的顶部表面低于第一层间介质层的顶部表面；所述阻挡层仅位于栅极结构的顶部表面；形成所述栅极结构之后，在所述栅开口中形成阻挡层。
可选的，形成所述阻挡层的方法包括：在所述栅开口中以及第一层间介质层上形成阻挡材料层；平坦化所述阻挡材料层直至暴露出第一层间介质层的表面，形成所述阻挡层。
可选的，所述非晶化离子注入所注入的离子包括锗离子。
可选的，所述金属硅化工艺的步骤包括：在第一通孔底部的源漏掺杂层表面形成金属层；形成金属层后，进行退火处理，使所述金属层和源漏掺杂层表面的材料反应而形成所述金属硅化物层。
可选的，所述金属层的材料为Ti、Ni或Co。
可选的，所述金属层的材料为Ti，所述退火处理的温度为750摄氏度～850摄氏度，退火时间为0.25毫秒～0.4毫秒。
可选的，所述金属层还位于第一通孔的侧壁、第二通孔的侧壁和底部；所述半导体器件的形成方法还包括：形成所述金属层后，且在进行所述退火处理之前，在第一通孔的侧壁和底部、以及第二通孔的侧壁和底部形成第一保护层，第一保护层位于所述金属层的表面。
可选的，所述第一保护层的材料包括TiN或TaN。
可选的，还包括：在形成栅极结构、源漏掺杂层和介质层的过程中，形成第二保护层，所述第二保护层位于源漏掺杂层的表面，所述介质层还覆盖所述第二保护层；形成第一通孔后，且在进行所述金属硅化工艺之前，所述第一通孔的底部暴露出所述第二保护层；以所述第二保护层为保护进行所述非晶化离子注入；在去除第二通孔底部的阻挡层的过程中去除第一通孔的底部的第二保护层。
可选的，所述第二保护层的材料为SiN、SiOCN、SiBCN或SiCN；所述第二保护层的厚度为3纳米～5纳米。
本发明还提供一种采用上述任意一项方法形成的半导体器件。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案提供的半导体器件的形成方法中，所述非晶化离子注入使源漏掺杂层表面材料呈非晶态，这样利于降低金属硅化工艺中的退火温度和退火时间。所述非晶化离子注入选择在形成第二通孔之后进行，这样使得非晶化离子注入的步骤和金属硅化工艺步骤之间的间隔步骤较少，降低对源漏掺杂层表面材料的非晶状态的影响。在进行非晶化离子注入的过程中，所述栅极结构的顶部表面具有阻挡层，阻挡层阻挡非晶化离子注入将离子注入栅极结构中，因此避免造成半导体器件不可预知的电学性能的波动，如阈值电压的波动；其次，非晶化离子注入的工艺不会将栅极结构的顶部表面的金属原子溅射出来，从而避免污染非晶化离子注入的腔室。综上，提高了半导体器件的形成。
进一步，所述非晶化离子注入采用的离子为Ge离子，Ge离子即不属于N型离子，也不属于P型离子，因此所述Ge离子对源漏掺杂层的电学性能影响较小。
进一步，所述非晶化离子注入的工艺通过第二保护层将离子注入到源漏掺杂层的表面，使得源漏掺杂层的表面材料非晶化。所述离子通过第二保护层后散射进入源漏掺杂层，避免离子穿过源漏掺杂层的晶格间隙，利于对源漏掺杂层的表面材料进行非晶化。
附图说明
图1至图4是一种半导体器件形成过程的结构示意图；
图5至图15是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有技术形成的半导体器件的性能较差。
图1至图4是一种半导体器件形成过程的结构示意图。
参考图1，提供半导体衬底100；形成栅极结构110、源漏掺杂层120和介质层140，所述栅极结构110位于半导体衬底100上，所述源漏掺杂层120分别位于栅极结构110两侧的半导体衬底100中，所述介质层140覆盖栅极结构110和半导体衬底100。
参考图2，在栅极结构110两侧的介质层140中分别形成第一通孔141；形成第一通孔141后，在栅极结构110上的介质层140中形成第二通孔142，第二通孔142暴露出栅极结构110的顶部表面。
随着半导体器件的特征尺寸的不断减小，受到光刻极限的限制，难以同时对源漏掺杂层120上的介质层140和栅极结构110上的介质层140进行图形化，因此需要分别形成第一通孔141和第二通孔142。
参考图3，形成第二通孔142后，对第一通孔141底部的源漏掺杂层120表面进行非晶化离子注入。
参考图4，进行所述非晶化离子注入后，采用金属硅化工艺在源漏掺杂层120的表面形成金属硅化物层150，金属硅化工艺的步骤包括：在源漏掺杂层的表面形成金属层；形成金属层后，进行退火工艺，使得金属层的源漏掺杂层的表面材料反应形成金属硅化物层150。
而所述金属硅化工艺选择在形成第二通孔142之后进行的原因包括：形成第二通孔142的步骤中有多道刻蚀工艺，若金属硅化工艺在形成第二通孔142之前进行，那么形成第二通孔142过程中的多道刻蚀工艺会对金属硅化物层造成损伤，降低金属硅化物层的电学性能。
在进行金属硅化工艺之前进行所述非晶化离子注入，能够使源漏掺杂层120的表面材料非晶化，这样利于降低金属硅化工艺中的退火温度。
所述非晶化离子注入选择在形成第二通孔142之后进行的原因包括：使得非晶化离子注入的步骤和金属硅化工艺步骤之间的间隔步骤较少，降低对源漏掺杂层表面材料的非晶状态的影响。
然而，由于在进行非晶化离子注入的过程中，第二通孔142暴露出栅极结构110的顶部表面，因此会将非晶化离子注入至栅极结构110中，造成半导体器件不可预知的电学性能的波动，如阈值电压的波动，其次，非晶化离子注入的工艺还会将栅极结构110表面的金属原子溅射出来，污染非晶化离子注入采用的腔室。
在此基础上，本发明提供一种半导体器件的形成方法，在栅极结构的整个顶部表面形成阻挡层，阻挡层被介质层覆盖；之后，在栅极结构两侧的介质层中分别形成第一通孔，第一通孔位于源漏掺杂层上；之后，在栅极结构上形成贯穿介质层的第二通孔，且第二通孔暴露出所述阻挡层；之后，对第一通孔底部的源漏掺杂层的表面进行非晶化离子注入；之后，去除第二通孔底部的阻挡层；之后，采用金属硅化工艺在源漏掺杂层的表面形成金属硅化物层。所述方法提高了半导体器件的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图5至图15是本发明一实施例中半导体器件形成过程的结构示意图。
结合参考图5和图6，图6为沿图5中切割线A-A1的示意图，提供基底200。
本实施例中，以半导体器件为鳍式场效应晶体管为示例进行说明，相应的，基底200包括半导体衬底201和位于半导体衬底201上的鳍部202。
所述半导体衬底201的材料为单晶硅。所述半导体衬底201还可以是多晶硅或非晶硅。所述半导体衬底201的材料还可以为锗、锗化硅、砷化镓等半导体材料。
本实施例中，所述半导体衬底201上还具有隔离结构203，所述隔离结构203覆盖鳍部202的部分侧壁表面。所述隔离结构203的材料为氧化硅。
在其它实施例中，所述半导体器件为平面式MOS晶体管，相应的，所述基底为平面式的半导体衬底。
继续结合参考图5和图6，形成栅极结构210、源漏掺杂层220和介质层230，所述栅极结构210位于基底200上，源漏掺杂层220位于栅极结构210两侧的基底200中，介质层230位于基底200、源漏掺杂层220和栅极结构210上；在栅极结构210的整个顶部表面形成阻挡层240，所述阻挡层240被所述介质层230覆盖。
所述介质层230的材料包括氧化硅。所述介质层230包括第一层间介质层231和第二层间介质层232。
所述栅极结构210包括栅介质层211和位于栅介质层211上的栅电极层212。所述栅介质层211的材料为高K(K大于3.9)介质材料，所述栅电极层212的材料为金属。本实施例中，栅极结构210横跨鳍部202且覆盖鳍部202的部分侧壁表面和部分顶部表面。
形成所述栅极结构210、源漏掺杂层220和介质层230的方法包括：在所述基底200上形成伪栅极结构(为图示)；在伪栅极结构两侧的基底200中分别形成源漏掺杂层220，具体的，在伪栅极结构两侧的鳍部202中分别形成源漏掺杂层220；在基底200、伪栅极结构和源漏掺杂层220上形成第一层间介质层231，第一层间介质层231覆盖伪栅极结构的侧壁且暴露出伪栅极结构的顶部表面；形成第一层间介质层231后，去除伪栅极结构，在第一层间介质层231中形成栅开口；在所述栅开口中形成栅极结构210；在栅极结构210和第一层间介质层231上形成第二层间介质层232。
本实施例中，还包括：在形成源漏掺杂层220之前，在伪栅极结构的侧壁形成侧墙250；在伪栅极结构和侧墙250两侧的基底200中分别形成源漏掺杂层220；所述第一层间介质层231还覆盖侧墙250的侧壁。形成栅极结构210后，侧墙250位于栅极结构210的侧壁，源漏掺杂层220分别位于栅极结构210两侧的鳍部202中；所述第二层间介质层232还位于侧墙250上。
在形成第二层间介质层232之前形成阻挡层240；所述第二层间介质层232还位于阻挡层240上。
本实施例中，栅极结构210的顶部表面和第一层间介质层231的顶部表面齐平；所述阻挡层240位于第一层间介质层231和所述栅极结构210的顶部表面，所述阻挡层240还位于侧墙250的顶部表面。形成所述阻挡层240的工艺为沉积工艺，如原子层沉积工艺或等离子体化学气相沉积工艺。
所述阻挡层240的材料和介质层230的材料不同；所述阻挡层240的材料包括SiN、SiOCN、SiBCN或SiCN。
所述阻挡层240的厚度为3纳米～5纳米，如4纳米。所述阻挡层240的厚度选择此范围的意义在于：若所述阻挡层240的厚度小于3纳米，则导致阻挡层240对后续非晶化离子注入的阻挡能力较弱；若所述阻挡层240的厚度大于5纳米，则导致后续增加去除第二通孔底部的阻挡层240的时间和复杂度。
在其它实施例中，栅极结构的顶部表面低于第一层间介质层的顶部表面，阻挡层仅位于栅极结构的顶部表面。具体的，形成所述栅极结构之后，在所述栅开口中形成阻挡层。相应的，形成阻挡层的方法包括：在所述栅开口中以及第一层间介质层上形成阻挡材料层；平坦化所述阻挡材料层直至暴露出第一层间介质层的表面，形成所述阻挡层。
本实施例中，还包括：在形成栅极结构210、源漏掺杂层220和介质层230的过程中，形成第二保护层270，所述第二保护层270位于源漏掺杂层220的表面，所述介质层230还覆盖所述第二保护层270。
所述第二保护层270的材料为SiN、SiOCN、SiBCN或SiCN。
所述第二保护层270的厚度为3纳米～5纳米，如4纳米。
本实施例中，第二保护层270的厚度和阻挡层240的厚度一致，在后续去除第一通孔底部的第二保护层和第二通孔底部的阻挡层240的过程中，在暴露出源漏掺杂层220表面的同时暴露出栅极结构210的顶部表面。
结合参考图7和图8，图7为在图5基础上的示意图，图8为在图6基础上的示意图，形成阻挡层240后，在栅极结构210两侧的介质层230中分别形成第一通孔261，第一通孔261位于源漏掺杂层220上；形成第一通孔261后，在栅极结构210上形成贯穿介质层230的第二通孔262，且第二通孔262暴露出所述阻挡层240。
本实施例中，第一通孔261还贯穿源漏掺杂层220上的阻挡层240。
第一通孔261和第二通孔262先后形成的原因在于：随着半导体器件的特征尺寸的不断减小，源漏掺杂层220的中心和栅极结构210的中心之间的距离不断减小。受到光刻极限的限制，难以同时对源漏掺杂层220上的介质层230和栅极结构210上的介质层230进行图形化，因此需要先后形成第一通孔261和第二通孔262。
本实施例中，第一通孔261暴露出位于源漏掺杂层220表面的第二保护层270。在其它实施例中，第一通孔暴露出源漏掺杂层220的表面。
本实施例中，形成第二通孔262的步骤包括：形成第一通孔261后，形成填充满第一通孔261的平坦层，所述平坦层还位于介质层230上；在平坦层上形成光刻胶层，所述光刻胶层用于定义第二通孔262的位置；以所述光刻胶层为掩膜，采用各向异性干刻工艺刻蚀栅极结构210上的介质层230和平坦层直至暴露出阻挡层240，在栅极结构210上的介质层230和平坦层中形成第二通孔262；之后去除光刻胶层；去除光刻胶层后，去除平坦层。
所述平坦层的材料为光阻材料、底部抗反射层材料或有机聚合物。形成所述平坦层的工艺为旋涂工艺。去除所述平坦层的工艺为干刻工艺，所述干刻工艺采用的气体采用含氧气体。
本实施例中，在去除平坦层的过程中，所述第二保护层270能够保护源漏掺杂层220的表面，避免源漏掺杂层220表面被氧化。
参考图9和图10，图9为在图7基础上的示意图，图10为在图8基础上的示意图，形成第二通孔262和阻挡层240后，对第一通孔261底部的源漏掺杂层220的表面进行非晶化离子注入。
具体的，在去除平坦层之后，进行所述非晶化离子注入。
所述非晶化离子注入的作用包括：使源漏掺杂层220表面材料呈非晶态，从而使后续在源漏掺杂层220表面形成的金属硅化物层的表面粗糙度较低，且后续在第一通孔261中形成的第一插塞和源漏掺杂层220之间的接触电阻较低；其次，源漏掺杂层220的表面材料非晶化，这样利于降低后续金属硅化工艺中的退火温度和退火时间。
所述非晶化离子注入所注入的离子包括锗离子。
所述非晶化离子注入采用的离子为Ge离子，Ge离子即不属于N型离子，也不属于P型离子，因此所述Ge离子对源漏掺杂层220的电学性能影响较小。
所述非晶化离子注入的参数包括：注入能量为2KeV～20KeV，注入剂量为1.0E12atom/cm2～1.0E16atom/cm2，注入角度为0度～30度。所述注入角度为注入方向与半导体衬底法线方向之间的夹角。
本实施例中，所述非晶化离子注入的工艺通过第二保护层270将离子注入到源漏掺杂层220的表面，使得源漏掺杂层220的表面材料非晶化。所述离子通过第二保护层270后散射进入源漏掺杂层220，避免离子穿过源漏掺杂层220的晶格间隙，利于对源漏掺杂层220的表面材料进行非晶化。
形成第二通孔262后，对第一通孔261底部的源漏掺杂层220的表面进行非晶化离子注入，使得所述非晶化离子注入的步骤和后续金属硅化工艺步骤之间的间隔步骤较少，降低对源漏掺杂层220表面材料的非晶状态的影响。若非晶化离子注入的步骤和后续金属硅化工艺之间的间隔步骤较多时，这些间隔步骤中的温度会修复源漏掺杂层表面材料的非晶状态，这样不利于后续金属硅化工艺的进行。
本实施例中，在进行非晶化离子注入的过程中，所述栅极结构210的顶部表面具有阻挡层240，阻挡层240阻挡非晶化离子注入将离子注入栅极结构210中，因此避免造成半导体器件不可预知的电学性能的波动，如阈值电压的波动；其次，非晶化离子注入的工艺不会将栅极结构210的顶部表面的金属原子溅射出来，从而避免污染非晶化离子注入的腔室。
参考图11和图12，图11为在图9基础上的示意图，图12为在图10基础上的示意图，进行所述非晶化离子注入后，去除第二通孔262底部的阻挡层240。
去除第二通孔262底部的阻挡层240的工艺为干刻工艺或湿刻工艺。
本实施例中，在去除第二通孔262底部的阻挡层240的过程中，去除第一通孔261底部的第二保护层270，即在一道刻蚀工艺中去除第二通孔262底部的阻挡层240和第一通孔261底部的第二保护层270，使得工艺得到简化。
本实施例中，所述阻挡层240的材料和第二保护层270的材料相同，利于同时去除第二通孔262底部的阻挡层240和第一通孔261底部的第二保护层270。本实施例中，阻挡层240的材料和第二保护层270的材料均为氮化硅。
本实施例中，去除第二通孔262底部的阻挡层240和第一通孔261底部的第二保护层270的工艺为湿法工艺，参数包括：采用的溶液为热磷酸溶液。
在其它实施例中，阻挡层240的材料和第二保护层270的材料不同。
去除第二通孔262底部的阻挡层240后，采用金属硅化工艺在源漏掺杂层220的表面形成金属硅化物层281(参考图15)。
所述金属硅化工艺的步骤包括：在第一通孔261底部的源漏掺杂层220表面形成金属层；形成金属层后，进行退火处理，使所述金属层和源漏掺杂层220表面的材料反应而形成金属硅化物层281。
参考图13和图14，图13为在图11基础上的示意图，图14为在图12基础上的示意图，在第一通孔261底部的源漏掺杂层220表面形成金属层280。
本实施例中，非晶化离子注入之后，紧接着去除第二通孔262底部的阻挡层240和第一通孔261底部的第二保护层270，在去除第二通孔262底部的阻挡层240和第一通孔261底部的第二保护层270后，紧接着进行形成金属层280的步骤。非晶化离子注入的步骤和去除第二通孔262底部的阻挡层240和第一通孔261底部的第二保护层270的步骤之间没有会对源漏掺杂层220表面材料的非晶状态产生影响的工艺步骤，在去除第二通孔262底部的阻挡层240和第一通孔261底部的第二保护层270的步骤和形成金属层280的步骤之间没有会对源漏掺杂层220表面材料的非晶状态产生影响的工艺步骤，如没有刻蚀步骤。
所述金属层280的材料为Ti、Ni或Co。
所述金属层280还位于第一通孔261的侧壁、第二通孔262的侧壁和底部、以及介质层230的顶部表面。
所述半导体器件的形成方法还包括：形成所述金属层280后，在第一通孔261的侧壁和底部、第二通孔262的侧壁和底部、以及介质层230上形成第一保护层，第一保护层位于所述金属层280的表面。
所述第一保护层的材料包括TiN或TaN。在其它实施例中，不形成第一保护层。
参考图15，图15为在图13基础上的示意图，形成金属层280后，进行退火处理，使所述金属层280和源漏掺杂层220表面的材料反应而形成金属硅化物层281。
由于在进行金属硅化工艺之前，进行了所述非晶化离子注入，使得金属硅化工艺的温度降低，且退火时间降低。当所述金属层280的材料为Ti，所述退火处理的温度为750摄氏度～850摄氏度，如800摄氏度，退火时间为0.25毫秒～0.4毫秒。
当金属层280的材料为Ti，好处还包括：在进行所述退火处理的过程中，主要由源漏掺杂层220表面的材料向金属层280中扩散，进而反应形成金属硅化物层281，因此金属硅化物层281中的底部形貌良好，具体的，避免金属硅化物层281中的底部和侧部有尖端。若金属硅化物层281中的底部和侧部有尖端，那么该尖端会穿透源漏掺杂区和沟道区之间的PN结，引起漏电。
本实施例中，第一保护层在进行所述退火处理之前形成，在进行所述退火处理的过程中，第一保护层能够保护金属层280，阻挡所述退火处理对金属层280造成氧化。在一个实施例中，为了防止所述退火处理的温度下，第一保护层的材料重新结晶而导致第一保护层性能稳定性较差的问题，选择所述退火处理的温度在900摄氏度以下。
在其它实施例中，第一保护层在所述退火处理之后形成。
所述金属硅化工艺选择在形成第二通孔262之后进行的原因包括：形成第二通孔262的步骤中有多道刻蚀工艺，若金属硅化工艺在形成第二通孔262之前进行，那么形成第二通孔262过程中的多道刻蚀工艺会对金属硅化物层造成损伤，降低金属硅化物层的电学性能。
所述半导体器件额形成方法还包括：形成金属硅化物层281后，在第一通孔261中和第二通孔262中、以及介质层230上形成插塞材料层；平坦化插塞材料层、第一保护层和金属层280直至暴露出介质层230的顶部表面，在第一通孔261中形成第一插塞，在第二通孔262中形成第二插塞。
由于第一插塞和第二插塞在一道工艺制程中形成，因此简化了工艺。
形成第一插塞后，第一插塞和金属硅化物层281之间、以及第一插塞和介质层230之间具有第一保护层，第一通孔中的第一保护层还用于阻挡第一插塞的原子扩散。形成第二插塞后，第二插塞和栅极结构之间、以及第二插塞和介质层230之前还具有第一保护层，第二通孔中的第一保护层还用于阻挡第二插塞的原子扩散。
相应的，本实施例还提供一种采用上述方法形成的半导体器件。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (16)

1.一种半导体器件的形成方法，其特征在于，包括：
提供基底；
形成栅极结构、源漏掺杂层和介质层，所述栅极结构位于基底上，源漏掺杂层位于栅极结构两侧的基底中，介质层位于基底、源漏掺杂层和栅极结构上；
在栅极结构的整个顶部表面形成阻挡层，所述阻挡层被所述介质层覆盖；
形成阻挡层后，在栅极结构两侧的介质层中分别形成第一通孔，第一通孔位于源漏掺杂层上；
形成第一通孔后，在栅极结构上形成贯穿介质层的第二通孔，且第二通孔暴露出所述阻挡层；
形成第二通孔和阻挡层后，对第一通孔底部的源漏掺杂层的表面进行非晶化离子注入；
进行所述非晶化离子注入后，去除第二通孔底部的阻挡层；
去除第二通孔底部的阻挡层后，采用金属硅化工艺在源漏掺杂层的表面形成金属硅化物层。
2.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述阻挡层的材料和介质层的材料不同；所述阻挡层的材料包括SiN、SiOCN、SiBCN或SiCN。
3.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述阻挡层的厚度为3纳米～5纳米。
4.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述介质层包括第一层间介质层和第二层间介质层；形成所述栅极结构、源漏掺杂层和介质层的方法包括：在所述基底上形成伪栅极结构；在伪栅极结构两侧的基底中分别形成源漏掺杂层；在基底、伪栅极结构和源漏掺杂层上形成第一层间介质层，第一层间介质层覆盖伪栅极结构的侧壁且暴露出伪栅极结构的顶部表面；形成第一层间介质层后，去除伪栅极结构，在第一层间介质层中形成栅开口；在所述栅开口中形成栅极结构；在栅极结构和第一层间介质层上形成第二层间介质层；在形成第二层间介质层之前形成所述阻挡层，所述第二层间介质层还位于阻挡层上。
5.根据权利要求4所述的半导体器件的形成方法，其特征在于，所述栅极结构的顶部表面和第一层间介质层的顶部表面齐平；所述阻挡层位于第一层间介质层和所述栅极结构的顶部表面；所述第一通孔还贯穿源漏掺杂层上的阻挡层；形成所述阻挡层的工艺为沉积工艺。
6.根据权利要求4所述的半导体器件的形成方法，其特征在于，所述栅极结构的顶部表面低于第一层间介质层的顶部表面；所述阻挡层仅位于栅极结构的顶部表面；形成所述栅极结构之后，在所述栅开口中形成阻挡层。
7.根据权利要求6所述的半导体器件的形成方法，其特征在于，形成所述阻挡层的方法包括：在所述栅开口中以及第一层间介质层上形成阻挡材料层；平坦化所述阻挡材料层直至暴露出第一层间介质层的表面，形成所述阻挡层。
8.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述非晶化离子注入所注入的离子包括锗离子。
9.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述金属硅化工艺的步骤包括：在第一通孔底部的源漏掺杂层表面形成金属层；形成金属层后，进行退火处理，使所述金属层和源漏掺杂层表面的材料反应而形成所述金属硅化物层。
10.根据权利要求9所述的半导体器件的形成方法，其特征在于，所述金属层的材料为Ti、Ni或Co。
11.根据权利要求10所述的半导体器件的形成方法，其特征在于，所述金属层的材料为Ti，所述退火处理的温度为750摄氏度～850摄氏度，退火时间为0.25毫秒～0.4毫秒。
12.根据权利要求9所述的半导体器件的形成方法，其特征在于，所述金属层还位于第一通孔的侧壁、第二通孔的侧壁和底部；所述半导体器件的形成方法还包括：形成所述金属层后，且在进行所述退火处理之前，在第一通孔的侧壁和底部、以及第二通孔的侧壁和底部形成第一保护层，第一保护层位于所述金属层的表面。
13.根据权利要求12所述的半导体器件的形成方法，其特征在于，所述第一保护层的材料包括TiN或TaN。
14.根据权利要求1所述的半导体器件的形成方法，其特征在于，还包括：在形成栅极结构、源漏掺杂层和介质层的过程中，形成第二保护层，所述第二保护层位于源漏掺杂层的表面，所述介质层还覆盖所述第二保护层；形成第一通孔后，且在进行所述金属硅化工艺之前，所述第一通孔的底部暴露出所述第二保护层；以所述第二保护层为保护进行所述非晶化离子注入；在去除第二通孔底部的阻挡层的过程中去除第一通孔的底部的第二保护层。
15.根据权利要求14所述的半导体器件的形成方法，其特征在于，所述第二保护层的材料为SiN、SiOCN、SiBCN或SiCN；所述第二保护层的厚度为3纳米～5纳米。
16.一种如权利要求1至15任意一项方法形成的半导体器件。
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