TW201905960A - 裝置的形成方法 - Google Patents
裝置的形成方法Info
- Publication number
- TW201905960A TW201905960A TW107114689A TW107114689A TW201905960A TW 201905960 A TW201905960 A TW 201905960A TW 107114689 A TW107114689 A TW 107114689A TW 107114689 A TW107114689 A TW 107114689A TW 201905960 A TW201905960 A TW 201905960A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- region
- forming
- opening
- etch stop
- Prior art date
Links
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
提供內連線結構與其形成方法。方法包括形成開口於介電層與蝕刻停止層中,其中開口只部份地延伸穿過蝕刻停止層。方法亦包括產生真空環境於裝置周圍。在產生真空環境於裝置周圍之後,方法包括蝕刻穿過蝕刻停止層,以延伸開口並露出第一導電結構。方法亦包括形成第二導電結構於開口中。
Description
本發明實施例關於裝置的形成方法,更特別關於在將晶圓輸送至真空腔室之前,部份穿過蝕刻停止層的開口不露出下方的接點以避免其氧化。
在使半導體裝置最小化的現有製程中,需要低介電常數的介電材料作為導電內連線之間的金屬間及/或層間介電層,以在傳遞訊號時減少因電容效應產生的電阻-電容延遲。如此一來,介電層的介電常數越低,則相鄰導電線路的寄生電容與積體電路的電阻-電容延遲越低。
然而,作為低介電常數的介電材料之現有材料不理想。特別的是,依介電常數選擇材料時,材料的其他特性如材料硬度或強度可能不適於半導體製程。如此一來,需改善採用低介電常數的介電材料之製程。
本發明一實施例提供之裝置的形成方法,包括:形成開口於介電層與蝕刻停止層中,其中開口只部份地延伸穿過蝕刻停止層;產生真空環境於裝置周圍;在產生真空環境於裝置周圍之後,蝕刻穿過蝕刻停止層以延伸開口,並露出第一導電結構;以及形成第二導電結構於開口中。
A-A、B/C-B/C‧‧‧剖面
T1‧‧‧厚度
30‧‧‧鰭狀場效電晶體
32、50‧‧‧基板
34、54‧‧‧隔離區
36、52、56‧‧‧鰭狀物
38‧‧‧閘極介電層
40‧‧‧閘極
42、44‧‧‧源極/汲極區
50B‧‧‧第一區
50C‧‧‧第二區
58‧‧‧虛置介電層
60‧‧‧虛置閘極層
62、157‧‧‧遮罩層
70、76‧‧‧虛置閘極
72、78‧‧‧遮罩
80‧‧‧閘極密封間隔物
82、84‧‧‧磊晶源極/汲極區
86‧‧‧閘極間隔物
88、100‧‧‧層間介電層
90‧‧‧凹陷
92、96‧‧‧閘極介電層
94、98‧‧‧閘極
102、104、106、108‧‧‧接點
150‧‧‧蝕刻停止層
151、160、210、216、222‧‧‧底層
152、164、214、220、226‧‧‧上方層
154‧‧‧介電層
156、158‧‧‧抗反射塗層
162、212、218、224‧‧‧中間層
166、168、170、172‧‧‧開口
174‧‧‧溝槽
176‧‧‧通孔開口
180‧‧‧部份
202‧‧‧製程腔室
204‧‧‧晶圓座
206‧‧‧製程設備
182‧‧‧阻障層
183‧‧‧晶種層
184‧‧‧導電材料
186‧‧‧導電結構
第1圖係一些實施例中,鰭狀場效電晶體的透視圖。
第2至6圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第7A、7B、與7C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第8A、8B、與8C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第9A、9B、與9C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第10A、10B、與10C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第11A、11B、與11C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第12A、12B、與12C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第13A、13B、與13C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第14A、14B、與14C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第15A、15B、與15C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第16A、16B、與16C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第17A、17B、與17C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第18A、18B、與18C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第19A、19B、與19C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第20A、20B、與20C圖係一些實施例中,製程腔室中的鰭狀場效電晶體裝置其剖視圖。
第21A、21B、與21C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第22A、22B、與22C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第23A、23B、與23C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第24A、24B、與24C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第25A、25B、與25C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第26A、26B、與26C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第27A、27B、與27C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第28A、28B、與28C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第29A、29B、與29C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第30A、30B、與30C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第31A、31B、與31C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第32圖係一些實施例中,製程腔室中的鰭狀場效電晶體裝置其剖視圖。
第33A、33B、與33C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第34A、34B、與34C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第35A、35B、與35C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第36A、36B、與36C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
第37A、37B、與37C圖係一些實施例中,形成鰭狀場效電晶體裝置的中間階段其剖視圖。
下述揭露內容提供許多不同實施例或實例以實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸,或兩者之間隔有其他額外構件而非直接接觸。此外,本發明的多個實例可採用重複標號及/或 符號使說明簡化及明確,但這些重複不代表多種實施例中相同標號的元件之間具有相同的對應關係。
此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。元件亦可轉動90°或其他角度,因此方向性用語僅用以說明圖示中的方向。
多種實施例提供內連線結構與其形成方法。下述說明形成內連線結構的中間階段。此處所述的一些實施例的上下文中,採用雙鑲嵌製程形成內連線。在其他實施例中,可採用單鑲嵌製程。下述內容包含實施例的一些變化。本技術領域中具有通常知識者應理解其他調整屬於其他實施例的範疇。雖然此處所述的實施例中的方法以特定順序說明,但其他實施例的方法可由任何邏輯性的順序進行,且可包含較少或較多的下述步驟。
第1圖係鰭狀場效電晶體之一例的三維圖。鰭狀場效電晶體30包含鰭狀物36於基板32上。隔離區34位於基板32上,且鰭狀物36自相鄰的隔離區34之間向上凸起。閘極介電層38延著鰭狀物36的側壁並位於鰭狀物36的上表面上,而閘極40位於閘極介電層38上。源極/汲極區42與44相對於閘極介電層38與閘極40,位於鰭狀物36的兩側中。第1圖亦顯示後續圖式中所用的參考剖面。剖面A-A越過通道、閘極介電層38、與閘極40,其沿著鰭狀物36的縱軸,且其方向為源極/汲極區42與 44之間的電流方向。後續圖式將對應參考剖面以清楚說明。
此處所述的實施例上下文中的鰭狀場效電晶體,其形成方法採用閘極後製製程。在其他實施例中,可採用閘極先製製程。此外,一些實施例可用於平面裝置,比如平面場效電晶體。
第2至31C圖與第33A至37C圖係一些實施例中,形成鰭狀場效電晶體的中間階段其剖視圖。第2至6圖對應第1圖中的參考剖面A-A,除了具有多個鰭狀場效電晶體。在第7A至31C圖與第33A至37C圖中,末尾為A的圖式沿著類似的剖面A-A;末尾為B的圖式沿著類似的剖面B/C-B/C且位於基板的第一區上;而末尾為C圖的圖式沿著類似的剖面B/C-B/C且位於基板的第二區上。
第2圖顯示基板50。基板50可為半導體基板如基體半導體、絕緣層上半導體基板、或類似物,其可摻雜(比如摻雜p型或n型摻質)或未摻雜。基板50可為晶圓如矽晶圓。一般而言,絕緣層上半導體基板包含半導體材料層形成於絕緣層上。舉例來說,絕緣層可為埋置氧化物層、氧化矽層、或類似物。可提供絕緣層於基板上,通常為矽基板或玻璃基板。亦可採用其他基板如多層基板或組成漸變基板。在一些實施例中,基板50的半導體材料可包含矽、鍺、半導體化合物(如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、半導體合金(如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦)、或上述之組合。
基板50具有第一區50B與第二區50C。第一區50B 對應後續圖式中末尾為B者,其可用於形成n型裝置如n型金氧半電晶體或n型鰭狀場效電晶體。第二區50C對應後續圖式中末尾為C者,其可用於形成p型裝置如p型金氧半電晶體或p型鰭狀場效電晶體。
第3與4圖顯示形成鰭狀物52,以及形成隔離區54於相鄰的鰭狀物52之間。在第3圖中,鰭狀物52形成於基板50中。在一些實施例中,鰭狀物52形成於基板50中的方法可為蝕刻溝槽於基板50中。上述蝕刻可為任何可接受的蝕刻製程,比如反應性離子蝕刻、中性束蝕刻、類似方法、或上述之組合。蝕刻可為非等向性。
在第4圖中,形成絕緣材料於相鄰的鰭狀物52之間,以形成隔離區54。絕緣材料可為氧化物如氧化矽、氮化物、類似物、或上述之組合,且其形成方法可為高密度電漿化學氣相沉積、可流動的化學氣相沉積(比如在遠端電漿系統中沉積化學氣相沉積為主的材料,之後硬化以將沉積的材料轉為另一材料如氧化物)、類似方法、或上述之組合。此外可採用任何可接受的製程形成的其他絕緣材料。一旦形成絕緣材料,可進行退火製程。在例示性的實施例中,絕緣材料為可流動的化學氣相沉積製程形成的氧化矽。絕緣材料可稱作隔離區54。在第4圖中,可進行平坦化製程如化學機械研磨,以移除任何多餘的絕緣材料,並使隔離區54的上表面與鰭狀物52的上表面齊平。
如第5圖所示,使隔離區54凹陷化以形成淺溝槽隔離區。由於隔離區54凹陷化,因此第一區50B與第二區50C中的 鰭狀物56自相鄰的隔離區54之間凸起。此外,隔離區54的上表面可具有圖示的平坦表面、凸起表面、凹陷表面(如碟狀)、或上述之組合。藉由合適蝕刻,可讓隔離區54的上表面平坦、凸起、及/或凹陷。隔離區54的凹陷化步驟可採用可接受的蝕刻製程,比如對隔離區54的材料具有選擇性的蝕刻製程。舉例來說,可採用化學氧化物移除法,其可為CERTAS®蝕刻、Applied Material SICONI工具、或稀氫氟酸。
本技術領域中具有通常知識者應理解第2至5圖所示的製程,僅為形成鰭狀物56的例子之一。在其他實施例中,可形成介電層於基板50的上表面上;可蝕刻形成穿過介電層的溝槽;可磊晶成長同質磊晶結構於溝槽中;並使介電層凹陷化,讓同質磊晶結構自介電層凸起以形成鰭狀物。在其他實施例中,可採用異質磊晶結構作為鰭狀物。舉例來說,可使第4圖中的半導體帶如鰭狀物52凹陷化,並將不同於鰭狀物52的材料磊晶成長於凹陷處。在其他實施例中,可形成介電層於基板50的上表面上;蝕刻形成穿過介電層的溝槽、將不同於基板50的材料磊晶成長於溝槽中,以形成異質磊晶結構;並使介電層凹陷化,讓異質磊晶結構自介電層凸起以形成鰭狀物56。在一些實施例中,磊晶成長同質磊晶結構或異質磊晶結構時,可原位摻雜磊晶成長的材料以省略之前或之後的佈植。不過原位摻雜與佈植摻雜亦可搭配使用。此外,在n型金氧半區與p型金氧半區中磊晶成長不同的材料可具有優點。在多種實施例中,鰭狀物56可包含矽鍺(SixGe1-x,其中x可介於近似0與1之間)、碳化矽、純或實質上純鍺、III-V族半導體化合物、II-VI族半導 體化合物、或類似物。舉例來說,用以形成III-V族半導體化合物的可用材料包含但不限於砷化銦、砷化鋁、砷化鎵、磷化銦、氮化鎵、砷化銦鎵、砷化銦鋁、銻化鎵、銻化鋁、磷化鋁、磷化鎵、或類似物。
在第5圖中,合適的井區可形成於鰭狀物56、鰭狀物52、及/或基板50中。舉例來說,p型井區可形成於第一區50B中,而n型井區可形成於第二區50C中。
採用光阻或其他遮罩(未圖示),可對第一區50B與第二區50C進行不同的佈植步驟。舉例來說,光阻形成於第一區50B的鰭狀物56與隔離區54上。圖案化光阻以露出基板50的第二區50C如p型金氧半區。光阻的形成方法可採用旋轉塗佈技術,且光阻的圖案化方法可採用可接受的光微影技術。一旦圖案化光阻層,即對第二區50C進行n型雜質的佈植,且光阻可作為遮罩以實質上避免n型雜質佈植至第一區50B(如n型金氧半區)中。n型雜質可為磷、砷、或類似物,且其佈植至第二區50C中的濃度小於或等於1018cm-3,比如介於約1017cm-3至約1018cm-3之間。在佈植後移除光阻,且移除方法可為可接受的灰化製程。
在佈植第二區50C之後,形成光阻於第二區50C中的鰭狀物56與隔離區54上。圖案化光阻以露出基板50的第一區50B如n型金氧半區。光阻的形成方法可採用旋轉塗佈技術,且光阻的圖案化方法可採用可接受的光微影技術。一旦圖案化光阻層,即對第一區50B進行p型雜質的佈植,且光阻可作為遮罩以實質上避免p型雜質佈植至第二區50C(如p型金氧半區)中。p 型雜質可為硼、氟化硼、或類似物,且其佈植至第一區50B中的濃度小於或等於1018cm-3,比如介於約1017cm-3至約1018cm-3之間。在佈植後移除光阻,且移除方法可為可接受的灰化製程。
在佈植第一區50B與第二區50C之後,可進行退火製程以活化佈植的p型與n型雜質。佈植可形成p型井區於第一區50B(如n型金氧半區)中,並形成n型井區於第二區50C(如p型金氧半區)中。在一些實施例中,磊晶鰭狀物的成長材料可在成長時原位摻雜以省略佈植步驟,不過原位摻雜與佈植摻雜亦可搭配使用。
在第6圖中,形成虛置介電層58於鰭狀物56上。舉例來說,虛置介電層58可為氧化矽、氮化矽、上述之組合、或類似物,且其形成方法可為依據可接受的技術進行之沉積法或熱成長法。虛置閘極層60形成於虛置介電層58上,而遮罩層62形成於虛置閘極層60上。虛置閘極層60可沉積於虛置介電層58上後平坦化,且平坦化的方法可為化學機械研磨。遮罩層62可沉積於虛置閘極層60上。舉例來說,虛置閘極層60的組成可為多晶矽,但亦可採用對隔離區54具有高蝕刻選擇性的其他材料。舉例來說,遮罩層62可包含氮化矽或類似物。在此例中,單一的虛置閘極層60與單一的遮罩層62越過第一區50B與第二區50C。在其他實施例中,可分別形成虛置閘極層於第一區50B與50C中,並分別形成遮罩層於第一區50B與第二區50C中。
在第7A、7B、與7C圖中,可採用可接受的光微影與蝕刻技術圖案化遮罩層62,以形成遮罩72於第一區50B中(如第7B圖所示),以及形成遮罩78於第二區50C中(如第7C圖所 示)。藉由可接受的蝕刻技術,可將遮罩72與78的圖案轉移至虛置閘極層60與虛置介電層58,以形成虛置閘極70於第一區50B中,並形成虛置閘極76於第二區50C中。虛置閘極70與76分別覆蓋鰭狀物56的通道區。虛置閘極70與76的縱向,亦可實質上垂直於個別磊晶鰭狀物的縱向。
在第8A、8B、與8C圖中,可形成閘極密封間隔物80於個別的虛置閘極70與76及/或鰭狀物56的露出表面上。熱氧化或沉積步驟後進行非等向蝕刻,可行成閘極密封間隔物80。
在形成閘極密封間隔物80之後,可進行佈植以形成輕摻雜源極/汲極區。與前述的第5圖類似,可形成遮罩如光阻於第一區50B(如n型金氧半區)上,並露出第二區50C(如p型金氧半區)。可佈植p型雜質至第二區50C中露出的鰭狀物56中。接著可移除遮罩。接著可形成遮罩如光阻層於第二區50C上,並露出第一區50B。可佈植n型雜質至第一區50B中露出的鰭狀物56中。接著可移除遮罩。n型雜質可為前述的任何n型雜質,而p型雜質可為前述的任何p型雜質。輕摻雜源極/汲極區的雜質濃度可介於約1015cm-3至約1016cm-3之間。接著可退火以活化佈植的雜質。
如第8A、8B、與8C圖所示,磊晶源極/汲極區82與84形成於鰭狀物56中。在第一區50B中,磊晶源極/汲極區82形成於鰭狀物56中,因此每一虛置閘極70位於相鄰的一對磊晶源極/汲極區82之間。在一些實施例中,磊晶源極/汲極區82可延伸至鰭狀物52中。在第二區50C中,磊晶源極/汲極區84形成 於鰭狀物56中,因此每一虛置閘極76位於相鄰的一對磊晶源極/汲極區84之間。在一些實施例中,磊晶源極/汲極區84可延伸至鰭狀物52中。
第一區50B(如n型金氧半區)中的磊晶源極/汲極區82,其形成方法可為先遮罩第二區50C(如p型金氧半區),並順應性地沉積虛置間隔物層於第一區50B中,再非等向蝕刻虛置間隔物層,以沿著第一區50B中的虛置閘極70及/或閘極密封間隔物80的側壁形成虛置閘極間隔物(未圖示)。接著蝕刻第一區50B中磊晶鰭狀物的源極/汲極區以形成凹陷。接著磊晶成長磊晶源極/汲極區82於第一區50B的凹陷中。磊晶源極/汲極區82可包含任何可接受的材料,比如適用於n型鰭狀場效電晶體的材料。舉例來說,若鰭狀物56為矽,則磊晶源極/汲極區82可包含矽、碳化矽、磷碳化矽、磷化矽、或類似物。磊晶源極/汲極區82可具有自鰭狀物56之個別表面隆起的表面,且可具有晶面。之後移除第一區50B中的虛置閘極間隔物與第二區50C上的遮罩,且移除方法可為蝕刻。
第二區50C(如p型金氧半區)中的磊晶源極/汲極區84,其形成方法可為先遮罩第一區50B(如n型金氧半區),並順應性地沉積虛置間隔物層於第二區50C中,再非等向蝕刻虛置間隔物層,以沿著第二區50C中的虛置閘極76及/或閘極密封間隔物80的側壁形成虛置閘極間隔物(未圖示)。接著蝕刻第二區50C中磊晶鰭狀物的源極/汲極區以形成凹陷。接著磊晶成長磊晶源極/汲極區84於第二區50C的凹陷中。磊晶源極/汲極區84可包含任何可接受的材料,比如適用於p型鰭狀場效電晶體的 材料。舉例來說,若鰭狀物56為矽,則磊晶源極/汲極區84可包含矽鍺、硼化矽鍺、鍺、鍺錫、或類似物。磊晶源極/汲極區84可具有自鰭狀物56之個別表面隆起的表面,且可具有晶面。之後移除第二區50C中的虛置閘極間隔物與第一區50B上的遮罩,且移除方法可為蝕刻。
在第9A、9B、與9C圖中,閘極間隔物86形成於閘極密封間隔物80上,而閘極密封間隔物80沿著虛置閘極70與76的側壁。閘極間隔物86的形成方法可為順應性地沉積材料,並非等向蝕刻材料。閘極間隔物86的材料可為氮化矽、碳氮化矽、上述之組合、或類似物。
磊晶源極/汲極區82與84及/或磊晶鰭狀物可佈植摻質,以形成源極/汲極區。佈植摻質的方法可與前述形成輕摻雜的源極/汲極區的製程類似,接著進行退火。源極/汲極區的雜質濃度可介於約1019cm-3至約1021cm-3之間。第一區50B如n型金氧半區中的源極/汲極區所用的n型雜質,可為前述的任何n型雜質。第二區50C如p型金氧半區中的源極/汲極區所用的p型雜質,可為前述的任何p型雜質。在其他實施例中,可在成長時原位摻雜磊晶源極/汲極區82與84。
在第10A、10B、與10C圖中,沉積層間介電層88於第9A、9B、與9C圖所示的結構上。在一實施例中,層間介電層88為可流動的化學氣相沉積形成的可流動膜。在一些實施例中,層間介電層88之組成為介電材料,比如磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、或類似物,且其沉積方法可為任何合適方法如化學氣相沉 積或電漿增強化學氣相沉積。
在第11A、11B、與11C圖中,可進行平坦化製程如化學機械研磨,使層間介電層88的上表面與虛置閘極70及76的上表面齊平。化學機械研磨亦可移除虛置閘極70與76上的遮罩72與78。綜上所述,虛置閘極70與76的上表面自層間介電層88露出。
在第12A、12B、與12C圖中,在蝕刻步驟中移除虛置閘極70與76、閘極密封間隔物80、以及直接位於虛置閘極70與76下的虛置介電層58的部份,以形成凹陷90。每一凹陷90露出個別鰭狀物56的通道區。每一通道區位於相鄰的一對磊晶源極/汲極區82與84之間。在蝕刻虛置閘極70與76的移除步驟中,虛置介電層58可作為蝕刻停止層。在移除虛置閘極70與76之後,接著可移除虛置介電層58與閘極密封間隔物80。
在第13A、13B、與13C圖中,形成閘極介電層92與96以及閘極94與98以用於置換閘極。閘極介電層92與96係順應性地沉積於凹陷90中,比如沉積於鰭狀物56的上表面與側壁上、閘極間隔物86的側壁上、以及層間介電層88的上表面上。在一些實施例中,閘極介電層92與96包含氧化矽、氮化矽、或其多層結構。在其他實施例中,閘極介電層92與96包含高介電常數的介電材料,且這些實施例中的閘極介電層92與96其介電常數大於約7.0,其可包含鉿、鋁、鋯、鑭、鎂、鋇、鈦、鉛、或上述之組合的金屬氧化物或矽酸鹽。閘極介電層92與96的形成方法可包含分子束沉積、原子層沉積、電漿增強化學氣相沉積、或類似方法。
接著分別沉積閘極94與98於閘極介電層92與96上並填入凹陷90的其餘部份。閘極94與98的組成可為含金屬材料如氮化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、鎢、上述之組合、或上述之多層結構。若採用多層結構,其可包含一或多個功函數層、一或多個調整層、一或多個阻障層、上述之組合、或類似物。在填入閘極94與98之後,可進行平坦化製程如化學機械研磨,以移除層間介電層88其上表面上的閘極介電層92與96以及閘極94與98的多餘部份。閘極94與98以及閘極介電層92與96的材料之保留部份,即形成鰭狀場效電晶體的置換閘極。
可同時形成閘極介電層92與96,因此閘極介電層92與96可由相同材料組成。可同時形成閘極94與98,因此閘極94與98可由相同材料組成。然而其他實施例可分別形成閘極介電層92與96,因此閘極介電層92與96可由不同材料組成。可分別形成閘極94與98,因此閘極94與98可由不同材料組成。在採用分開的製程形成閘極介電層與閘極時,可採用多種遮罩步驟以遮罩並露出合適的區域。
在第14A、14B、與14C圖中,沉積層間介電層100於層間介電層88上。第14A、14B、與14C圖亦顯示穿過層間介電層100與層間介電層88的接點102與104,以及穿過層間介電層100的接點106與108。在一實施例中,層間介電層100為可流動的化學氣相沉積法形成的可流動膜。在一些實施例中,層間介電層100之組成為介電材料如磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、或類似物,且其沉積方法可為任何合適方法如化學氣相沉積或電漿增強 化學氣相沉積、形成穿過層間介電層88與100的開口,以用於接點102與104。形成穿過層間介電層100的開口,以用於接點106與108。這些開口可同時形成於相同步驟中,或形成於分開的步驟中。開口的形成方法可採用可接受的光微影與蝕刻技術。襯墊物如擴散阻障層、黏著層、或類似物,以及導電材料可形成於開口中。襯墊物可包含鈦、氮化鈦、鉭、氮化鉭、或類似物。導電材料可為銅、銅合金、銀、金、鎢、鋁、鎳、或類似物。可進行平坦化製程如化學機械研磨,以自層間介電層100的表面移除多餘材料。保留的襯墊物與導電材料,即形成開口中的接點102與104。可進行退火製程,以分別形成矽化物於磊晶源極/汲極區82與84以及接點102與104之間的界面。接點102物理與電性耦接至磊晶源極/汲極區82,接點104物理與電性耦接至磊晶源極/汲極區84,接點106物理與電性耦接至閘極94,且接點108物理與電性耦接至閘極98。
在第15A、15B、與15C圖中,可形成蝕刻停止層150於層間介電層100及接點102、104、106、與108上。介電層154可形成於蝕刻停止層150上。抗反射塗層156、遮罩層157、與抗反射塗層158形成於介電層154上。三層結構形成於抗反射塗層158上,其包含底層160、中間層162、與上方層164。上述每一層狀物將進一步詳述於下。
蝕刻停止層150可包含氮化物、矽碳為主的材料、摻雜碳的氧化物、碳氧化矽、摻雜氧的碳化矽、或摻雜氮的碳化矽。蝕刻停止層150可為同質材料的單層,或含有多個子層的複合層。在本發明一些實施例中,蝕刻停止層150包含底層 151,與底層151上的上方層152。在一些實施例中,底層151可包含氮化鋁,而上方層152可包含摻雜氧的碳化矽。蝕刻停止層150的沉積方法可為化學氣相沉積、物理氣相沉積、原子層沉積、旋轉塗佈介電層的製程、類似製程、或上述之組合。
介電層154形成於蝕刻停止層150上。介電層154可形成以幫助接點102、104、106、與108彼此隔離,以及幫助接點102、104、106、與108與其他相鄰的電性線路(即將形成於介電層154之中與之上)之間的隔離。在一些實施例中,介電層154可為孔洞材料如氮碳氧化矽、氮碳化矽、碳氧化矽、碳氫氧化矽、或類似物,且其形成方法可先形成前驅物層於蝕刻停止層150上。前驅物層可包含基質材料與穿插於基質材料中的致孔劑,或者只含基質材料而不含致孔劑。在一實施例中,前驅物層的形成方法可為共沉積基質與致孔劑,且共沉積製程採用電漿增強化學氣相沉積以同時沉積基質與致孔劑,即形成的前驅物層中基質材料與致孔劑混合在一起。然而如本技術領域中具有通常知識者所知,同時採用電漿增強化學氣相沉積製程的共沉積製程,並非用以形成前驅物層的唯一製程。此外亦可採用任何合適製程,比如預混合基質材料與致孔劑材料成液體,接著將混合物液體旋轉塗佈於蝕刻停止層150上。
基質材料或主要材料的形成方法,可採用電漿增強化學氣相沉積,但亦可改用任何合適的製程如化學氣相沉積、物理氣相沉積、甚至是旋轉塗佈。電漿增強化學氣相沉積可採用的前驅物為甲基二乙氧基矽烷,但亦可改用其他前驅物如其他矽烷如烷基矽烷(如三甲基矽烷或四甲基矽烷)、烷氧基 矽烷(如甲基三乙氧基矽烷、甲基三甲氧基矽烷、甲基二甲氧基矽烷、三甲基甲氧基矽烷、或二甲基二甲氧基矽烷)、線狀矽氧烷或環狀矽氧烷(如八甲基環四矽氧烷或四甲基環四矽氧烷)、上述之組合、或類似物。然而本技術領域中具有通常知識者應理解,此處所列的材料與製程僅用以說明而非侷限實施例,且可改用任何其他合適的基質前驅物。
在放置基質材料後,可自基質材料移除致孔劑並形成孔洞於基質中,以降低介電層154其整體的介電常數。致孔劑材料可大到足以形成孔洞,亦小到足以使個別孔洞的尺寸不會完全取代基質材料。如此一來,致孔劑可包含有機分子如α-萜品烯(即1-異丙基-4-甲基-1,3-環己二烯)、環辛烷(船型)、或1,2-雙(三乙氧基矽基)乙烷矽。
在致孔劑分散於基質材料中的前驅物層形成之後,自基質材料移除致孔劑以形成孔洞於基質材料中。在一實施例中,移除致孔劑的方法為退火製程,其可破壞並蒸發致孔劑材料,使致孔劑材料擴散並離開基質材料,以保留結構完整的孔洞狀介電材料作為介電層154。舉例來說,退火溫度可介於約200℃至約500℃之間(比如約400℃),且退火時間可介於約10秒至約600秒之間(比如約200秒)。
然而本技術領域中具有通常知識者應理解,上述熱製程並非自基質材料移除致孔劑以形成介電層154的唯一方法。此外亦可改用其他合適製程,比如以紫外線照射致孔劑以分解致孔劑,或採用微波分解致孔劑。可移除所有或部份致孔劑的這些製程與任何其他合適製程,均完全包含於實施例的範 疇中。
抗反射塗層156、遮罩層157、與抗反射塗層158形成於介電層154上。在一些實施例中,抗反射塗層156可為無氮抗反射塗層,其組成可為無氮的氧化物。舉例來說,抗反射塗層156可為氧化矽層,其形成方法可採用任何合適的沉積方法如原子層沉積、化學氣相沉積、電漿增強化學氣相沉積、上述之組合、或類似方法。
遮罩層157形成於抗反射塗層156上。遮罩層157亦可稱作硬遮罩層。在一些實施例中,遮罩層157包含金屬,其型態可為金屬氮化物如氮化鈦。遮罩層157的組成亦可為非金屬的氮化物如氮化矽、氮氧化物如氮氧化矽、或類似物。遮罩層157的形成方法可採用任何合適的沉積製程,比如原子層沉積、化學氣相沉積、電漿增強化學氣相沉積、上述之組合、或類似製程。
可進一步形成抗反射塗層158於遮罩層157上。抗反射塗層158亦可為無氮抗反射塗層,其組成可為氧化物如氧化矽,且其形成方法可採用電漿增強化學氣相沉積。在一些實施例中,未形成抗反射塗層158。
第15A-C圖至第22A-C圖係一些實施例中,圖案化抗反射塗層156、抗反射塗層158、與遮罩層157的中間階段其剖視圖。經由兩圖案化兩蝕刻製程,可圖案化抗反射塗層156、抗反射塗層158、與遮罩層157,其採用不同的微影製程形成相鄰的溝槽,因此相鄰的溝槽可彼此緊鄰而不會造成光學鄰近效應。在其他實施例中,可採用更多或更少的圖案化及/或蝕刻 步驟。
為了說明目的,第15A-C圖至第22A-C圖顯示兩圖案化兩蝕刻製程,其先圖案化接點106與108上的抗反射塗層156、抗反射塗層158、與遮罩層157,再圖案化接點102與104上的抗反射塗層156、抗反射塗層158、與遮罩層157。在其他實施例中,可採用不同的圖案化順序、可一起圖案化不同的接點組合、或可個別圖案化接點。
第15A-C至第18A-C圖顯示用於形成第一溝槽的第一圖案化-第一蝕刻製程的中間階段。在一些實施例中,第15A-C圖中的三層結構形成於抗反射塗層158上,其中三層結構包括底層160、底層160上的中間層162、以及中間層162上的上方層164。在一些實施例中,底層160與上方層164的組成可為光阻。中間層162的組成可為無機材料,其可為氮化物如氮化矽、氮氧化物如氮氧化矽、氧化物如氧化矽、或類似物。中間層162相對於上方層164與底層160可具有高蝕刻選擇性。如此一來,上方層164可作為圖案化中間層162時的蝕刻遮罩,而中間層162可作為圖案化底層160時的蝕刻遮罩。如第15A-C圖所示,圖案化上方層164以形成接點106與108上的開口166,其具有即將形成於介電層154中的金屬線路之圖案。
接著如第16A-C圖所示,採用圖案化的上方層164作為蝕刻遮罩並蝕刻中間層162,以將上方層164的圖案轉移至中間層162。在蝕刻穿過中間層162之後,可圖案化底層160如第17A-C圖所示,其中中間層162作為蝕刻遮罩。在圖案化底層160時,可消耗上方層164,亦可消耗中間層162。若在圖案化 底層160時未完全消耗中間層162,之後可移除殘留的中間層162。
接著採用底層160作為蝕刻遮罩,並蝕刻下方的抗反射塗層158。因此開口166延伸至抗反射塗層158中,且在蝕刻抗反射塗層158後的開口166露出遮罩層157的上表面。在圖案化抗反射塗層158時亦消耗底層160,雖然底層160的蝕刻速率小於中間層162(見第16A-C圖)與抗反射塗層158的蝕刻速率。因此在完成圖案化抗反射塗層158時,可減少底層160的厚度。上述步驟形成的結構如第17A-C圖所示。
在蝕刻之後,移除殘餘的底層160(其可包含光阻)。舉例來說,可在灰化製程中移除底層160,且一些實施例可採用氧移除底層160。上述步驟形成之結構如第18A-C圖所示。
第19A-C圖至第21A-C圖顯示圖案化抗反射塗層158以形成第二溝槽的第二圖案化第二蝕刻製程。在一些實施例中,第二三層結構形成於抗反射塗層158上,如第19A-C圖所示。第二三層結構包含底層216、底層216上的中間層218、與中間層218上的上方層220。如上所述,一些實施例的底層216與上方層220的組成可為光阻。中間層218的組成可為無機材料,其可為氮化物如氮化矽、氮氧化物如氮氧化矽、氧化物如氧化矽、或類似物。中間層218相對於上方層220與底層216可具有高蝕刻選擇性,因此上方層220可作為圖案化中間層218時所用的蝕刻遮罩,而中間層218可作為圖案化底層216時所用的蝕刻遮罩。上方層220經圖案化後形成開口168,其具有之後形 成於介電層154中的金屬線路圖案。
如前所述,可採用圖案化的上方層220作為蝕刻中間層218時的蝕刻遮罩,因此可將上方層220的圖案轉移至中間層218、底層216、以及抗反射塗層158中。上述結構如第20A-C圖所示。在轉移圖案之後,可移除剩餘的底層216(其可包含光阻)。在一些實施例中,底層216的移除方法可為採用氧的灰化製程。如此一來,抗反射塗層158包含開口166與168,如第21A-C圖所示。
接著如第22A-C圖所示,採用圖案化的抗反射塗層158作為蝕刻遮罩,並蝕刻遮罩層157以形成延伸至遮罩層157中的開口166與168。蝕刻製程將露出抗反射塗層156,其可作為蝕刻遮罩層157的蝕刻停止層。上述步驟可採用任何合適的蝕刻製程,比如濕蝕刻或乾蝕刻。
第23A-C圖至第28A-C圖顯示用以形成通孔圖案的兩圖案化兩蝕刻製程。第23A-C圖至第25A-C圖顯示第一通孔圖案的形成方法。如第23A-C圖所示,形成三層結構,其包含底層210、中間層212、與上方層214。上方層214經圖案化以包含開口170,其具有後續形成的通孔圖案。接著蝕刻中間層212、底層210、抗反射塗層156、與介電層154,使開口170延伸至介電層154中。上述步驟形成的結構如第24A-C圖所示。開口170的底部水平位於介電層154的上表面與下表面之間(如兩表面之間的中間處)。舉例來說,一些實施例可控制蝕刻製程的時間參數,在開口170的底部達到所需水平時停止蝕刻製程。在完成開口170時,可消耗上方層214與中間層212(見第 23A-C圖)。舉例來說,可在灰化製程中移除殘留的底層210,以形成第25A-C圖所示的結構。
如第26A-C至第28A-C圖所示,形成第二通孔圖案。如第26A-C圖所示,形成三層結構,其包含底層222、中間層224、與上方層226。底層222延伸至介電層154中的開口170(見第25A-C圖)。上方層226經圖案化後包含開口172,其具有後續形成的通孔圖案。接著蝕刻中間層224、底層222、抗反射塗層156、與介電層154,且開口172延伸至介電層154中。上述步驟形成之結構如第27A-C圖所示。開口172的底部水平亦位於介電層154的上表面與下表面之間(比如上表面與下表面之間的中間處)。在一些實施例中,可控制蝕刻製程的時間參數,以在開口172的底部達到所需水平時停止蝕刻製程。在完成開口172時,可消耗上方層226與中間層224(見第26A-C圖)。舉例來說,可在灰化製程中移除殘留的底層222,以形成第28A-C圖所示的結構。
接著如第29A-C圖所示,進行蝕刻製程如非等向蝕刻製程,以蝕刻介電層154。遮罩層157作為蝕刻遮罩。藉由蝕刻製程可形成溝槽174。蝕刻可採用具有氟與碳的含氟氣體,其中氟用於蝕刻,而碳具有保護通孔開口176與溝槽174之側壁的效果。舉例來說,用於蝕刻的製程氣體可包含八氟環丁烷及/或四氟化碳。在蝕刻步驟中,開口170與172向下延伸至介電層154的底部以形成開口,其於第29A-C圖中標示為通孔開口176。通孔開口176露出蝕刻停止層的上方層152。在蝕刻製程之後,溝槽174的底部水平位於介電層154的上表面與下表面之 間。
接著蝕刻蝕刻停止層的上方層152。在蝕刻製程之後,通孔開口176延伸至蝕刻停止層的上方層152中。在一些實施例中,部份地蝕刻蝕刻停止層的上方層152。蝕刻停止層的上方層152與蝕刻停止層的底層151的保留部份,可保護下方的接點102、104、106、與108免於後續製程損傷。後續製程可為移除遮罩層157的製程(見第30A-C圖)。上述步驟形成的結構如第29A-C圖所示。
接著如第30A-C圖所示,移除遮罩層157。移除遮罩層157的方法可採用任何合適製程。在一些實施例中,可採用濕蝕刻製程移除遮罩層157。蝕刻停止層的上方層152與蝕刻停止層的底層151的保留部份可保護下方的接點102、104、106、與108免於濕蝕刻損傷。上述步驟形成的結構如第30A-C圖所示。
接著如第31A-C圖所示,進行一或多道額外蝕刻製程,以進一步擴大通孔開口176。額外蝕刻製程可蝕刻穿過蝕刻停止層的上方層152,並蝕刻穿過部份的蝕刻停止層的底層151。額外蝕刻製程可採用任何合適的蝕刻製程。在一些實施例中,額外蝕刻製程可包含乾蝕刻製程,以及後續的濕式清潔製程。
如第31A-C圖所示,僅部份地蝕刻蝕刻停止層的底層151,以避免接點102、104、106、與108經通孔開口176暴露至大氣。若通孔開口176延伸並蝕刻穿過蝕刻停止層的底層151,則接點102、104、106、與108將暴露至外界大氣。當接 點102、104、106、與108將暴露至外界大氣時,可能氧化接點102、104、106、與108。舉例來說,接點102、104、106、及/或108可包含銅,當銅暴露至大氣時可能發生氧化以產生氧化銅。此態樣可能損傷接點,並降低接點的可信度及/或降低製程良率。
在習知技術中,可進行爐烤以自暴露至大氣的金屬內連線線路移除氧化物。爐烤的高溫可能或使金屬上的氧化銅還原為銅,而氧化銅中的氧與氫反應形成水。一般而言,爐烤可持續兩個小時以上。接著,習知製程將含有鰭狀場效電晶體裝置的晶圓輸送至真空環境,以形成阻障層與銅晶種層。然而在輸送晶圓時,晶圓將暴露至外界大氣,因此又形成薄氧化銅層於接點102、104、106、及/或108的任何露出部份上。如此一來,在真空環境下需進行額外的移除製程以移除薄氧化銅層。移除薄氧化銅層的製程可包含除氣製程(高溫且不導入任何氫)以移除濕氣。然而長爐烤時間以及真空環境下的額外氧化銅移除製程,會負面地影響製程產能。氧化銅的移除製程亦增加生產成本。
在一些實施例中,蝕刻停止層的底層151的部份180保留於接點102、104、106、及/或108上,直到鰭狀場效電晶體裝置形成其上的晶圓輸送至真空環境。如此一來,部份180可保護接點102、104、106、及/或108免於因暴露至大氣而氧化,直到鰭狀場效電晶體裝置形成其上的晶圓輸送至真空腔室為止。如第31A-C圖所示,在蝕刻穿過蝕刻停止層的底層151之前可停止蝕刻製程,且在蝕刻製程之後保留蝕刻停止層的底 層151的部份180。部份180保留於接點102、104、106、及/或108上,直到鰭狀場效電晶體裝置形成其上的晶圓輸送至真空腔室。在真空腔室中,導電元件將形成於通孔開口176中。如搭配第32圖與第33A-C圖說明的下述內容,在晶圓輸送至真空腔室之後將移除部份180,因此後續形成於通孔開口176中的導電結構可電性連接至接點102、104、106、及/或108。然而,藉由將晶圓輸送至真空腔室之前未蝕刻穿過部份180,可減少或避免氧化接點102、104、106、與108,且一些實施例可縮短或省略爐烤步驟及/或除氣製程。如此一來,可減少製程時間與製程成本,並可達較高的製程良率。
如第31A-C圖所示,部份180的厚度T1可介於約0.1Å至約5Å之間。當部份180的厚度T1大於或等於約0.1Å時,部份180可避免接點102、104、106、與106暴露至大氣,即可避免或減少接點102、104、106、與106的氧化。舉例來說,當部份180的厚度T1大於或等於約0.1Å時,部份80可在輸送晶圓至真空腔室中避免接點102、104、106、與106因暴露至外界大氣而氧化。當部份180的厚度小於或等於約5Å時,可在真空腔室中有效地移除部份180,如搭配第32圖與第33A-C圖說明的下列內容所述。
接著如第32圖所示,將鰭狀場效電晶體裝置30形成其上的晶圓,輸送至製程腔室202中。在製程腔室202中進行製程時,以晶圓座204支撐鰭狀場效電晶體裝置30。製程腔室202可包含製程設備206,其可包含用以產生製程腔室中真空環境的設備、用以蝕刻部份180的設備、用以形成阻障層182(見 第34A-C圖)的設備、以及用以形成晶種層183(見第35A-C圖)於溝槽174與通孔開口176中的設備。
如第33A-C圖至第35A-C圖所示,在製程腔室202中產生真空環境之後,在製程腔室202(見第32圖)中對鰭狀場效電晶體裝置30進行的製程。在第33A-C圖中,進行預清潔製程,以移除部份180。接著在第34A-C圖中,形成阻障層182。在第35A-C圖中,形成晶種層183。
在第33A-C圖中,進行預清潔製程以移除部份180。將製程氣體導入製程腔室202中,其用以蝕刻部份180並露出接點102、104、106、與108。在一些實施例中,製程氣體為之後用以沉積阻障層182(見第34A-C圖)的前驅物。製程氣體可包含氟化碳,比如四氟化碳氣體、八氟環丁烷氣體、或類似物。在預清潔製程中,製程腔室202可具有低壓。舉例來說,製程腔室202中的壓力可小於約40mTorr。由於預清潔製程在製程腔室202(見第32圖)中的真空環境下蝕刻部份180,接點102、104、106、與108並未暴露至外界大氣,因此可減少或避免接點102、104、106、與108的氧化。
在第34A-C圖中,形成阻障層182。阻障層182形成於真空環境下的製程腔室202中。阻障層182可包含導電材料如氮化鈦,不過亦可改用其他材料如氮化鉭、鈦、介電物、或類似物。阻障層182的形成方法可採用化學氣相沉積製程如電漿增強化學氣相沉積,或物理氣相沉積製程。如前所述的一些實施例中,阻障層182為物理氣相沉積的氮化鉭,其採用鉭與氮為前驅物。在一些實施例中,在將形成阻障層182的前驅物導 入製程腔室202之前,先將蝕刻製程氣體導入製程腔室202,以自通孔開口176蝕刻部份180,並露出接點102、104、106、及/或108。在一些實施例中,形成阻障層182的前驅物可與蝕刻製程氣體同時導入製程腔室202。在一些實施例中,阻障層182的厚度介於約10Å至約1000Å之間。然而可採用其他製程如濺鍍或有機金屬化學氣相沉積。阻障層182可與下方的溝槽174與通孔開口176的形狀共形。
在第35A-C圖中,形成晶種層183。晶種層183形成於真空環境下的製程腔室202中。在一些實施例中,晶種層183可包含銅,但亦可採用其他合適材料。晶種層183的形成方法可為沉積製程如原子層沉積、物理氣相沉積、電漿增強化學氣相沉積、或類似方法。可在晶種層183上進行電漿氬處理。在一些實施例中,在晶種層183上進行電漿氬處理,可避免晶種層183在暴露至外界大氣時氧化。舉例來說,一些實施例在晶種層183上進行電漿氬處理,可使晶種層183在暴露至外界大氣約6小後仍不會明顯氧化。
接著如第36A-C圖所示,自製程腔室202移出鰭狀場效電晶體裝置30形成其上的晶圓,並將溝槽174與通孔開口176的其餘部份填入導電材料184。導電材料184可包含銅,但亦可改用其他合適材料如鋁、合金、摻雜的多晶矽、上述之組合、或類似物。導電材料184的形成方法可為電鍍銅至晶種層183上,以填滿並填出溝槽174。如第36A-C圖所示的一些實施例,晶種層183(見第35A-C圖)與導電材料184之間無可分辨的界面。在其他實施例中,晶種層183與導電材料184之間存在可 分辨的界面。
一旦填滿溝槽174,則移除超出溝槽174的多餘阻障層182與多餘導電材料184,以形成導電結構186。此外亦可移除抗反射塗層156的任何殘留部份。在一些實施例中,移除多餘阻障層182、多餘導電材料184、與抗反射塗層156的殘餘部份的製程可為研磨製程如化學機械研磨,但亦可為任何合適的移除製程。上述製程形成的結構如第37A-C圖所示。
在後續製程中,額外的介電層與導電結構可形成於介電層154與導電結構186上,以形成用於鰭狀場效電晶體裝置的內連線區。導電結構186與後續形成的導電結構(未圖示)可依特定設計朝任何方向延伸。綜上所述,內連線區可實施接腳以用於完成的封裝,其不同於接點102、104、106、與108的圖案,在放置外部連接物(未圖示,可形成於內連線區上以連接鰭狀場效電晶體裝置與其他封裝或構件)時具有更多彈性。
第15A-C至第37A-C圖所示的實施例中,導電結構186直接形成於接點102、104、106、與108上並與其接觸。在其他實施例中,導電結構186形成於內連線中的較高層。舉例來說,導電結構186可形成於第五層、第六層、或其他層的金屬層。
第1至36A-C圖顯示的實施例中,導電結構186形成於鰭狀場效電晶體30上。在其他實施例中,導電結構186形成於其他種類的電晶體上,比如平面場效電晶體。
如前所述,在製程腔室中的真空環境下形成導電結構。蝕刻穿過接點上部份的蝕刻停止層以形成通孔開口,且 接點即將電性連接至導電結構。部份的蝕刻停止層保留為未蝕刻,直到裝置形成其上的晶圓輸送至製程腔室中,並在腔室中產生真空環境。在產生真空環境之後,採用製程氣體以蝕刻穿過部份的蝕刻停止層,並露出下方的接點。接著形成導電元件於開口中。由於在形成導電元件時,下方的接點並未暴露至外界大氣,可避免或減少下方的接點氧化。可省略烘烤製程步驟與除氣步驟,並可縮短製程時間。上述製程可增加製程良率。
一些實施例提供裝置的形成方法。方法包括形成開口於介電層與蝕刻停止層中,其中開口只部份地延伸穿過蝕刻停止層。方法亦包括產生真空環境於裝置周圍。方法亦包括在產生真空環境於裝置周圍之後,蝕刻穿過蝕刻停止層以延伸開口,並露出第一導電結構。方法亦包括形成第二導電結構於開口中。在一實施例中,在形成開口後保留蝕刻停止層的一部份於第一導電結構上,且部份的厚度介於約0.1Å至約5Å之間。在一實施例中,形成第二導電結構的步驟包括:形成阻障層於開口中;形成晶種層於阻障層上;以及電鍍導電材料於晶種層上。在一實施例中,在外界大氣環境中形成開口於介電層中,且在形成阻障層與晶種層時維持真空環境。在一實施例中,採用製程氣體蝕刻穿過蝕刻停止層以延伸開口並露出第一導電結構,且製程氣體含碳與氟。在一實施例中,形成第二導電結構於開口中的步驟包括:形成阻障層;且在施加製程氣體至開口中時同時施加另一氣體,且另一氣體作為形成阻障層的前驅物。在一實施例中,形成開口的步驟包括形成底部與上側部,且平面圖中的上側部大於底部。在一實施例中,蝕刻停止層包 括第一蝕刻停止層與第二蝕刻停止層,且在產生真空環境之前的開口延伸穿過第一蝕刻停止層。在一實施例中,形成開口於介電層與蝕刻停止層中的步驟包括:在第一光阻圖案化製程中形成第一開口於介電層中;採用第二光阻圖案化製程以形成第二開口於介電層中;以及在蝕刻製程中延伸第一開口與第二開口。
在一些實施例中,提供裝置的形成方法。方法包括形成蝕刻停止層於第一導電結構上,並形成介電層於蝕刻停止層上。方法亦包括形成開口於介電層與蝕刻停止層中,且開口的下表面位於蝕刻停止層的上表面與下表面之間。方法亦包括蝕刻穿過蝕刻停止層,以延伸開口並露出第一導電結構,使第一導電結構暴露於真空環境中。方法亦包括形成第二導電結構於開口中。在一實施例中,蝕刻停止層包括底層與上側層,且在形成開口之後的開口其下表面位於蝕刻停止層的底層中。在一實施例中,底層包括氮化鋁。在一實施例中,形成第二導電結構的步驟包括:在真空環境中形成阻障層;在真空環境中形成晶種層於阻障層上;形成導電材料於晶種層上;以及平坦化導電材料的上表面。在一實施例中,形成開口於介電層中之後,開口的下表面與蝕刻停止層的下表面之間的距離介於約0.1Å至約5Å之間。在一實施例中,開口在平面圖中包含厚部與薄部,且薄部延伸至蝕刻停止層中。在一實施例中,第一導電結構包括銅。
一些實施例提供裝置的形成方法。方法包括形成第一蝕刻停止層於第一導電結構上。方法亦包括形成第二蝕刻 停止層於第一蝕刻停止層上。方法亦包括形成介電層於第二蝕刻停止層上。方法亦包括形成開口於介電層與第二蝕刻停止層中,並部份地蝕刻第一蝕刻停止層以延伸開口。在部份地蝕刻第一蝕刻停止層之後,第一蝕刻停止層的一部份覆蓋開口下的第一導電結構。方法亦包括產生真空環境於開口中,並蝕刻穿過第一蝕刻停止層的部份以延伸開口,並經由開口露出第一導電結構。在一實施例中,方法更包括形成阻障層於開口中,其中用於蝕刻穿過第一蝕刻停止層的部份之製程氣體導入開口時,同時導入用於形成阻障層的前驅物。在一實施例中,方法更包括形成晶種層於阻障層上;在晶種層上進行電漿氬處理;自開口移除真空環境;並進行電鍍製程以形成導電材料於晶種層上。在一實施例中,第一蝕刻停止層的部份其厚度介於約0.1Å至約5Å之間。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明精神與範疇,並可在未脫離本發明之申請專利範圍的精神與範疇的前提下進行改變、替換、或更動。
Claims (1)
- 一種裝置的形成方法,包括:形成一開口於一介電層與一蝕刻停止層中,其中該開口只部份地延伸穿過該蝕刻停止層;產生一真空環境於該裝置周圍;在產生該真空環境於該裝置周圍之後,蝕刻穿過該蝕刻停止層以延伸該開口,並露出一第一導電結構;以及形成一第二導電結構於該開口中。
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