TWI595598B - 鈷互連技術 - Google Patents
鈷互連技術 Download PDFInfo
- Publication number
- TWI595598B TWI595598B TW104139103A TW104139103A TWI595598B TW I595598 B TWI595598 B TW I595598B TW 104139103 A TW104139103 A TW 104139103A TW 104139103 A TW104139103 A TW 104139103A TW I595598 B TWI595598 B TW I595598B
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- Prior art keywords
- cobalt
- liner
- pad
- opening
- barrier
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- 239000010941 cobalt Substances 0.000 title claims description 168
- 229910017052 cobalt Inorganic materials 0.000 title claims description 168
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 title claims description 146
- 238000000034 method Methods 0.000 title claims description 107
- 230000004888 barrier function Effects 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 33
- -1 cobalt nitride Chemical class 0.000 claims description 25
- 239000002243 precursor Substances 0.000 claims description 23
- 238000005229 chemical vapour deposition Methods 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 14
- 238000011049 filling Methods 0.000 claims description 14
- 238000007747 plating Methods 0.000 claims description 11
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 239000012528 membrane Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 33
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 239000003792 electrolyte Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- PPWNCLVNXGCGAF-UHFFFAOYSA-N 3,3-dimethylbut-1-yne Chemical group CC(C)(C)C#C PPWNCLVNXGCGAF-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LNIPHKNRMZVGSU-UHFFFAOYSA-N [Co].[Co].CC(C#C)(C)C Chemical compound [Co].[Co].CC(C#C)(C)C LNIPHKNRMZVGSU-UHFFFAOYSA-N 0.000 description 2
- 125000002252 acyl group Chemical group 0.000 description 2
- 239000007833 carbon precursor Substances 0.000 description 2
- 238000009833 condensation Methods 0.000 description 2
- 230000005494 condensation Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 238000000995 aerosol-assisted chemical vapour deposition Methods 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910001507 metal halide Inorganic materials 0.000 description 1
- 150000005309 metal halides Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- CXXKWLMXEDWEJW-UHFFFAOYSA-N tellanylidenecobalt Chemical compound [Te]=[Co] CXXKWLMXEDWEJW-UHFFFAOYSA-N 0.000 description 1
- 150000004772 tellurides Chemical group 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 239000011364 vaporized material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
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- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
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Description
本揭露是關於鈷互連技術。
在製備積體電路(IC)時,會在晶圓上形成元件並透過導電互連層來連接。可在所謂的中段(MEOL)製程或後段(BEOL)製程中形成這些導電互連層。MEOL和BEOL製程的相似之處在於兩者都會在介電層形成開孔(如,介電層中之接點開孔、渠道或通孔),且之後以導電性材料來填充這些開孔。MEOL和BEOL不同之處在於MEOL通常在製造過程中較早的階段進行,且可視為在基板中形成導電性區域(譬如源極/汲極)之接點的製程;而BEOL通常在製造過程中較晚的階段進行,且可視為在MEOL所形成之接點上方形成後續金屬化層與通孔之製程。
於某些實施方式中,本揭露關於用以製備積體電路元件的方法。所述方法包括於基板上形成介電層。介電層包括設於介電層中之一開孔。所述方法進一步包括沿著開孔的底部與側壁表面形成第一鈷襯墊。所述方法進一步包括於第一鈷襯墊之裸露表面上形成阻障襯墊,以及以鈷主體層來填充開孔的剩餘空間。
於其他實施方式中,本揭露係關於用以製備積體電路元件的方法。所述方法包括於基板上形成一中段製程(MEOL)結
構,並於基板上形成介電層。所述方法進一步包括形成延伸通過介電層之開孔,以使MEOL結構之上表面的至少一部分裸露,以及在矽層的上表面的裸露部分上並沿著開孔的側壁向上延伸而形成第一鈷襯墊。所述方法進一步包括在第一鈷襯墊的裸露表面上形成鈷氮化物襯墊,並以鈷主體層填充開孔之剩餘空間。所述方法進一步包括在填充鈷主體層之後,進行退火製程,以在第一鈷襯墊和MEOL結構上表面的裸露部分間之介面形成矽化物膜。
在又一些實施方式中,本揭露係關於一種積體電路元件。所述積體電路元件包括半導體基板以及覆設於基板上之介電層,且介電層有一開孔設於介電層中。所述積體電路元件進一步包括沿著開孔之側壁表面設置的第一鈷襯墊,以覆蓋第一鈷襯墊的阻障襯墊。積體電路元件進一步包括填充開孔之剩餘空間的鈷栓。
100a、100b‧‧‧積體電
102‧‧‧基板
104‧‧‧半導體結構
106‧‧‧介電層
108‧‧‧第一鈷襯墊
110‧‧‧阻障襯墊
111‧‧‧鈷栓
112‧‧‧鈷晶種襯墊
114‧‧‧鈷主體層
116‧‧‧矽化物膜
118‧‧‧金屬層
120‧‧‧導電互連結構
122‧‧‧開孔
200‧‧‧方法
202-225‧‧‧動作
300、400、500、600、700、800‧‧‧剖面圖
302‧‧‧蝕刻劑
510‧‧‧鈷氮化物襯墊
在閱讀了下文實施方式以及附隨圖式時,能夠最佳地理解本揭露的多種態樣。應注意到,根據本領域的標準作業習慣,圖中的各種特徵並未依比例繪製。事實上,為了能夠清楚地進行描述,可能會刻意地放大或縮小某些特徵的尺寸。
圖1A繪示根據某些實施方式具有互連結構之積體電路的剖面圖。
圖1B繪示根據某些其他實施方式具有互連結構之積體電路的剖面圖。
圖2繪示根據某些實施方式填充開孔之方法的流程圖。
圖3-8繪示之積體電路的剖面圖係用以說明根據某些實施方式用於填充建立互連之開口的方法。
圖9繪示根據某些實施方式用於沈積互連之製程系
統。
以下揭示內容提供了多種實施方式或例示,其能用以實現本揭示內容的不同特徵。下文所述之元件與配置的具體例子係用以簡化本揭示內容。當可想見,這些敘述僅為例示,其本意並非用於限制本揭示內容。舉例來說,在下文的描述中,將一第一特徵形成於一第二特徵上或之上,可能包含某些實施例其中所述的第一與第二特徵彼此直接接觸;且也可能包含某些實施例其中還有而外的元件形成於上述第一與第二特徵之間,而使得第一與第二特徵可能沒有直接接觸。此外,本揭示內容可能會在多個實施例中重複使用元件符號和/或標號。此種重複使用乃是基於簡潔與清楚之目的,且其本身不代表所討論的不同實施例和/或組態之間的關係。
再者,在此處使用空間上相對的詞彙,譬如「之下」、「下方」、「低於」、「之上」、「上方」及與其相似者,可能是為了方便說明圖中所繪示的一元件或特徵相對於另一或多個元件或特徵之間的關係。這些空間上相對的詞彙其本意除了圖中所繪示的方位之外,還涵蓋了裝置在使用或操作中所處的多種不同方位。可能將所述設備放置於其他方位(如,旋轉90度或處於其他方位),而這些空間上相對的描述詞彙就應該做相應的解釋。
在中段製程(MEOL)互連層中,會使用矽化工藝來形成矽化物接點。在現代半導體製程(譬如互補金屬氧化物半導體(CMOS)或雙極CMOS製程)中,常利用矽化工藝來形成矽化物層,以對譬如源極/汲極區域、基極區域、集電極區域、射極區域或多晶矽閘極提供歐姆接觸。通常,形成矽化物層的第一步是形成和下方矽區域(如,下方MEOL結構)直接接觸之金屬襯墊(如,鈦襯墊)。之後利用物理氣相沈積(PVD)製程或化學氣相沈積(CVD)
製程在一真空腔室中,於金屬襯墊上形成阻障襯墊(如,鈦氮化物)。接著,從真空腔室中移出工作件,並進行退火製程。此一退火製程會加熱金屬襯墊以及相鄰的下方矽區域,以形成矽化物層。之後,將工作件送回真空腔室內,並形成導電栓以填充開孔的剩餘空間。
已理解到,在形成金屬襯墊及阻障襯墊之後(即,在後續退火製程之前)將工作件由真空腔室移出有其缺點。大氣環境可能會導致金屬襯墊和/或阻障襯墊的氧化,這會增加所得到之電阻值。雖然可利用氧化還原工藝來消除此種氧化,移除氧化材料會導致空洞的產生。這些空洞會導致不佳的電性連接且可能會使可靠度降低。
因此,本揭露係關於一種改良的方法,其可用以形成MEOL互連層與相關元件,以降低其接點電阻值、減少空洞並提升可靠度。於某些實施方式中,所述方法包括於一真空腔室中,原位形成金屬襯墊、阻障襯墊以及栓的至少一部分(譬如用於鍍覆之晶種層)。在形成栓之部分後,進行退火製程,以使得金屬襯墊和下方矽區域混合,因而形成矽化物層。藉由將金屬襯墊及阻障襯墊保持在連續真空的環境下(如,不將金屬襯墊及阻障襯墊暴露於製造廠的大氣環境下),可以限制氧化作用且可減少空洞的產生。於某些實施方式中,金屬襯墊及栓材料係由鈷所製成,而阻障襯墊係由鈷氮化物所製成。由於鈷和鈷氮化物可在室溫或相對較低的溫度下形成,凝結作用受到限制,並能夠進一步提升元件的效能。
圖1A繪示根據某些實施方式之積體電路100a的剖面圖。
於某些實施方式中,積體電路100a包括覆設於基板102上之介電層106。在垂直延伸而通過介電層106之開孔122中,設有
導電互連結構120。從開孔122的周邊到中心,導電互連結構120依序包括第一鈷襯墊108、阻障襯墊110以及鈷栓111。矽化物膜116係設於第一鈷襯墊108與半導體結構104間之介面,例如基板102中之矽區域。矽化物膜116包括矽原子與鈷原子之化合物,能夠在半導體結構104和其上的導電互連結構120之間提供晶格匹配與良好的接觸(如,歐姆接觸)。
第一鈷襯墊108係沿著開孔122的底部與側壁表面所設置。於某些實施方式中,第一鈷襯墊108和介電層106直接接觸。於某些實施方式中,第一鈷襯墊108為或含鈷的化合物。第一鈷襯墊108的厚度為約20Å至約30Å。在某些其他實施方式中,第一鈷襯墊108的厚度為約10Å至約50Å。在一些進一步的實施方式中,第一鈷襯墊108的厚度為約10Å至約200Å。
阻障襯墊110(譬如,鈷氮化物(CoN)襯墊),係設於第一鈷襯墊108上,並覆蓋第一鈷襯墊108的底部與側壁表面。阻障襯墊110可用作一種矽化物形成之限制材料,以防止矽化物材料擴散通過阻障襯墊110。於某些實施方式中,阻障襯墊110的厚度為約10Å至約20Å。在某些其他實施方式中,阻障襯墊110的厚度為約10Å至約30Å。在一些進一步的實施方式中,阻障襯墊110的厚度為約10Å至約100Å。
鈷栓111可包括多個不同的層,例如鈷晶種襯墊112以及鈷主體層114,其填充了開孔122的剩餘空間。於某些實施方式中,鈷晶種襯墊112為鈷或含鈷的化合物。於某些實施方式中,鈷晶種襯墊112的厚度為約20Å至約50Å。在某些其他實施方式中,鈷晶種襯墊112的厚度為約20Å至約300Å。於某些實施方式中,鈷主體層114的厚度為約200nm至約600nm。在某些其他實施方式中,鈷栓111可以是由利用單一沈積製程所製得之均質材料所組成的連續性導電本
體,特別是當開孔122的高寬比非常小的時候;且在這些情形中,可觀察到鈷主體層114和阻障襯墊110直接接觸。
半導體結構104係設於基板102內並直接位於開孔122下方。於某些實施方式中,半導體結構104為一中段製程(MEOL)結構。於某些實施方式中,中段製程(MEOL)結構可以是半導體元件(包括經摻雜半導體結構)的主動區域,例如場效應電晶體的源極/汲極區域或多晶矽閘極。作為一實施例,中段製程(MEOL)結構可以是磊晶生長的SiGe或SiP區域,其可作為源極/汲極區域,且及可延伸以高於基板102之上表面。於其他實施方式中,MEOL結構可以是利用離子佈植或向外擴散所形成之源極/汲極區域,且其及最高區域和基板102之上表面相應。
圖1B繪示根據某些實施方式之積體電路100b的剖面圖。
於某些實施方式中,積體電路100b包括覆設於基板102上的半導體結構104。由圖1B可以看出,於某些實施方式中,半導體結構104的上表面有一凹面上表面,且矽化物膜116向上延伸到達鈷氮化物襯墊510之底面。因此,雖然圖1A所繪示之第一鈷襯墊108係延伸至矽化物膜116上,以將矽化物膜116和阻障襯墊110隔離;圖1B所繪示的實施例是以矽化物膜116從所述的凹面表面向上延伸而直接和阻障襯墊110的下方表面鄰接。鈷氮化物襯墊510仍然覆蓋鈷栓111之底部與側壁表面,且可用作矽化物形成之限制材料,以保護鈷栓111不發生矽化。可將金屬層118覆設於介電層106與導電互連結構120上。於某些實施方式中,金屬層118可和導電互連結構120直接接觸。可利用和栓材料相同或不同的材料來製備金屬層118。譬如,可利用含銅或鈷或其組合之化合物來製備金屬層118。
圖2繪示根據某些實施方式,用於填充建立互連之開
孔的方法200之例示性流程圖。於某些實施方式中,方法200可運用於中段(MEOL)製程,以形成接點栓。雖然下文以一夕咧的動作或事件來描述所繪示之方法200,當可理解不應將所示之動作或事件的順序理解為對本揭露之限制。譬如,某些動作可利用和此處所敘述和/或繪示的不同的順序和/或可和其他動作或事件同時進行。此外,並非所有繪示的動作都是實現此處所數之一或多種態樣或實施方式所必須的。再者,此處所述的一或多種動作可利用一或多種分別的動作和/或階段來進行。
在動作202,在覆蓋於半導體結構上之介電層內形成開孔。上述半導體結構可形成於基板之內或之上。
在動作203,如下文所詳述,在原位形成鈷襯墊、阻障襯墊以及鈷晶種層,以分別在動作204、210與216中填充開孔。由於鈷襯墊、阻障襯墊及鈷晶種層是在一腔室內於持續的真空下依序形成(如,並未將半導體結構暴露於製造廠的周遭大氣環境中),可顯著縮短製造時間。亦可減少非蓄意的氧化限向,且可提升元件品質。於某些實施方式中,鈷襯墊、阻障襯墊以及鈷晶種層可利用化學氣相沈積(CVD)製程來形成。在某些其他實施方式中,鈷襯墊、阻障襯墊以及鈷晶種層可利用物理氣相沈積(PVD)製程譬如濺鍍沈積製程來形成。
在動作204,將鈷襯墊沈積於開孔的側壁與下表面上,並與半導體基板直接接觸。於某些實施方式中,鈷襯墊為鈷或含鈷的化合物。於某些實施方式中,利用動作206、208及209來形成鈷襯墊。
在動作206,將鈷前驅物沈積於開孔的表面上。於某些實施方式中,鈷前驅物可包含六碳基二鈷叔丁基乙炔(CCTBA)。
在動作208,以電漿處理鈷前驅物。於某些實施方式
中,以含氫的電漿進行處理。
在動作209,重複動作206與208,以達到所欲之鈷襯墊厚度。
在動作210,將阻障襯墊沈積於鈷襯墊,並和鈷襯墊直接接觸。於某些實施方式中,阻障襯墊為鈷氮化物襯墊。於某些實施方式中,阻障襯是利用動作212、214及215所形成。
在動作212,將阻障前驅物沈積於鈷襯墊的表面上。於某些實施方式中,阻障前驅物可包含六碳基二鈷叔丁基乙炔(CCTBA)或三碳基亞硝醯鈷(Co(CO)3NO3NO)。
在動作214,以電漿處理阻障前驅物。於某些實施方式中,以含有氫、氮或氨的電漿進行處理。
在動作215,重複動作212與214以達到所欲之阻障襯墊厚度。
在動作216,將鈷晶種層沈積於阻障襯墊上。於某些實施方式中,鈷晶種層為元素鈷或含鈷化合物。於某些實施方式中,鈷晶種層是利用動作218、220及221所形成。
在動作218,將鈷晶種前驅物沈積於阻障襯墊的表面上。於某些實施方式中,鈷晶種前驅物可包含六碳基二鈷叔丁基乙炔(CCTBA)。
在動作220,以電漿處理鈷晶種前驅物。於某些實施方式中,以含氫電漿進行處理。
重複動作221、動作218及220以到所欲之鈷晶種層厚度。
在動作222,形成鈷主體層以填充開孔之剩餘空間。於某些實施方式中,鈷主體層為鈷或含鈷的化合物。於某些實施方式中,鈷主體層是利用鍍覆製程所形成。於多種實施方式中,鍍覆製程
可包括電化學電鍍製程或無電電鍍製程。於某些實施方式中,用來來移除形成於鈷晶種層上之鈍化膜的化學溶液亦可用作鍍覆製程之電解液。在某些其他實施方式中,鈷主體層是利用PVD製程或CVD製程來沈積,且可在和動作203中鈷襯墊及阻障襯墊的形成在原位進行。
在動作224,在以鈷主體層填充開孔之剩餘空間之後,進行退火製程。退火製程會使得鈷襯墊和下方半導體結構反應,以在鈷矽化物襯墊及下方半導體結構間之介面形成矽化物膜。
圖3-8的剖面圖繪示根據某些實施方式,用以填充積體晶片之金屬互連的開孔之方法。雖然圖3-8是參照方法200來描述,當可理解,圖3-8所示之結構不限於此種方法200,且可作為一種獨立於方法之外的結構。相似地,雖然參照圖3-8來描述此方法,當可理解,所述方法不限於圖3-8所示之結構,且可獨立於圖3-8所示結構而存在。
圖3繪示某些實施方式中,對應於動作202之剖面圖300。
如剖面圖300所示,半導體結構104係形成於基板102。於某些實施方式中,基板102可以是譬如矽塊材基板或也可以是二元半導體基板(如,GaAs)、三元半導體基板(如,AlGaAs)或更高階的半導體基板。在許多情形中,於製備時,基板102可以是碟狀晶圓,其直徑為例如英吋(25mm);2英吋(51mm);3英吋(76mm);4英吋(100mm);5英吋(130mm)或125mm(4.9英吋);150mm(5.9英吋,通常稱為"6吋");200mm(7.9英吋,通常稱為"8吋");300mm(11.8英吋,通常稱為"12吋");或450mm(17.7英吋,通常稱為"18寸")。於某些實施方式中,半導體結構104可以是MEOL結構,譬如半導體元件之主動區域。譬如,半導體結構104可以是場效應電晶體的經摻雜源極/汲極區域或多晶矽閘極。作為一實
施例,半導體結構104可透過離子佈植而形成,或藉由於基板102內形成凹槽並以應變誘導源極/汲極材料(如,磊晶生長之SiP或SiGe)來填充凹槽。於某些實施方式中,半導體結構104可延伸高於基板102之上表面。
一介電層106形成於半導體結構104及基板102上。於某些實施方式中,介電層106可以是二氧化矽(SiO2)層,其介電常數約為3.9。於其他實施方式中,介電層106可以是多孔或故態低介電常數介電層,其介電常數小於3.9。
一開孔122形成於介電層106內且位於半導體結構104上方。於某些實施方式中,將介電層106和蝕刻劑302接觸,其可用以根據先前設於介電層106上之遮罩(圖中未繪示)而移除介電層106之未遮蔽部分,以形成開孔122。於多種實施方式中,蝕刻劑302可包括乾式蝕刻劑,其含有含氟之蝕刻化學物質(如,CF4、CHF3、C4F8等)。於其他實施方式中,蝕刻劑302可包括濕式蝕刻劑,其包括氫氟酸(HF)。開孔122垂直地延伸穿過介電層106到達下方半導體結構104。於某些實施方式中,開孔122可垂直延伸通過形成於基板102與介電層106之間的蝕刻停止層(圖中未繪示)。於某些實施方式中,開孔122可包其中形成有導電互連層之含渠道或通孔。於某些實施方式中,開孔122可利用雙層鑲嵌製程來形成,其包括在通孔上形成渠道線。雙層鑲嵌製程可以是渠道優先製程、通孔優先製程或自動對準製程。開孔122也可以是基板通孔(TSV)開孔。
圖4繪示某些實施方式中,對應於動作204之剖面圖400。
如剖面圖400,利用PVD製程或CVD製程,將第一鈷襯墊108沈積於開孔122的側壁與下表面上。當可想見,在此處,PVD一詞可涵蓋任何種類的製程,包括但不限於蒸發並連同後續凝結、濺
鍍或電漿強化濺鍍;CVD一詞可涵蓋任何種類的CVD製程,包括但不限於電漿強化CVD、遠端電漿強化CVD、原子層CVD、快速熱CVD,氣溶膠輔助CVD等。於某些實施方式中,第一鈷襯墊108由開孔122向外延伸至介電層106之上表面上。
圖5繪示某些實施方式中,對應於動作210之剖面圖500。
如剖面圖500,將鈷氮化物襯墊510形成於第一鈷襯墊108上。鈷氮化物襯墊510作為一阻障襯墊。可利用CVD製程來形成鈷氮化物襯墊510。可在相對較低的溫度((低於約200℃))下,形成鈷氮化物襯墊可以是。在形成了阻障襯墊110之後,將工作件保持在真空腔室內,以供後續沈積。
圖6繪示某些實施方式中,對應於動作216之剖面圖600。
如剖面圖600,利用CVD製程,將鈷晶種襯墊112形成於鈷氮化物襯墊510上。
圖7繪示某些實施方式中,對應於動作222之剖面圖700。
如剖面圖700,形成鈷主體層114以填充開孔122之剩餘空間。於某些實施方式中,鈷主體層114是利用鍍覆製程所形成。於多種實施方式中,鍍覆製程可包括電化學電鍍製程或無電電鍍製程。於某些實施方式中,用來由鈷晶種層112移除鈍化膜之化學溶液亦可作為鍍覆製程之電解液。於多種實施方式中,電解液可以是酸性電解液、鹼性電解液或中性電解液。在某些其他實施方式中,利用PVD製程或CVD製程沈積鈷主體層114,且其可和第一鈷襯墊108及鈷氮化物襯墊510在相同位置下進行。對於此種方法,繪示於鈷晶種襯墊112及鈷主體層114之間的相同或不同之邊界線可不存在。
圖8繪示某些實施方式中,對應於動作224之剖面圖800。
如剖面圖800,在以鈷主體層114填充開孔的剩餘空間之後,進行退火製程。退火製程使得第一鈷襯墊108和下方半導體結構104反應,以在第一鈷襯墊108及下方半導體結構104間之介面形成矽化物膜116。於某些實施方式中,第一鈷襯墊108的下方側邊部分會因為反應消耗而變薄(亦可見於圖1A);而於某些實施方式中;會形成和鈷氮化物襯墊510鄰接的矽化物膜116(亦可見於圖1B)。於某些實施方式中,在退火後進行平坦化製程。平坦化製程移除第一鈷襯墊108、鈷氮化物襯墊510與鈷主體層114之多餘部分,以形成一平面的表面。因此,第一鈷襯墊108、鈷氮化物襯墊510與鈷主體層114可具有一平面的上表面,其和介電層106之上表面齊平,如圖1A及圖1B所示。於某些實施方式中,平坦化製程可包括化學機械研磨(CMP)製程。於其他實施方式中,平坦化製程可包含其他蝕刻製程。
圖9繪示根據某些實施方式,用以沈積對應於圖4-6之互連的製程系統。於某些實施方式中,第一鈷襯墊108、鈷氮化物襯墊510及鈷晶種襯墊112係於原位形成,如圖9所示。對應於圖4,鈷前驅物沈積於半導體結構104之表面上。於某些實施方式中,鈷前驅物可包含六碳基二鈷叔丁基乙炔(CCTBA)。鈷前驅物經電漿處理。於某些實施方式中,處理電漿含氫。前驅物沈積與電漿處理可重複數個循環(如,2-3個循環)以得到所欲之第一鈷襯墊108厚度。同樣在相同的真空腔室中,且仍然在連續的真空下,對應於圖5,央阻障前驅物沈積於第一鈷襯墊108之表面上。於某些實施方式中,阻障前驅物可包含六碳基二鈷叔丁基乙炔(CCTBA)或三碳基亞硝醯鈷(Co(CO)3NO3NO)。阻障前驅物經電漿處理。於某些實施方式中,處理電漿包含氫、氮或氨。前驅物沈積與電漿處理可重複數個循環
(如,5-6個循環)以得到所欲之鈷氮化物襯墊510厚度。仍然在相同的真空腔室中,且仍然在連續的真空下,對應於圖6,將晶種層前驅物沈積於鈷氮化物襯墊510之表面上。於某些實施方式中,晶種層前驅物可包含六碳基二鈷叔丁基乙炔(CCTBA)。阻障前驅物經電漿處理。於某些實施方式中,處理電漿含氫。前驅物沈積與電漿處理可重複數個循環(如,8-9個循環)以達到所欲之鈷晶種襯墊112厚度。
因此,本揭露係關於用以形成互連層(特別是有矽化物膜之MEOL互連)之最佳化技術,其可減少空洞並提升可靠度。可在原位利用低溫化學氣相沈積(CVD)製程,再進行矽化之退火製程,以形成第一鈷襯墊(作為金屬矽化物襯墊)、鈷氮化物襯墊(作為阻障襯墊)和鈷晶種襯墊。因此,可達到較佳的填充結果。
上文揭示數個實施方式之特徵,而本發明所述技術領域中具有通常知識者能夠更佳地理解本揭露之態樣。本發明所述技術領域中具有通常知識者當可理解,其可輕易地利用本揭露之內容作為基礎,來設計或修改其他製程與結構,以實現和此處所述之實施方式相同的目的和/或達到相同的優點。本發明所述技術領域中具有通常知識者亦應理解,這些均等的實施方式並未悖離本揭露之精神與範圍,且可對其進行各種更動、取代與替換,而不會悖離本揭露之精神與範圍。
200‧‧‧方法
202-224‧‧‧動作
Claims (9)
- 一種用以製備一積體電路元件之方法,其包括:形成一介電層於一基板上,其中該介電層包括設於該介電層內之一開孔;沿著該開孔之底部與側壁表面形成一第一鈷襯墊;於該第一鈷襯墊之裸露表面上形成一阻障襯墊;於該開孔中並於該阻障襯墊上形成一鈷主體層,以填充該開孔之一剩餘空間;以及在以該鈷主體層填充該開孔之該剩餘空間之後,進行一退火製程,其中該退火製程使得該第一鈷襯墊和一下方中段製程(MEOL)結構反應,以於該第一鈷襯墊與該下方MEOL結構間之一介面形成一矽化物膜。
- 如請求項1所述之方法,其中該第一鈷襯墊經形成與該介電層直接接觸。
- 如請求項1所述之方法,其中該第一鈷襯墊係利用一濺鍍沈積製程、一化學氣相沈積(CVD)或一物理氣相沈積(PVD)所形成。
- 如請求項1所述之方法,其中該第一鈷襯墊、該阻障襯墊及該鈷主體層係於一腔室中依序形成,且當形成該第一鈷襯墊、阻障襯墊及鈷主體層時,該腔室經連續地置於真空下。
- 如請求項1所述之方法,進一步包括:在填充該鈷主體層之前,於該阻障襯墊上形成一鈷晶種襯墊; 其中該鈷主體層係利用一鍍覆製程所填充。
- 如請求項5所述之方法,其中該鈷晶種襯墊及該阻障襯墊係形成於一腔室中,且當形成該鈷晶種襯墊及該阻障襯墊時,該腔室經連續地置於真空下。
- 如請求項1所述之方法,其中形成該第一鈷襯墊及該阻障襯墊包括:引入六碳基二鈷叔丁基乙炔(CCTBA)至一腔室內以作為一鈷前趨物;使該鈷前驅物暴露於包括氫之一電漿,以形成該第一鈷襯墊;於該腔室中引入六碳基二鈷叔丁基乙炔(CCTBA)至該第一鈷襯墊上以作為一阻障前趨物;以及使該阻障前驅物暴露於包括氫、氮或氨之一電漿,以形成一鈷氮化物襯墊。
- 一種用以製備一積體電路元件之方法,其包括:形成一中段製程(MEOL)結構於一基板上;形成一介電層於該基板上;形成延伸通過該介電層之一開孔,以使該MEOL結構之一上表面的至少一部分裸露;形成一第一鈷襯墊於該MEOL結構之該上表面的該裸露部分上並沿著該開孔之側壁向上延伸;形成一鈷氮化物襯墊於該第一鈷襯墊之裸露表面上;以一鈷主體層填充該開孔之一剩餘空間;以及於填充該鈷主體層之後,進行一退火製程以在該第一鈷襯墊和該MEOL結構之該上表面的該裸露部分間之一介面形成一矽化物 膜。
- 一種積體電路元件,其包括:一基板;一介電層,覆設於該基板上並有一開孔垂直地延伸通過該介電層;一中段製程(MEOL)結構,位於該基板內且於該開孔下方;一第一鈷襯墊,沿著該開孔之底部與側壁表面設置;一矽化物膜,位於該第一鈷襯墊與該MEOL結構間之一介面;一阻障襯墊,設於該開孔中並覆蓋該第一鈷襯墊;以及一鈷主體層,覆設於該阻障襯墊上並填充該開孔之一剩餘空間。
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Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10276397B2 (en) * | 2015-06-30 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | CVD metal seed layer |
WO2018094329A1 (en) * | 2016-11-20 | 2018-05-24 | Applied Materials, Inc. | Methods to selectively deposit corrosion-free metal contacts |
US10546785B2 (en) | 2017-03-09 | 2020-01-28 | International Business Machines Corporation | Method to recess cobalt for gate metal application |
US10304735B2 (en) | 2017-06-22 | 2019-05-28 | Globalfoundries Inc. | Mechanically stable cobalt contacts |
US10553481B2 (en) | 2017-08-31 | 2020-02-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vias for cobalt-based interconnects and methods of fabrication thereof |
KR102376508B1 (ko) | 2017-11-16 | 2022-03-18 | 삼성전자주식회사 | 집적회로 장치 및 그 제조 방법 |
US10340183B1 (en) * | 2018-01-02 | 2019-07-02 | Globalfoundries Inc. | Cobalt plated via integration scheme |
US10840324B2 (en) * | 2018-08-28 | 2020-11-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method for the same |
US11043558B2 (en) | 2018-10-31 | 2021-06-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source/drain metal contact and formation thereof |
US10832946B1 (en) | 2019-04-24 | 2020-11-10 | International Business Machines Corporation | Recessed interconnet line having a low-oxygen cap for facilitating a robust planarization process and protecting the interconnect line from downstream etch operations |
CN112397443B (zh) * | 2019-08-14 | 2023-07-04 | 中芯国际集成电路制造(深圳)有限公司 | 半导体结构及其形成方法 |
CN111211110A (zh) * | 2020-01-14 | 2020-05-29 | 中国科学院微电子研究所 | 一种电子器件及其制作方法、集成电路和电子设备 |
KR102659491B1 (ko) * | 2021-08-12 | 2024-04-23 | 한국과학기술연구원 | 배선 재료용 저저항 필름의 제조 방법 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070269974A1 (en) * | 2002-08-23 | 2007-11-22 | Park Hee-Sook | Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer |
US20140183738A1 (en) * | 2012-12-28 | 2014-07-03 | Christopher J. Jezewski | Cobalt based interconnects and methods of fabrication thereof |
CN104205302A (zh) * | 2012-03-28 | 2014-12-10 | 应用材料公司 | 实现无缝钴间隙填充的方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020019127A1 (en) * | 1997-02-14 | 2002-02-14 | Micron Technology, Inc. | Interconnect structure and method of making |
US6436819B1 (en) | 2000-02-01 | 2002-08-20 | Applied Materials, Inc. | Nitrogen treatment of a metal nitride/metal stack |
US8110489B2 (en) | 2001-07-25 | 2012-02-07 | Applied Materials, Inc. | Process for forming cobalt-containing materials |
US6521956B1 (en) * | 2002-01-04 | 2003-02-18 | Promos Technologies Inc. | Semiconductor device having contact of Si-Ge combined with cobalt silicide |
JP2004055803A (ja) * | 2002-07-19 | 2004-02-19 | Renesas Technology Corp | 半導体装置 |
US20070111519A1 (en) * | 2003-10-15 | 2007-05-17 | Applied Materials, Inc. | Integrated electroless deposition system |
US20070210448A1 (en) * | 2006-03-10 | 2007-09-13 | International Business Machines Corporation | Electroless cobalt-containing liner for middle-of-the-line (mol) applications |
KR100703984B1 (ko) * | 2006-03-22 | 2007-04-09 | 삼성전자주식회사 | 반도체 집적 회로 장치의 제조 방법 및 그 구조 |
US7846841B2 (en) | 2008-09-30 | 2010-12-07 | Tokyo Electron Limited | Method for forming cobalt nitride cap layers |
US8058728B2 (en) * | 2008-09-30 | 2011-11-15 | Tokyo Electron Limited | Diffusion barrier and adhesion layer for an interconnect structure |
US7727883B2 (en) * | 2008-09-30 | 2010-06-01 | Tokyo Electron Limited | Method of forming a diffusion barrier and adhesion layer for an interconnect structure |
KR101149043B1 (ko) * | 2009-10-30 | 2012-05-24 | 에스케이하이닉스 주식회사 | 매립형 비트라인을 구비하는 반도체 장치 및 그 제조방법 |
JP6360276B2 (ja) * | 2012-03-08 | 2018-07-18 | 東京エレクトロン株式会社 | 半導体装置、半導体装置の製造方法、半導体製造装置 |
US20130341794A1 (en) * | 2012-06-21 | 2013-12-26 | Applied Materials, Inc. | Ultra-thin copper seed layer for electroplating into small features |
CN103855023A (zh) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法及半导体器件 |
US9425092B2 (en) * | 2013-03-15 | 2016-08-23 | Applied Materials, Inc. | Methods for producing interconnects in semiconductor devices |
US20150270168A1 (en) * | 2014-03-19 | 2015-09-24 | International Business Machines Corporation | Semiconductor contact with diffusion-controlled in situ insulator formation |
-
2015
- 2015-07-14 US US14/798,996 patent/US9472502B1/en active Active
- 2015-11-25 TW TW104139103A patent/TWI595598B/zh active
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070269974A1 (en) * | 2002-08-23 | 2007-11-22 | Park Hee-Sook | Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer |
CN104205302A (zh) * | 2012-03-28 | 2014-12-10 | 应用材料公司 | 实现无缝钴间隙填充的方法 |
US20140183738A1 (en) * | 2012-12-28 | 2014-07-03 | Christopher J. Jezewski | Cobalt based interconnects and methods of fabrication thereof |
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