TWI540678B - 接觸插塞及其製作方法與半導體元件 - Google Patents
接觸插塞及其製作方法與半導體元件 Download PDFInfo
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- TWI540678B TWI540678B TW103136669A TW103136669A TWI540678B TW I540678 B TWI540678 B TW I540678B TW 103136669 A TW103136669 A TW 103136669A TW 103136669 A TW103136669 A TW 103136669A TW I540678 B TWI540678 B TW I540678B
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- Prior art keywords
- conductive
- diffusion barrier
- contact plug
- barrier layer
- core
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- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 47
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 40
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 11
- 238000005496 tempering Methods 0.000 claims description 11
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 7
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
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- 230000004913 activation Effects 0.000 description 3
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- 229910052751 metal Inorganic materials 0.000 description 3
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- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
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- 150000001875 compounds Chemical class 0.000 description 2
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- AEVRNKXPLOTCBW-UHFFFAOYSA-N carbon monoxide;cobalt;cyclopenta-1,3-diene Chemical compound [Co].[O+]#[C-].[O+]#[C-].C=1C=C[CH-]C=1 AEVRNKXPLOTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- ZSEHKBVRLFIMPB-UHFFFAOYSA-N cobalt;cyclopenta-1,3-diene Chemical compound [Co].C=1C=C[CH-]C=1 ZSEHKBVRLFIMPB-UHFFFAOYSA-N 0.000 description 1
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- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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Description
本申請案主張西元2014年4月30日申請之美國臨時申請案第61/986740號,名稱「低電阻之複合插塞及其製造方法與包含其之積體電路(Composite Plug with Low Resistance,Methods of Making Same,and Integrated Circuits Incorporating Same)」之優先權,在此併入此申請案以供參考。
本發明是有關於一種半導體元件製作技術,且特別是有關於一種接觸插塞及其製作方法。
半導體元件元件使用在各種電子應用中,例如個人電腦、行動電話、數位相機及其他電子設備。通常,一般的半導體元件包含具有主動元件之基材,這些主動元件例如為電晶體與電容器。這些主動元件最初彼此隔離,隨後在這些主動元件上方形成內連結構,以產生功能電路。這類的內連結構可包含數個接觸插塞,其可電性耦合至基材上之主動元件。
一般之接觸插塞可包含鎢(W),因鎢的低電阻率(約
5.4μΩ.cm)以及高可靠度。然而,隨著積體電路的尺寸持續縮減至先進節點應用中的更小次微米尺寸時,在減少接觸洞之尺寸下,降低接觸插塞之電阻的挑戰也漸增。亟需改進之結構及其製作方法。
本發明之一態樣就是在提供一種接觸插塞及其製作方法與半導體元件,其可維持低電阻率的情況下,縮減插塞結構之尺寸。
本發明之另一態樣是在提供一種接觸插塞及其製作方法與半導體元件,其接觸插塞具有高活化能與熔點,而可提供良好之抗電子遷移性(electro-migration,EM)與電氣性能。
本發明之又一態樣是在提供一種接觸插塞極其製作方法與半導體元件,其接觸插塞具有良好的附著性能。
根據本發明之上述目的,提出一種接觸插塞。此接觸插塞包含雙層結構以及擴散阻障層。雙層結構包含導電芯以及導電襯,其中導電襯位於導電芯之側壁與底面上,且導電襯包含鈷(Co)或釕(Ru)。擴散阻障層位於雙層結構之側壁與底面上。
依據本發明之一實施例,上述之接觸插塞更包含導電膜位於擴散阻障層之側壁上,其中擴散阻障層設於導電膜與雙層結構之間。
依據本發明之另一實施例,上述之導電膜包含鈦、鈷、鎳或鎢。
依據本發明之又一實施例,上述之擴散阻障層包含鉭或氮化鉭。
依據本發明之再一實施例,上述之導電芯包含鎢。
依據本發明之再一實施例,上述之導電襯包含釕,且導電芯包含鈷。
依據本發明之再一實施例,上述之導電襯包含鈷,且導電芯包含釕。
根據本發明之上述目的,另提出一種半導體元件。此半導體元件包含介電層、接觸插塞以及矽化區。接觸插塞延伸穿過介電層。接觸插塞包含導電芯、導電襯以及擴散阻障層。導電襯位於導電芯之數個側壁與底面上,其中導電襯包含鈷或釕。擴散阻障層位於導電襯之數個側壁與底面上,其中導電襯設於擴散阻障層與導電芯之間。矽化區位於介電層下方,其中接觸插塞接觸矽化區。
依據本發明之一實施例,上述之接觸插塞更包含導電膜設於擴散阻障層之數個側壁上,其中導電膜設於擴散阻障層與介電層之間。
依據本發明之另一實施例,上述之導電膜包含鈦、鈷、鎳或鎢。
依據本發明之又一實施例,上述之矽化區包含矽與導電膜之導電材料的結合。
依據本發明之再一實施例,上述之導電芯包含鎢、釕或鈷,其中導電芯與導電襯包含不同導電材料。
依據本發明之再一實施例,上述之擴散阻障層包含
鉭或氮化鉭。
根據本發明之上述目的,又提出一種接觸插塞之製作方法。在此方法中,形成介電層於基材上。圖案化開口於介電層中以暴露出基材。形成擴散阻障層於開口中。形成導電襯於擴散阻障層之數個側壁與底面上,其中導電襯包含鈷或釕。形成導電芯於開口中,其中導電芯與導電襯包含不同之導電材料,其中導電襯設於導電芯與擴散阻障層之間。
依據本發明之一實施例,上述形成擴散阻障層之步驟包含形成擴散阻障層包含鉭或氮化鉭。
依據本發明之另一實施例,於形成擴散阻障層之步驟前,上述之方法更包含形成導電膜於開口之底面上,其中導電膜接觸基材。
依據本發明之又一實施例,於形成導電芯之步驟後,上述之方法更包含形成矽化區於基材之上部中。
依據本發明之再一實施例,上述形成矽化區之步驟包含回火製程,其中此回火製程將至少一部分之導電膜擴散至基材之上部中。
依據本發明之再一實施例,上述形成導電芯之步驟包含形成導電芯包含鎢、鈷或釕。
依據本發明之再一實施例,於形成導電芯之步驟後,上述之方法更包含暴露出介電層之頂面。
100‧‧‧晶粒
102‧‧‧基材
104‧‧‧矽化區
106‧‧‧導電膜
108‧‧‧擴散阻障層
110‧‧‧雙層結構
110a‧‧‧導電芯
110b‧‧‧導電襯
112‧‧‧介電層
114‧‧‧光阻
116‧‧‧開口
120‧‧‧接觸插塞
200‧‧‧製程流程
202‧‧‧步驟
204‧‧‧步驟
206‧‧‧步驟
208‧‧‧步驟
210‧‧‧步驟
212‧‧‧步驟
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
T4‧‧‧厚度
從以下結合所附圖式所做的詳細描述,可對本揭露之態樣有更佳的了解。需注意的是,根據業界的標準實務,各特徵並未依比例繪示。事實上,為了使討論更為清楚,各特徵的尺寸都可任意地增加或減少。
第1圖係繪示依照一些實施例之一種接觸插塞的剖面圖。
第2圖至第9圖係繪示依照一些實施例之一種製作接觸插塞之各個中間步驟的剖面圖。
第10圖係繪示依照一些實施例之一種製作接觸插塞之製程流程。
以下的揭露提供了許多不同實施例或例子,以實施所提供之標的之不同特徵。以下所描述之構件與安排的特定例子係用以簡化本揭露。當然這些僅為例子,並非用以做為限制。舉例而言,於描述中,第一特徵形成於第二特徵上方或上,可能包含第一特徵與第二特徵以直接接觸的方式形成的實施例,亦可能包含額外特徵可能形成在第一特徵與第二特徵之間的實施例,如此第一特徵與第二特徵可能不會直接接觸。此外,本揭露可能會在各例子中重複參考數字及/或文字。這樣的重複係基於簡化與清楚之目的,以其本身而言並非用以指定所討論之各實施例及/或配置之間的關係。
另外,在此說明中可能會使用空間相對用語,例如「向下(beneath)」、「下方(below)」、「較低(lower)」、「上方
(above)」、「較高(upper)」等等,以方便說明如圖式所繪示之一元件或一特徵與另一(另一些)元件或特徵之關係。除了在圖中所繪示之方向外,這些空間相對用詞意欲含括元件在使用或操作中的不同方位。設備可能以不同方式定位(旋轉90度或在其他方位上),因此可利用同樣的方式來解釋在此所使用之空間相對描述符號。
在具體提出圖例實施例前,先概括性地提出本揭露之態樣。概括而言,在此所描述之實施例提供一種複合接觸插塞。舉例而言,此複合接觸插塞可包含至少一雙層結構,此雙層結構具有鈷(Co)或釕(Ru)之導電襯位於鎢(W)、釕或鈷之導電芯的數個側壁或底面上。已經觀察到,可在仍舊維持低電阻率的情況下,縮減此一複合插塞結構之尺寸(例如,供先進節點應用)。一些實施例之另一有利特徵為良好的附著性能。使用擴散阻障層[例如包含鉭(Ta)或氮化鉭(TaN)]之實施例更顯現出低電阻與良好之附著性。一些實施例之另一有利特徵為雙層插塞顯現出高活化能與熔點,而可提供良好之抗電子遷移性(electro-migration,EM)與電氣性能。此外,藉由控制雙層結構中各層之側壁角度及/或厚度,可依據元件設計來微調接觸插塞之應力特性。
如將以圖示實施例所做的更詳細說明,在此所描述之一般實施例可提供包含低電阻、高活性能、高熔點、可調應力、以及雙層結構與擴散阻障層間的良好附著性中的一或多個有利特徵。
現請參照第1圖,其提供一複合接觸插塞120例子
之剖面圖。接觸插塞120電性接觸一下方結構之矽化(silicide)區104,例如矽化之源極/汲極區或矽化之閘極電極。在圖示之實施例中,矽化區104為透過回火導電膜106而形成之自我對準矽化物(self-aligned silicide,salicide)。導電膜106可在回火前設在接觸插塞120之數個側壁與底面上,且於回火後,部分之導電膜106可留在接觸插塞120之數個側壁上。留在接觸插塞120之側壁上的導電膜106可能是因為導電膜106與介電層112之材料之間具有較低之反應性。此外,在一些實施例中,甚至於回火後,一些導電膜106可留在接觸插塞120之底面。在一些實施例中,導電膜106可為鈷、鎢、鈦(Ti)、鎳(Ni)、與類似之導電襯,而可用以形成包含矽化鈦(TiSix)、矽化鎳(NiSix)、矽化鎢(WSix)、矽化鈷(CoSix)等等之矽化區104。舉例而言,下方之矽化結構(例如基材102)可包含矽(Si)、矽鍺(SiGe)、磷化矽(SiP)、碳化矽(SiC)、及其組合、與類似物。在其他考量的實施例中,下方結構亦可為金屬或其他導體。
如第1圖之進一步圖示,接觸插塞120包含擴散阻障層108位於接觸插塞120之側壁與底面上。擴散阻障層108可設於導電膜106之頂上。舉例而言,導電膜106可設於擴散阻障層108與基材102/矽化區104之間。在許多實施例中,擴散阻障層108可包含相對低電阻率之材料,例如鉭或氮化鉭,且擴散阻障層108亦可充當接觸插塞120之黏著層。
接觸插塞120更包含雙層結構110。擴散阻障層108
設於此雙層結構110之數個側壁與底面上。在許多實施例中,擴散阻障層108可降低或防止雙層結構110之導電材料擴散至周邊的元件特徵中(例如介電層112)。圖示之雙層結構110包含導電芯110a、以及設於導電芯110a之數個側壁與底面上的導電襯110b。舉例而言,導電襯110b可包含鈷或釕,導電芯110a可包含鎢、鈷或釕。然而,導電芯110a與導電襯110b之導電材料可包含不同材料。例如,許多實施例可包含雙層結構110,而此雙層結構110具有鈷或釕導電襯110b與鎢導電芯110a、鈷導電襯110b與釕導電芯110a、或釕導電襯110b與鈷導電芯110a。
已經觀察到,上述之導電材料的組合適合雙層結構110,因其具有類似之電阻率特性之故。舉例而言,鈷具有62.4nΩ.m之電阻率,鎢具有56.0nΩ.m之電阻率,而釕具有71.1nΩ.m之電阻率。鈷或釕在導電襯110b的應用提供良好的附著性(例如,導電襯110b可充當黏著層),並降低導電芯110a之材料(例如,在一些實施例中的鎢)擴散至周遭的元件層中。因此,可有效地利用具有低電阻率優勢之鉭或氮化鉭來作為第二擴散阻障層,以降低雙層結構110之材料的擴散。
此外,在一些實施例中,擴散阻障層108具有約5Å至約100Å之厚度T1。導電襯110b具有沿著接觸插塞120之底部的厚度T2,以及沿著接觸插塞120之側壁的厚度T3。在一些實施例中,厚度T2可為約100Å至約2000Å,厚度T3可為約10Å至約200Å。舉例而言,如圖1所示,
導電襯110b在導電芯110a之每個側壁上的部分較導電襯110b在導電芯110a之底面上的部分薄。導電芯110a具有從約100Å至約2000Å的厚度T4(例如,從上表面量到下表面)。在例示之實施例中,接觸插塞120之總高(從上表面量到下表面,或第1圖之厚度T1加厚度T2加厚度T4)為約500Å至約2000Å。導電芯110a與導電襯110b之厚度均可大於擴散阻障層108之厚度(例如,厚度T4與T2可均大於厚度T1)。在許多實施例中,可挑選複合接觸插塞120中之各層的側壁角度及/或厚度T1、T2、T3及/或T4,以根據元件設計而提供所需之應力特性。舉例而言,已經觀察到,矽化區104之電子電洞及/或電流遷移率會根據接觸插塞120之應力特性而受到影響,且可透過選取接觸插塞120中各層(例如,擴散阻障層108、導電襯110b及/或導電芯110a)之適當側壁角度及/或相對厚度,來對此應力特性進行微調。
在此所揭露之所有尺寸僅係用以舉例,而非限制。可考量的是,熟習此項技藝者一旦由本揭露所告知後,其他應用這些尺寸以及其他尺寸之層與特徵的結構與方法對這些熟習此項技藝者而言是顯而易知的,且這類其他結構、方法與尺寸在本發明之考量範圍內。
第2圖至第9圖繪示依照一些實施例之製作接觸插塞之各個中間階段的剖面圖。第2圖係繪示晶粒100,此晶粒100具有基材102、以及設於基材102上方之介電層112。在後續之製程步驟中,複合接觸插塞120可形成在介電層
112中,以電性連接至下方之基材102。舉例而言,基材102可為一主動元件(例如電晶體)之源極/汲極區或閘極。基材102可例如為塊狀矽(bulk silicon)基材、摻雜或未摻雜、或絕緣底半導體(SOI)基材之主動層。一般而言,絕緣底半導體基材包含一層半導體材料,例如矽,形成在一絕緣層上。此絕緣層可例如包含埋層氧化層(BOX)或氧化矽層。此絕緣層提供在基材上,例如矽或玻璃基材。替代的,基材102可包含另一元素半導體,例如鍺;化合物半導體,包含碳化矽、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)、及/或銻化銦磷化銦(InSb);合金半導體,包含矽鍺、磷化鎵砷(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)、及/或磷化鎵銦砷(GaInAsP);或上述材料之組合。亦可使用其他基材,例如多層或梯度基材(gradient substrate)。此外,基材102亦可包含多晶矽、金屬或其他導電材料。
介電層112設於基材102之上方。在許多實施例中,介電層112可為第一內層介電(ILD)/內金屬介電(IMD)層。介電層112可例如由介電值低於約4.0或甚至約2.8之低介電常數介電材料所形成。在一些實施例中,介電層112可包含利用任何適合方法,例如旋轉、化學氣相沉積(CVD)與電漿輔助化學氣相沉積(PECVD),形成之磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟矽玻璃(FSG)、摻碳氧化矽(SiOxCy)、旋塗式玻璃(Spin-On-Glass)、旋塗式聚合物(Spin-On-Polymer)、矽碳材料、及其化合物、及其複合物、
及其組合或其類似物。介電層112亦可包含複層,例如多個隔離層、多個黏著層、多個緩衝層及其類似層。
如第2圖所進一步圖示,設置圖案化光阻114於介電層112之上方。光阻114可利用旋塗(spin-on)製程、層壓(lamination)製程等等,而在介電層112上方沉積成一覆蓋層。接下來,可利用光罩(未繪示)曝光部分之光阻114。接著,根據負型或正型光阻的使用,移除光阻114之曝光或未曝光之部分,而形成開口116延伸穿過光阻114。
如第3圖所示,可利用光阻114作為圖案化罩幕,來圖案化介電層112。舉例而言,可利用乾及/或濕蝕刻技術,來蝕刻開口116所暴露出之介電層112的部分。蝕刻將開口116延伸穿過介電層112。開口116可暴露下方基材102之一區域,例如源極/汲極區、閘極電極與類似區域。隨後,例如在灰化及/或濕式剝除製程中,移除光阻114。雖然僅顯示出一個開口116,但可根據元件設計,而在介電層112中圖案化出任何數量之開口(例如,使用微影與蝕刻的組合)。
在一些實施例中,可在圖案化製程中使用其他層。舉例而言,可在光阻114形成前,形成一或多個硬罩幕(未繪示)於介電層112之頂上,在這樣的實施例中,來自光阻114之圖案先施加在一或多個硬罩幕上,而圖案化之硬罩幕可應用來圖案化介電層112。一般而言,在許多實施例中,一或多個硬罩幕層是有益的,在這些實施例中,蝕刻製程需要除了光阻材料所提供之遮罩外的遮罩。在後續之圖案
化介電層112的蝕刻製程期間,亦將蝕刻圖案化之光阻罩幕,然而光阻材料之蝕刻率可能沒有像介電層112之蝕刻率那麼高。若蝕刻製程為在介電層112之蝕刻製程完成前,可能已耗盡圖案化之光阻罩幕,那麼可能要使用額外之硬罩幕。選擇一或多個硬罩幕層之材料,而使硬罩幕層顯現出較下方之材料,例如介電層112之材料,低之蝕刻率。
第4圖繪示導電膜106形成在開口116之多個側壁與底面上。導電膜106更可設於介電層112上。可利用任何適合的製程,例如物理氣相沉積(PVD)製程、化學氣相沉積(CVD)製程、原子層沉積(ALD)製程及類似製程,來沉積導電膜106。導電膜106可包含具有合適厚度之適合導電材料,以供在後續製程步驟中形成矽化區於基材102之上部上(例如矽化區104)。舉例而言,在一些實施例中,導電膜160可包含厚度約30Å至約250Å之鎢、鈷、鈦、鎳與類似材料。在一些實施例中,可進一步選取導電膜106之材料,以縮減製作接觸插塞120所需之製程反應室的總數。舉例而言,當導電膜106與導電芯110a均包含鎢時,可重複利用相同之製程反應室來製作接觸插塞120的不同部分。
接下來,在第5圖中,形成擴散阻障層108於導電膜106之頂上。擴散阻障層108可設於開口116之多個側壁與底面上。擴散阻障層108可包含低電阻率材料,例如鉭或氮化鉭,且擴散阻障層108可具有約5Å至約100Å之厚度T1。可利用任何適合的製程,例如物理氣相沉積製程、化學氣相沉積製程、原子層沉積製程及類似製程,來沉積
擴散阻障層108。舉例而言,可利用原子層沉積製程,在適當之製程條件下(例如,在製程溫度約100℃至約350℃下),使用五(二甲氨基)鉭(pentakis dimethylamido tantalum,PDMAT)作為前驅化學物。
第6圖與第7圖係繪示依照一些實施例之一種接觸插塞120中之雙層結構110的製作。首先請參照第6圖,形成雙層結構110之導電襯110b於擴散阻障層108之頂上。導電襯110b可設於開口116之多個側壁與底面上。在一些實施例中,導電襯110b可包含鈷或釕。導電襯110b可包含在開口116之底面上的厚度T2、以及在開口116之側壁上的厚度T3。在一些實施例中,厚度T2可為約100Å至約2000Å,且厚度T3可為約10Å至約200Å。可利用任何適合的製程,例如物理氣相沉積製程、化學氣相沉積製程、原子層沉積製程及類似製程,來沉積導電襯110b。所採用之具體製程條件可依據導電襯110b之材料而變。舉例而言,當導電襯110b包含鈷時,可採用利用C12H10O6Co2(例如,在製程溫度約90℃至約350℃下)、雙環戊二烯鈷(biscyclopentadienyl Co)(例如,在製程溫度約100℃至約500℃下)、或二羰基環戊二烯鈷(cyclopentadienyl dicarbonyl cobalt)(例如,在製程溫度約100℃至約500℃下)作為前驅化學物之原子層沉積或化學氣相沉積製程。在另一個例子中,當導電襯110b包含釕,可利用原子層沉積或化學氣相沉積製程,在適當之製程條件下(例如,在製程溫度約100℃至約500℃下),使用三(2-乙醯丙酮)釕或三(4-
乙醯丙酮)釕、十二羰基三釕(Ru3CO12)、或釕二苯環[Ru(C5H5)2]作為前驅化學物。
接下來,在第7圖中,可設置雙層結構110之導電芯110a,以填充開口116之剩餘部分。導電芯110a更可溢出開口116,而覆蓋導電襯110b之頂面。在一些實施例中,導電芯110a可包含鈷、釕或鎢。導電襯110b與導電芯110a之材料可不同。舉例而言,許多實施例之雙層結構110可包含鈷導電襯110b與鎢導電芯110a、釕導電襯110b與鎢導電芯110a、釕導電襯110b與鈷導電芯110a、或鈷導電襯110b與釕導電芯110a。可利用任何適合的製程,例如物理氣相沉積製程、化學氣相沉積製程、原子層沉積製程及類似製程,來沉積導電芯110a。已觀察到,上述之導電材料的組合適合雙層結構110,因鈷、釕與鎢具有類似之電阻率特性。此外,鈷或釕使用在導電襯110b提供良好之附著性(例如,導電襯110b可充當黏著層),並降低導電芯110a之材料的擴散(例如,導電襯110b亦可充當擴散阻障層)。因此,可採用低電阻率材料(例如鉭或氮化鉭)來製作擴散阻障層108,其可進一步降低雙層結構110之材料擴散至周遭之元件層中。因此,雙層結構110形成在介電層112中。
接下來請參照第8圖,形成矽化區104於基材102之上部(例如,基材102與導電膜106實際接觸的部分)。可藉由將導電膜106之導電材料擴散至基材102之上部的方式形成矽化區104。舉例而言,可在溫度在約100℃至約900℃,氣壓約770Torr至約850Torr下,以氬氣(Ar)或氮氣(N2)
作為製程氣體,進行回火製程。回火後,導電膜106之底部可擴散至基材102中,而導電膜106在接觸插塞120之側壁上的部分可存留。在一些實施例中,一些位在接觸插塞120之底面的導電膜106可存留(例如,導電膜106之底部可能不會完全擴散到基材102之上部)。替代地,基材102之材料(例如矽)可能擴散至導電膜106中而形成矽化區104。導電膜106之導電材料的擴散可增加基材102之受作用區(affected area)的導電性,因而形成更適合接觸插塞120電性連接之接觸區(即矽化區104)。
隨後,可進行平坦化製程[例如化學機械製程(CMP)或研磨],以從介電層112之頂面移除過多之材料(例如導電膜106、擴散阻障層108與雙層結構110)。亦可採用其他的回蝕刻(etch back)技術。複合接觸插塞120因而形成於介電層112中。複合接觸插塞120可包含導電膜106、擴散阻障層108與雙層結構110。雙層結構110包含導電芯110a(例如包含鈷、釕或鎢)、以及位於導電芯110a之多個側壁與底面上之導電襯110b(例如包含鈷或釕)。
第10圖係繪示依照一些實施例之一種製作複合接觸插塞之製程流程200。始於步驟202,利用例如微影與蝕刻,圖案化開口於介電層(例如介電層112)中。開口可暴露出供電性連接之下方基材區(例如基材102),例如源極/汲極區或閘極電極。接下來,在步驟204中,可沉積導電膜(例如包含鈷、鎢、鈦、鎳與類似材料之導電膜106)於開口之側壁與底面上。導電膜可應用在後續製程步驟中(例如步驟
210),以形成矽化區。因此,在一些實施例中,導電膜可接觸下方基材之暴露部分。
在步驟206中,可形成擴散阻障層(例如擴散阻障層108)於位在開口之側壁與底面上之導電膜的頂上。舉例而言,導電膜設於擴散阻障層與下方基材之間。因此,在後續製程步驟中(例如步驟210),擴散阻障層可不妨礙矽化區形成在下方基材之上部中。擴散阻障層可包含低電阻率材料,例如鉭或氮化鉭,且在一些實施例中,擴散阻障層更可具有良好之附著特性且可用來作為黏著層。在步驟208中,形成雙層結構(例如雙層結構110)來填充開口之剩餘部分。擴散阻障層可設於雙層結構之多個側壁與底面上,以防止或減少雙層結構之材料擴散至周遭之元件層中(例如介電層)。
形成雙層結構之步驟可包含先沉積鈷或釕構成之導電襯(例如導電襯110b)在位於開口之側壁與底面上之擴散阻障層之頂上。接下來,沉積鈷、釕或鎢構成之導電芯(例如導電芯110a),以填充開口之剩餘部分。導電芯與導電襯可包含具有類似電阻率性質之不同材料。許多實施例可包含鈷或釕導電襯與鎢導電芯、鈷導電襯與釕導電芯、或釕導電襯與鈷導電芯。導電襯可減少擴散並改善附著性,而有利於擴散阻障層使用低電阻率材料。此外,可選擇擴散阻障層、導電襯及/或導電芯之側壁角度及/或相對尺寸(例如,厚度、高度等等),以達成接觸插塞所需之應力特性,其可根據元件設計而微調。
在開口中填充接觸插塞之各層後,形成矽化區(例如矽化區104)於下方基材之上部中。舉例而言,可進行回火製程,以將導電膜之材料擴散至下方基材中,來形成矽化區。接觸插塞可電性連接至矽化區。最後,在步驟212中,藉由利用合適之平坦化製程,例如化學機械製程、研磨製程或另外之回蝕刻技術,以從頂面移除過多材料的方式,來暴露出介電層之頂面。如此,可在介電層中形成電性連接下方基材之矽化區的複合接觸插塞(例如接觸插塞120)。在後續製程步驟中,可在介電層上方形成許多額外之內連線結構(例如具有導線及/或介層窗之金屬化層)。這類內連線結構將此接觸插塞與其他接觸插塞及/或主動元件電性連接,以形成功能電路。亦可形成額外之元件特徵,例如被動層、輸入/輸出結構與類似結構。
許多實施例提供複合接觸插塞。舉例而言,複合接觸插塞可包含雙層結構,且此雙層結構具有鈷或釕導電襯位於鎢、釕或鈷導電芯之多個側壁與底面上。導電襯與導電芯可包含具有類似電阻率特性的不同導電材料。更可設置包含低電阻率材料(例如鉭或氮化鉭)之擴散阻障層於複合接觸插塞之多個側壁與底面上。已經觀察到,可在仍舊維持低電阻率與良好附著性的情況下,縮減此一複合插塞結構之尺寸(例如,供先進節點應用)。一些實施例之另一有利特徵為雙層插塞顯現出高活化能與熔點,而可提供良好之抗電子遷移性與電氣性能。此外,藉由控制雙層結構中各層之側壁角度及/或厚度,可依據元件設計來微調接觸插
塞之應力特性。
依照一實施例,一種接觸插塞包含雙層結構、以及擴散阻障層位於雙層結構之側壁與底面上。雙層結構包含導電芯、以及導電襯位於導電芯之側壁與底面上。在一實施例之接觸插塞中,導電襯包含鈷或釕。
依照另一實施例,一種半導體元件包含介電層、以及接觸插塞延伸穿過介電層。接觸插塞包含導電芯、導電襯位於導電芯之數個側壁與底面上、以及擴散阻障層位於導電襯之數個側壁與底面上。導電襯包含鈷或釕,且導電襯設於擴散阻障層與導電芯之間。此半導體元件更包含矽化區位於介電層下方,其中接觸插塞接觸矽化區。
依照又一實施例,一種接觸插塞之製作方法包含形成介電層於基材上、以及圖案化開口於介電層中以暴露出基材。此方法更包含形成擴散阻障層於開口中、以及形成導電襯於擴散阻障層之數個側壁與底面上。導電襯包含鈷或釕。形成導電芯於開口中。導電芯與導電襯包含不同之導電材料,且導電襯設於導電芯與擴散阻障層之間。
上述已概述數個實施例的特徵,因此熟習此技藝者可更了解本揭露之態樣。熟悉此技藝者應了解到,其可輕易地利用本揭露做為基礎,來設計或潤飾其他製程與結構,以實現與在此所介紹之實施例相同之目的及/或達到相同的優點。熟悉此技藝者也應了解到,這類對等架構並未脫離本揭露之精神和範圍,且熟悉此技藝者可在不脫離本揭露之精神和範圍下,進行各種之更動、取代與潤飾。
100‧‧‧晶粒
102‧‧‧基材
104‧‧‧矽化區
106‧‧‧導電膜
108‧‧‧擴散阻障層
110‧‧‧雙層結構
110a‧‧‧導電芯
110b‧‧‧導電襯
112‧‧‧介電層
120‧‧‧接觸插塞
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
T4‧‧‧厚度
Claims (10)
- 一種接觸插塞,包含:一雙層結構,包含:一導電芯;以及一導電襯,位於該導電芯之一側壁與一底面上,其中該導電襯包含鈷或釕,且該導電襯在該導電芯之該側壁上之部分較該導電襯在該導電芯之該底面上之部分薄;以及一擴散阻障層,位於該雙層結構之一側壁與一底面上。
- 如請求項1所述之接觸插塞,更包含一導電膜位於該擴散阻障層之一側壁上,其中該擴散阻障層設於該導電膜與該雙層結構之間。
- 如請求項2所述之接觸插塞,其中該導電膜包含鈦、鈷、鎳或鎢。
- 如請求項1所述之接觸插塞,其中該導電芯包含鎢、鈷或釕,且該導電芯與該導電襯包含不同導電材料。
- 一種半導體元件,包含:一介電層;一接觸插塞,延伸穿過該介電層,其中該接觸插塞包含:一導電芯;一導電襯,位於該導電芯之複數個側壁與一底面上,其中該導電襯包含鈷或釕,其中該導電襯在該導電 芯之每一該些側壁上之部分較該導電襯在該導電芯之該底面上之部分薄;以及一擴散阻障層,位於該導電襯之複數個側壁與一底面上,其中該導電襯設於該擴散阻障層與該導電芯之間;以及一矽化區,位於該介電層下方,其中該接觸插塞接觸該矽化區。
- 如請求項5所述之半導體元件,其中該接觸插塞更包含一導電膜設於該擴散阻障層之複數個側壁上,其中該導電膜設於該擴散阻障層與該介電層之間。
- 如請求項5所述之半導體元件,其中該導電芯包含鎢、釕或鈷,其中該導電芯與該導電襯包含不同導電材料,且該擴散阻障層包含鉭或氮化鉭。
- 一種接觸插塞之製作方法,包含:形成一介電層於一基材上;圖案化一開口於該介電層中以暴露出該基材;形成一擴散阻障層於該開口中;形成一導電襯於該擴散阻障層之複數個側壁與一底面上,其中該導電襯包含鈷或釕;以及形成一導電芯於該開口中,其中該導電芯與該導電襯包含不同之導電材料,其中該導電襯設於該導電芯與該擴散阻障層之間,且該導電襯位於該導電芯之複數個側壁與一底面上,該導電襯在該導電芯之每一該些側壁上之部分較該導電 襯在該導電芯之該底面上之部分薄。
- 如請求項8所述之方法,於形成該擴散阻障層之步驟前,更包含形成一導電膜於該開口之一底面上,其中該導電膜接觸該基材。
- 請求項9所述之方法,於形成該導電芯之步驟後,更包含形成一矽化區於該基材之一上部中,其中形成該矽化區之步驟包含一回火製程,其中該回火製程將至少一部分之該導電膜擴散至該基材之該上部中。
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