JP6360276B2 - 半導体装置、半導体装置の製造方法、半導体製造装置 - Google Patents
半導体装置、半導体装置の製造方法、半導体製造装置 Download PDFInfo
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Description
図1は、実施形態に係る半導体装置100の構成図である。半導体装置100は、幅又は高さの少なくとも一方が15nm(ナノメートル)以下である配線102,104及び外径が15nm以下であるビア導体105を、Ni(ニッケル)又はCo(コバルト)を主成分とする金属又は合金で形成していることを特徴とする。実施例にて後述するように、15nm以下では、細線効果によりNi(ニッケル)又はCo(コバルト)よりも、Cu(銅)の方が抵抗率が高くなる。
図2A〜図2Cは、半導体装置100の製造工程図である。以下、図2A〜図2Cを参照して、半導体装置100の製造方法について説明する。なお、以下の説明では、既に、層間絶縁層103が形成されている状態から、半導体装置100の製造工程を説明する。
層間絶縁層103を選択的にエッチングし、配線104を埋め込むためのトレンチ103a及びビア導体105を埋め込むためのビアホール103bを形成する。
CVD(Chemical Vapor Deposition)法、PVD(Physical Vapor Deposition)法、ALD(Atomic Layer Deposition)法、電解めっき法、又は無電解めっき法、超臨界CO2成膜法、もしくは、これらの方法を組み合わせて、トレンチ103a及びビアホール103bを含む層間絶縁層103表面上にNi又はCoを主成分とするシード層S2及び金属層M2を形成する。
次に、CMP(Chemical Mechanical Polishing)法により、層間絶縁層103上に形成されたシード層S2及び金属層M2を研磨により除去し、トレンチ103aに埋め込まれた配線104及びビアホール103b内に埋め込まれたビア導体105を形成する。なお、CMP法により研磨されたウェハWは、スラリ等の残渣を取り除くために洗浄処理される。
図3は、半導体製造装置200の平面図である。以下、図3を参照して、半導体装置100を製造する半導体製造装置200の構成を説明する。
半導体製造装置200は、ローダモジュール210と、ロードロックチャンバ220A,220Bと、搬送チャンバ230と、複数の処理チャンバ240A〜240Dと、制御装置250とを備える。
ローダモジュール210は、複数のドアオープナ211A〜211Cと、搬送ロボット212と、アライメント室213とを備える。ドアオープナ211A〜211Cは、処理対象であるウェハWの収納容器C(例えば、FOUP(Front Opening Unified Pod)、SMIF(Standard Mechanical Inter Face)Pod等)のドアをOpen/Closeさせる。搬送ロボット212は、収納容器C、アライメント室213、ロードロックチャンバ220A,220Bとの間でウェハWを搬送する。
搬送チャンバ230は、ゲートバルブG1〜G6と、搬送ロボット231と、を備える。ゲートバルブG1,G2は、ロードロックチャンバ220A,220Bとの仕切弁である。ゲートバルブG3〜G6は、処理チャンバ240A〜240Dとの仕切弁である。搬送ロボット231は、ロードロックチャンバ220A,220B及び処理チャンバ240A〜240Dとの間でウェハWの受け渡しを行う。
次に、半導体製造装置200による半導体装置100の製造について説明する。以下、図2A、図2B及び図3を参照して、半導体製造装置200による半導体装置100の製造について説明する。なお、以下の説明では、半導体製造装置200に搬送される前のウェハW上には、半導体装置100が図2Aに示す状態まで製造されているものとする。
上記実施形態では、ダマシン(埋め込み)法により、半導体装置100(図1)を製造する工程を図2A〜図2Cを参照して説明した。この実施形態の変形例では、サブトラクティブ法により半導体装置100を製造する方法について説明する。
層間絶縁層101を選択的にエッチングし、ビアホール101bを形成する。
CVD法、PVD法、ALD法、電解めっき法、又は無電解めっき法、超臨界CO2成膜法、もしくは、これらの方法を組み合わせて、ビアホール101bを含む層間絶縁層101表面上にNi又はCo主成分とするシード層S2及び金属層M2を形成する。
次に、金属層M2上に所望のパターンにマスクHMを形成する。マスクHMの材料は、例えば、窒化ケイ素材(Si3N4)や、炭化ケイ素材(SiC)、TEOSなどの酸化ケイ素材(SiO2)である。
次に、ドライエッチングを行い、ビアホール101b内にビア導体105と、ビア導体105に接続された配線104とを形成する。
次に、層間絶縁層101及び配線104上に、層間絶縁層103を形成する。
次に、半導体製造装置200による半導体装置100の製造について説明する。以下、図3及び図4A,図4Bを参照して、半導体製造装置200による半導体装置100の製造について説明する。なお、以下の説明では、半導体製造装置200に搬送される前のウェハW上には、半導体装置100が図4Aに示す状態まで製造されているものとする。
以上、本発明の実施形態について説明したが、本発明は、上記実施形態に限定されるものではなく、各種の変形が可能であることは勿論である。図3を参照して説明した半導体製造装置200では、各処理チャンバ内の圧力が大気圧よりも低い真空装置を想定していたため、シード層S2を形成する処理チャンバ240BをPVDチャンバ又はALDチャンバとし、金属層M2を形成する処理チャンバ240CをCVDチャンバとしているが、この限りではない。
なお、NiとCoからなる合金を用いてもよく、その場合のNiとCoの含有比率は、0〜100%の間で適宜選択可能である。つまり、NixCo1−xとした場合、xのとり得る値は、0〜1である。x=0のときは、Niが0%でCoが100%となり、x=0.5のときは、NiもCoも50%となり、x=1のときは、Niが100%でCoが0%となる。
Cu、Co、Mo、W、Niのそれぞれについて、膜厚の異なる複数の金属膜を形成した後、各金属膜の膜厚及び抵抗を測定した。膜厚は、XRFを用いて測定した。
Cu、Co、Mo、W、Niのそれぞれについて、膜厚の異なる複数の金属膜を形成した後、還元雰囲気下において400℃、30分(間)のアニール処理を行った。なお、アニール処理は、水素(H2)ガスを3%含んだ窒素(N2)ガスを用いて還元雰囲気を形成した状態で行った。アニール処理後、各金属膜の膜厚及び抵抗を測定した。膜厚は、XRFを用いて測定した。
Cu、Co、Mo、Niのそれぞれについて、膜厚の異なる複数の金属膜を形成した後、各金属膜の膜厚及び抵抗を測定した。膜厚は、TEMを用いて測定した。
上記実施例1〜3の結果から、線幅又は高さの少なくとも一方が15nm以下の配線に使用する材料として、Cu、W、MoよりもNi又はCo(アニール処理有)の方が優れていることがわかった。今回の結果の理由としては、グレインサイズがCu、W、MoよりもNi、Coの方が大きかった可能性、グレインの配向性がCu、W、MoよりもNi、Coの方が揃っていた可能性、Ni、Coにおいては不動態被膜の形成により内部酸化が抑制された可能性が考えられる。今回の実験は、実際に配線を形成しておこなったものではなく、金属の薄膜を用いて実験したものであるが、薄膜で抵抗上昇する要因は、表面や界面の影響が薄膜化に伴って相対的に強くなり、電子の散乱が増加することであり、これは微細配線における抵抗上昇の要因と同じである。
Claims (14)
- 絶縁層及び配線層を備えた半導体装置であって、
前記配線層は、
配線の線幅又は高さの少なくとも一方が15nm以下であり、Ni又はCoからなる配線を有し、前記配線層の配線のうち線幅及び高さが15nmを超える配線は、Cuを主成分とする金属からなることを特徴とする半導体装置。 - 前記絶縁層を介して複数の前記配線層が積層され、
前記配線層の配線を接続するビア導体をさらに備え、
前記ビア導体は、直径が15nm以下であり、Ni又はCoからなることを特徴とする請求項1に記載の半導体装置。 - 前記Ni又は前記Coの平均グレインサイズが、15nm以上であることを特徴とする請求項1又は請求項2に記載の半導体装置。
- 絶縁層及び配線層を備えた半導体装置の製造方法であって、
前記絶縁層の表面に、線幅又は高さの少なくとも一方が15nm以下であり、Ni又はCoからなる配線と、線幅及び高さが15nmを超えCuを主成分とする金属からなる配線と、を有する前記配線層を形成する工程を有することを特徴とする半導体装置の製造方法。 - 前記配線層は、
非酸化雰囲気中で形成することを特徴とする請求項4に記載の半導体装置の製造方法。 - 前記非酸化雰囲気は、
真空雰囲気又は還元雰囲気であることを特徴とする請求項5に記載の半導体装置の製造方法。 - 前記配線層を熱処理する工程をさらに有することを特徴とする請求項4乃至請求項6のいずれかに記載の半導体装置の製造方法。
- 前記熱処理は、RTP処理、レーザアニール処理、又はLEDによる加熱処理であることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記熱処理は、枚葉式のアニール装置で行うことを特徴とする請求項7又は請求項8に記載の半導体装置の製造方法。
- 前記配線層を形成する工程の前に、
加熱により前記絶縁層のデガス処理を行う工程をさらに有することを特徴とする請求項4乃至請求項9のいずれかに記載の半導体装置の製造方法。 - 前記絶縁層を選択的にエッチングして凹部を形成する工程と、
前記凹部を含む前記絶縁層の表面に、Ni又はCoからなる金属層を形成する工程と、
前記凹部を除く前記絶縁層の表面に形成された前記金属層を除去して、前記配線を形成する工程と、
を有することを特徴とする請求項4乃至請求項10のいずれかに記載の半導体装置の製造方法。 - 前記絶縁層の表面に、Ni又はCoからなる金属層を形成する工程と、
前記金属層を選択的にエッチングして前記配線を形成する工程と、
を有することを特徴とする請求項4乃至請求項10のいずれかに記載の半導体装置の製造方法。 - 前記金属層を形成する工程は、
前記絶縁層の表面に、Ni又はCoからなるシード層を形成する工程と、
前記シード層上にNi又はCoからなる前記金属層を成長させる工程と、
を有することを特徴とする請求項11又は請求項12に記載の半導体装置の製造方法。 - 前記配線は、CVD法、PVD法、ALD法、電解めっき法、又は無電解めっき法、超臨界CO2成膜法、もしくはこれらの組み合わせにより形成されることを特徴とする請求項4乃至請求項13のいずれかに記載の半導体装置の製造方法。
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