TW201541557A - 導電內連線層及填充導電內連線層之間隙之方法 - Google Patents

導電內連線層及填充導電內連線層之間隙之方法 Download PDF

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TW201541557A
TW201541557A TW103146479A TW103146479A TW201541557A TW 201541557 A TW201541557 A TW 201541557A TW 103146479 A TW103146479 A TW 103146479A TW 103146479 A TW103146479 A TW 103146479A TW 201541557 A TW201541557 A TW 201541557A
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layer
opening
conductive
barrier layer
conductive interconnect
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TWI548032B (zh
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Chao-Hsien Peng
Chi-Liang Kuo
Ming-Han Lee
Hsiang-Huan Lee
Shau-Lin Shue
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Taiwan Semiconductor Mfg Co Ltd
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Abstract

本揭露係關於一種以預填入步驟形成之金屬內連線層以及其相關之製程。此預填入步驟係用以減少空隙。在一些實施例中，此金屬內連線層包括設於基底上介電層，以及向下延伸穿過介電層之開口，此開口包括設於水平面上之上部以及設於水平面下之下部。此金屬內連線層更包括填入開口之下部之第一導電層，以及一上阻障層，設於第一導電層上且覆蓋開口之上部的底部以及側壁之表面。此金屬內連線層更包括設於上阻障層上且填入開口之上部的第二導電層。

Description

在後段製程互連層上的導孔預填充
本揭露係有關於半導體技術，且特別係有關於導電內連線層及其相關之製造方法。
在積體電路的製程中，多個裝置係形成於晶圓上，且藉由多層導電內連線層彼此連接。這些導電內連線層之形成步驟為先形成間隙，例如介電層中的溝槽或是介層窗，接著於這些間隙中填入導電材料。
此導電材料通常係藉由電化學電鍍步驟(electrochemical plating process)形成於間隙中。在此步驟中，阻障層係先形成於介電層之間隙中，接著一晶種層係形成於此阻障層上。接著，間隙中剩餘之空間係以導電材料填充。接著，進行一平坦化步驟以移除多餘之導電材料。
下文及其相應之圖式係針對本揭露作詳細說明。應注意的是，圖式中之元件並非以其實際比例繪製。實際上，為了明確描述本揭露，圖式中的元件尺寸可能會被放大或縮小。
第1A圖係本揭露某些實施例之具有一或多層導電內連線層之基底的剖面圖。
第1B圖係本揭露某些實施例之具有一或多層導電內連線層之基底的剖面圖。
第2圖係本揭露某些實施例之填充導電內連線層之間隙之方法的流程圖。
第3圖係本揭露某些實施例之填充導電內連線層之間隙之方法的流程圖。
第4A-4E圖係本揭露實施例之導電內連線層在填充此導電內連線層之間隙之方法中的各階段的剖面圖。
第5圖係本揭露某些其它實施例之填充導電內連線層之間隙之方法的流程圖。
第6A-6E圖係本揭露某些其它實施例之導電內連線層在填充此導電內連線層之間隙之方法中的各階段的剖面圖。
以下針對本揭露之各實施例作詳細說明。應了解的是，以下之敘述提供許多不同的實施例或例子，用以實施本揭露之不同樣態。以下所述特定的元件及排列方式儘為簡單描述本揭露。當然，這些僅用以舉例而非本揭露之限定。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸之情形。或者，亦可能間隔有一或更多其它材料層之情形，在此情形中，第一材料層與第二材料層之間可能不直接接觸。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本揭露，不代表所討論之不同實施例及/或結構之間具有任何關連性。
此外，實施例中可能使用相對性的用語，例如「較 低」或「底部」及「較高」或「頂部」，以描述圖示的一個元件對於另一元件的相對關係。能理解的是，如果將圖示的裝置翻轉使其上下顛倒，則所敘述在「較低」側的元件將會成為在「較高」側的元件。或者，當裝置被旋轉至其它角度(例如旋轉90度或其它角度)，上述空間上相對性之用語亦可相對應之更動。
隨著半導體之尺寸不斷地縮小，後段製程之金屬 內連線結構之元件尺寸亦隨之縮小。而隨著後段製程之金屬內連線結構之元件尺寸縮小，間隙之徑長比則隨之增加。此間隙例如可為在形成金屬內連線結構之步驟中被填有導電層之溝槽或介層窗。在雙鑲崁金屬化步驟中，具有較大之徑長比的介層窗或溝槽會使得金屬難以藉由電化學電鍍步驟填入，導致在介層窗或溝槽中形成空隙(void)，或者在介層窗或溝槽中某些地方未形成導電材料。由於上述空隙中不具有導電材料，其會導致較差的連結與不佳的耐久性。
因此，本揭露揭示一使用介層窗預填充步驟(via pre-fill process)來填充間隙(gap)以減少雙鑲嵌金屬層中的空隙(void)之方法以及其相關之裝置。在一些實施例中，此方法包括移除介電層之選定的部分以形成一開口，此開口包括一上部(例如為溝槽)以及一下部(例如為介層窗)。進行一預填充層(pre-fill layer)之選擇性沈積步驟以填入一部分之此開口之下部中。接著，一阻障層、一晶種層及一導電層係依序形成於此預填充層上。藉由選擇性沈積一預填充層填入此開口之下部 中，此開口之下部中的空隙在以電化學電鍍形成導電層之步驟之前即被填滿，因此可防止空隙之形成。
第1A圖係本揭露某些實施例之具有一或多層導電 內連線層100之基底102的剖面圖。介電層106係設於基底102上。一開口向下延伸穿過介電層106，此開口包括設於水平面101上之上部110以及設於水平面101下之下部108。此開口之最長的縱軸對最短之橫軸之比例為約4：1至約10：1。此比例亦稱為徑長比。
此開口之下部108係填有第一導電層114，而其上 部110係填有第二導電層118。在一些實施例中，此開口可為一垂直延伸穿過介電層106之雙鑲嵌結構。在此實施例中，此開口可包括垂直穿過介電層106之溝槽及其下之介層窗。此介層窗之橫向尺寸小於溝槽之橫向尺寸。一部分之介層窗內可填有第一導電層114，例如第一導電層114可填入一半之介層窗、少於一半之介層窗、或多於一半之介層窗。介層窗其餘的部分以及溝槽可填有第二導電層118。
第一導電層114及第二導電層118之材料可為相同 或不同。例如，第一導電層114及第二導電層118之材料皆可包括Cu。或者，第一導電層114可包括Co、Ru、Al、Mo、W、CoW或CoWP。上阻障層116係設於第一導電層114與第二導電層118之間。此上阻障層116覆蓋開口之上部110的底部以及側壁之表面。此上阻障層116可包括TaN、TiN、MnN、SiC、SiN、SiOC或SiON。
在一些實施例中，第一導電層114之頂部、底部及 側壁係被一金屬氧化物阻障層112所圍繞。金屬氧化物阻障層112設於側壁上之部分的厚度可為約1nm至約10nm。金屬氧化物阻障層112設於底部上之另一部分的厚度可小於其設於側壁上之部分的厚度。在一些實施例中，金屬氧化物阻障層112可為氧化錳(MnOx)。在其它實施例中，金屬氧化物阻障層112亦可包括下列成分之氧化物：Mg、Al、Zr、Mo、Ti、Ta或W。 此上阻障層116及金屬氧化物阻障層112係用以防止第一導電層114及第二導電層118遷移到介電層106。
介電層106以及填入於其中之金屬氧化物阻障層 112、上阻障層116、第一導電層114及第二導電層118可為導電內連線層130之一部分。蝕刻停止層104係形成於基底102上，且設於介電層106之下。一或多個額外之導電內連線層(例如103)可形成於導電內連線層130之下或之上，且與導電內連線層130連接。在一些實施例中，第一導電層114可電性連接至下層之導電內連線層103。在其它某些實施例中，導電內連線層130可直接連接一半導體裝置之主動區。
第1B圖係本揭露其它某些實施例之具有一或多層 導電內連線層之基底102的剖面圖。介電層106係形成於半導體基底102以及蝕刻停止層104之上。一開口向下延伸穿過介電層106以及蝕刻停止層104，此開口包括下部108以及上部210。此下部108係填有第一導電層124，而此上部210係填有第二導電層128。此上阻障層126係沿著水平面121設置，且將第一導電層124與第二導電層128分離。晶種層127可形成於上阻障層126與第二導電層128之間。此上阻障層126係覆蓋開口之上部210 的底部以及側壁之表面。
下阻障層122，包括第一部分122a以及第二部分 122b。此第一部分122a設於開口之下部108的側壁上，而此第二部分122b設於開口之上部110的側壁上。此下阻障層122之第二部分122b亦設於介電層106與上阻障層126之間。在一些實施例中，下部108以及上部210之底表面上並未設有阻障層，故第一導電層124係鄰接另一下層之導電內連線層103或半導體裝置之主動區。在一些實施例中，開口之下部108可為介層窗之一部分，而上部210可為一溝槽。
第2圖係本揭露某些實施例之填充間隙之方法的流程圖200。
步驟202移除介電層之選定的部分，以形成一開口，此開口包括上部110以及下部108。
步驟204於開口之下部填入第一導電層。在一些實施例中，開口之下部可藉由第一電鍍步驟填充。在其它實施例中，開口之下部可藉由氣相沉積步驟填充，例如化學氣相沉積、物理氣相沉積等步驟。
步驟206形成上阻障層於第一導電層上且覆蓋開口之上部的底部以及側壁之表面。
步驟208於開口之上部剩餘的空間中填入第二導電層。在一些實施例中，此開口之上部剩餘的空間可藉由第二電鍍步驟填充，例如一電鍍步驟。
藉由在將第二導電層填入開口之上部之前，於開口之下部填入第一導電層，方法200可防止孔隙形成於開口之 下部。
第3圖係本揭露某些其它實施例之填充導電內連線層之間隙之方法的流程圖300。
應注意的是，雖然以下將揭露數個較佳實施例(例如方法200、300及500)，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作任意之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。例如，某些步驟可以不同之順去進行，或者可與其它未於此揭露揭示之步驟共同進行。此外，並非所有以下教示之步驟接為實施本揭露之必要步驟。此外，本揭露所教示之一或多個步驟可藉由一或多個步驟或階段實施。
步驟302移除介電層之選定的部分，以形成一開口，此開口包括上部以及下部。此開口可藉由雙鑲崁步驟形成。在一些實施例中，開口可藉由介層窗優先步驟(via first process)、溝槽優先步驟(trench first process)或自對準雙鑲嵌步驟形成。
步驟304於開口之下部填入合金層，此合金層包括第一金屬元素以及第二金屬元素。
步驟306進行一退火步驟以於合金層及介電層之界面形成金屬氧化物阻障層。此金屬氧化物阻障層包括自合金層遷移出之第二金屬元素。
步驟308形成一上阻障層於金屬氧化物阻障層及介電層上。
步驟310於開口之上部填入第二導電層。此第二導電層可藉由電化學電鍍步驟形成。
第4A-4E圖係本揭露實施例之半導體裝置在填充間隙之方法中的各階段的剖面圖。雖然第4A-4E圖係以方法400描述，然而此技術領域中具有通常知識者當可理解第4A-4E圖所繪之結構並不限於此方法。
如第4A圖所示，移除設於基底102上之介電層106之選定的部分以形成開口，此開口包括上部110以及下部108。在一些實施例中，一蝕刻停止層104係設於介電層106之下。在此實施例中，蝕刻停止層104之一對應的部分亦在相同之蝕刻步驟中被移除，以露出其下之導電內連線層103。此開口可藉由雙鑲崁步驟形成，而介層窗108可形成於溝槽110之下。在一些實施例中，開口可藉由介層窗優先步驟(via first process)、溝槽優先步驟(trench first process)或自對準雙鑲嵌步驟形成。
如第4B圖所示，合金層413係填入於開口之下部108，此合金層413包括第一金屬元素以及第二金屬元素。在一些實施例中，第一金屬元素可包括Cu，而第二金屬元素包括Mn。在其它某些實施例中，合金層之第二金屬元素包括Mn、Mg、Al、Zr、Mo、Ti、Ta或W。此填充步驟可為一由底部往上之電鍍步驟(bottom up plating process)。在此步驟中，合金層之成長始於開口之下部411的底部，並向上成長至開口之下部沿著平面101之表面。此電鍍步驟可為一無電極電鍍步驟(electroless plating process)。此步驟具有包含作為還原劑之甲醛(formaldehyde)或乙醛酸(glyoxyic acid)的反應浴(bath)。此 反應浴可更包括銅有機化合物溶劑(copper organic compound solvent)。
如第1C圖所示，進行一退火步驟以於合金層413及介電層106之界面形成金屬氧化物阻障層112。此金屬氧化物阻障層112包括自合金層413遷移出之第二金屬元素。同時，包含剩餘之第一金屬元素的第一導電層114取代合金層413。金屬氧化物阻障層112設於底部上之另一部分的厚度可小於其設於側壁上之部分的厚度。用於形成金屬氧化物阻障層112的氧可來自鄰接之介電層106，亦可來自合金層413所暴露之空氣中。此退火步驟可於操作腔室(processing chamber)進行，其退火溫度可為約300℃(攝氏)至約450℃。此退火步驟之操作時間可為約10分鐘至約60分鐘。
如第4D圖所示，形成上阻障層416於金屬氧化物阻障層112及介電層106上。此上阻障層416係設於上部110的底部以及側壁之表面上。在某些實施例中，此上阻障層416可藉由氣相沉積步驟形成，例如化學氣相沉積、物理氣相沉積等步驟。在一些實施例中，此上阻障層416可包括TaN、TiN、MnN、SiC、SiN、SiOC或SiON。此上阻障層416包括一薄襯層，此薄襯層覆蓋開口之上部的頂部、底部及側壁，以防止導電層遷移進入介電層。
如第4E圖所示，第二導電層418係填入於開口之上部110中。在一些實施例中，此第二導電層418包括Cu。晶種層417可於形成第二導電層418之前形成於上部110中。此晶種層417之材料可與第二導電層418相同或不同。此晶種層417可藉 由物理氣相沉積形成。於上述沈積步驟之後，可進行一平坦化步驟以移除多餘之第二導電層。此平坦化步驟例如可為一化學機械研磨步驟。
第5圖係本揭露某些其它實施例之填充間隙之方法500的流程圖。
步驟502形成第一阻障層於開口上，此開口向下延伸穿過介電層。此開口包括上部以及下部。
步驟504自上部及下部之底面移除第一阻障層之選定之部分，並留下設於開口之上部及下部之側壁上之保留部分。
步驟506於開口之下部填入第一導電層。
步驟508形成上阻障層於開口之上部上且覆蓋第一導電層114之上表面。
步驟510於開口之上部填入第二導電層於上阻障層上。
第6A-6E圖係本揭露實施例之半導體裝置在填充間隙之方法中的各階段的剖面圖。雖然第6A-6E圖係以方法500描述，然而此技術領域中具有通常知識者當可理解第4A-4E圖所繪之結構並不限於此方法。
如第6A圖所示，第一阻障層122係形成於開口上，此開口向下延伸穿過介電層106。此開口包括上部110以及下部108。
如第6B圖所示，自開口之上部及下部之底面移除第一阻障層122之選定之部分，並留下設於開口之上部及下部 之側壁上之保留部分。設於第一阻障層122之下的導電內連線層103被暴露出來。在一些實施例中，可藉由電漿蝕刻步驟移除第一阻障層之選定之部分。此電漿蝕刻步驟可使用氬氣或氬氣與氫氣之混合氣體。此電漿蝕刻步驟之氣體流速可為約100sccm(Standard Cubic Centimeters per Minute)至約1000sccm。 此電漿蝕刻步驟之操作功率可為約120W至約800W，而其操作時間可為約30秒至約240秒。此電漿蝕刻步驟可於操作腔室中進行，其溫度可為約25℃至約300℃，而其反應壓力可為約1torr至約10torr。
如第6C圖所示，第一導電層124係填入開口之下部108。在此步驟中，第一導電層114之成長始於開口之下部中沿著平面611之底部，並向上成長至開口之下部沿著平面121之表面。第一導電層124可直接成長於導電內連線層103上。在一些實施例中，下部108可藉由無電極電鍍步驟填充。此無電極電鍍步驟具有包含作為還原劑之甲醛(formaldehyde)或乙醛酸(glyoxyic acid)的反應浴(bath)。此反應浴可更包括銅有機化合物溶劑(copper organic compound solvent)。此第一導電層124可包括Co、Ru、Al、Mo、W、CoW或CoWP。在一些實施例中，此下部108可藉由化學氣相沉積步驟填充。此化學氣相沉積步驟之溫度可為100℃約至300℃約，而其反應壓力可為約1torr至約10torr。此第一導電層124可更包括Co、Ru或Al。H2、NH3(氨)與有機金屬化合物可共同作為前驅物。
如第6D圖所示，上阻障層126係形成於開口之上部110上，且覆蓋第一導電層124之上表面以及開口之上部110的 底部以及側壁之表面。
如第6E圖所示，第二導電層128係填入於開口之上部110中的上阻障層上。晶種層127可於形成第二導電層128之前形成。此晶種層127之材料可與第二導電層128相同或不同。
本揭露係有關於一種最佳化之間隙填入技術，此技術藉由某些選擇性沈積方法對間隙的下部進行一預沈積步驟。如此，可形成一較佳之內連線層。
綜上所述，本揭露已揭示一些關於導電內連線層之實施例。此導電內連線層包括設於基底上之介電層。此導電內連線層更包括向下延伸穿過介電層之開口，此開口包括設於一水平面上之上部以及設於水平面下之下部。此導電內連線層更包括填入開口之下部之第一導電層，以及設於第一導電層上且覆蓋開口之上部的底部以及側壁之表面的上阻障層。此導電內連線層更包括設於上阻障層上且填入開口之上部的第二導電層。
本揭露亦提供另一關於此導電內連線層之實施例。此導電內連線層包括形成於基底上之一或多層介電層。此導電內連線層更包括垂直穿過介電層之溝槽及其下之介層窗。此介層窗之橫向尺寸小於溝槽之橫向尺寸。此導電內連線層更包括填入部分之介層窗中之第一導電層。此導電內連線層更包括設於第一導電層上且覆蓋溝槽的底部以及側壁之表面之上阻障層。此導電內連線層更包括設於上阻障層上且填入溝槽之第二導電層。
本揭露亦提供另一關於填充此導電內連線層之間 隙之方法之實施例。在此方法中，介電層之選定的部分被移除以形成開口，此開口包括上部以及下部。接著，於開口之下部填入第一導電層。一上阻障層係形成於第一導電層上且覆蓋開口之上部的底部以及側壁之表面。接著，第二導電層係填入於開口之上部剩餘的空間中。
雖然本揭露的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。此外，本揭露之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本揭露揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本揭露使用。因此，本揭露之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。 另外，每一申請專利範圍構成個別的實施例，且本揭露之保護範圍也包括各個申請專利範圍及實施例的組合。

Claims (20)

  1. 一種導電內連線層，包括：一介電層，設於一基底上；一開口，向下延伸穿過該介電層，該開口包括設於一水平面上之一上部以及設於該水平面下之一下部；一第一導電層，填入該開口之該下部；一上阻障層，設於該第一導電層上且覆蓋該開口之該上部的底部以及側壁之表面；及一第二導電層，設於該上阻障層上且填入該開口之該上部。
  2. 如申請專利範圍第1項所述之導電內連線層，更包括：一下阻障層，包括一第一部分以及一第二部分，其中該第一部分設於該開口之該下部的側壁上，而該第二部分設於該開口之該上部的側壁上，且設於該介電層與該上阻障層之間。
  3. 如申請專利範圍第2項所述之導電內連線層，其中該第一導電層鄰接其下之一導電內連線層。
  4. 如申請專利範圍第2項所述之導電內連線層，其中該下阻障層包括TaN、TiN、MnN、SiC、SiN、SiOC或SiON。
  5. 如申請專利範圍第1項所述之導電內連線層，更包括：一金屬氧化物阻障層，圍繞該第一導電層之頂部、底部及側壁。
  6. 如申請專利範圍第5項所述之導電內連線層，其中該金屬氧化物阻障層包括氧化錳。
  7. 如申請專利範圍第5項所述之導電內連線層，其中該金屬 氧化物阻障層包括下列成分之氧化物：Mn、Mg、Al、Zr、Mo、Ti、Ta或W。
  8. 如申請專利範圍第1項所述之導電內連線層，其中該開口之最長的縱軸對最短之橫軸之比例為約4：1至約10：1。
  9. 如申請專利範圍第1項所述之導電內連線層，其中該上阻障層包括TaN、TiN、MnN、SiC、SiN、SiOC或SiON。
  10. 如申請專利範圍第1項所述之導電內連線層，其中該第一導電層包括Co、Ru、Al、Mo、W、CoW或CoWP。
  11. 一種導電內連線層，包括：一或多層介電層，形成於一基底上；一溝槽及其下之一介層窗，垂直穿過該介電層，其中該介層窗之橫向尺寸小於該溝槽之橫向尺寸；一第一導電層，填入一部分之該介層窗中；一上阻障層，設於該第一導電層上且覆蓋該溝槽的底部以及側壁之表面；及一第二導電層，設於該上阻障層上且填入該溝槽。
  12. 如申請專利範圍第11項所述之導電內連線層，更包括：一晶種層，設於該上阻障層與該第二導電層之間。
  13. 如申請專利範圍第11項所述之導電內連線層，更包括：一下阻障層，包括一第一部分以及一第二部分，其中該第一部分設於該介層窗之該部分的側壁上，而該第二部分設於該溝槽的側壁上，且設於該介電層與該上阻障層之間。
  14. 如申請專利範圍第11項所述之導電內連線層，其中該第一導電層鄰接其下之一導電內連線層。
  15. 一種填充導電內連線層之一間隙之方法，包括：移除一介電層之一選定的部分，以形成一開口，該開口包括一上部以及一下部；於該開口之該下部填入一第一導電層；形成一上阻障層於該第一導電層上且覆蓋該開口之該上部的底部以及側壁之表面；及於該開口之該上部剩餘的一空間中填入一第二導電層。
  16. 如申請專利範圍第15項所述之填充導電內連線層之該間隙之方法，其中形成該第一導電層之步驟包括：於該開口之該下部填入一合金層，該合金層包括一第一金屬元素以及一第二金屬元素；進行一退火步驟以於該合金層及該介電層之一界面形成一金屬氧化物阻障層，其中該金屬氧化物阻障層包括自該合金層遷移出之該第二金屬元素；形成一上阻障層於該金屬氧化物阻障層上且覆蓋該開口之該上部的底部以及側壁之表面；及於該開口之該上部剩餘的一空間中填入一第二導電層。
  17. 如申請專利範圍第16項所述之填充導電內連線層之該間隙之方法，其中該合金層之該第一金屬元素包括Cu，而該合金層之該第二金屬元素包括Mn、Mg、Al、Zr、Mo、Ti、Ta或W。
  18. 如申請專利範圍第15項所述之填充導電內連線層之該間隙之方法，其中在填入該第一導電層之前，更包括：形成一第一阻障層於該開口上；及 自該開口之該上部及該下部之底面移除該第一阻障層之一選定之部分，並留下設於該開口之該上部及下部之側壁上之一保留部分。
  19. 如申請專利範圍第15項所述之填充導電內連線層之該間隙之方法，其中該開口之該下部係以由底部往上之電鍍步驟(bottom up plating process)或以化學氣相沉積法填充。
  20. 如申請專利範圍第11項所述之填充導電內連線層之該間隙之方法，其中該開口係以雙鑲崁步驟形成。
TW103146479A 2014-03-21 2014-12-31 導電內連線層及填充導電內連線層之間隙之方法 TWI548032B (zh)

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