CN104934409A - 后道工序互连层上的通孔预填充 - Google Patents

后道工序互连层上的通孔预填充 Download PDF

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CN104934409A
CN104934409A CN201410234625.4A CN201410234625A CN104934409A CN 104934409 A CN104934409 A CN 104934409A CN 201410234625 A CN201410234625 A CN 201410234625A CN 104934409 A CN104934409 A CN 104934409A
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layer
conductive
opening
barrier layer
conductive layer
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CN104934409B (zh
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彭兆贤
郭启良
李明翰
李香寰
眭晓林
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及一种使用减少空隙的预填充工艺形成的金属互连层及其相关联的方法。在一些实施例中，金属互连层具有设置在衬底上方的介电层。具有水平面以上的上部和水平面以下的下部的开口向下延伸穿过介电层。第一导电层填充开口的下部。上部势垒层设置在第一导电层上方以覆盖开口的上部的底面和侧壁表面。第二导电层设置在上部势垒层上方以填充开口的上部。

Description

后道工序互连层上的通孔预填充
技术领域
本发明一般地涉及半导体技术领域，更具体地，涉及导电互连层及其形成方法。
背景技术
在集成电路(IC)的制造过程中，器件形成在晶圆上且通过多个导电互连层连接在一起。通过首先在介电层中形成间隙(如，沟槽和通孔)，然后用导电材料填充间隙来形成这些导电互连层。
导电材料通常通过电化学镀工艺(ECP工艺)形成在间隙内。首先在介电层中的间隙内形成势垒层。然后在势垒层的上方形成晶种层。用导电材料连续填充间隙的剩余空间。然后实施平坦化以去除多余的导电材料。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种导电互连层，包括：介电层，设置在衬底上方；开口，向下延伸穿过所述介电层，所述开口包括水平面以上的上部和水平面以下的下部；第一导电层，填充所述开口的下部；上部势垒层，设置在所述第一导电层上方，所述上部势垒层覆盖所述开口的上部的底面和侧壁表面；以及第二导电层，设置在所述上部势垒层上方，所述第二导电层填充所述开口的上部。
该导电互连层还包括下部势垒层，所述下部势垒层包括设置在所述开口的下部的侧壁上的第一部分和在所述介电层和所述上部势垒层之间设置在所述开口的上部的侧壁上的第二部分。
在该导电互连层中，所述第一导电层邻接下方的导电互连层。
在该导电互连层中，所述下部势垒层包括氮化钽(TaN)、氮化钛(TiN)、氮化锰(MnN)、碳化硅(SiC)、氮化硅(SiN)、碳氧化硅(SiOC)或氮氧化硅(SiON)。
该导电互连层还包括环绕所述第一导电层的顶部区、底部区和侧壁区的金属氧化物势垒层。
在该导电互连层中，所述金属氧化物势垒层包括氧化锰。
在该导电互连层中，所述金属氧化物势垒层包括锰(Mn)、镁(Mg)、铝(Al)、锆(Zr)、钼(Mo)、钛(Ti)、钽(Ta)或钨(W)的氧化物。
在该导电互连层中，所述开口的最大纵向尺寸与最小横向尺寸的比率介于约4:1和约10:1之间。
在该导电互连层中，所述上部势垒层包括氮化钽(TaN)、氮化钛(TiN)、氮化锰(MnN)、碳化硅(SiC)、氮化硅(SiN)、碳氧化硅(SiOC)或氮氧化硅(SiON)。
在该导电互连层中，所述第一导电层包括钴(Co)、钌(Ru)、铝(Al)、钼(Mo)、钨(W)、CoW或钴钨磷(CoWP)。
根据本发明的另一方面，提供了一种导电互连层，包括：一个或多个介电层，形成在衬底的上方；沟槽和下面的通孔，垂直延伸穿过所述介电层，其中，所述通孔的横向尺寸小于所述沟槽的横向尺寸；第一导电层，填充所述通孔的一部分；上部势垒层，设置在所述第一导电层上方，所述上部势垒层覆盖所述沟槽的底面和侧壁表面；以及第二导电层，设置在所述上部势垒层上方且填充所述沟槽。
该导电互连层还包括晶种层，所述晶种层设置在所述上部势垒层和所述第二导电层之间。
该导电互连层还包括下部势垒层，所述下部势垒层包括设置在所述通孔的部分的侧壁上的第一部分和在所述介电层和所述上部势垒层之间设置在所述沟槽的侧壁上的第二部分。
在该导电互连层中，所述第一导电层邻接下方的导电互连层。
根据本发明的又一方面，提供了一种填充用于互连件的间隙的方法，所述方法包括：去除介电层的所选择部分，以形成包括上部和下部的开口；用第一导电层填充所述开口的下部；在所述第一导电层上方施加上部势垒层，所述上部势垒层覆盖所述开口的上部的底面和侧壁表面；以及用第二导电层填充所述开口的上部的剩余空间。
在该方法中，所述第一导电层由下列步骤形成：用包括第一金属元素和第二金属元素的合金层填充所述开口的下部；进行退火以在所述合金层和所述介电层的界面处形成金属氧化物势垒层，其中，所述金属氧化物势垒层包括从所述合金层迁移来的所述第二金属元素；在所述金属氧化物势垒层上方施加所述上部势垒层，所述上部势垒层覆盖所述开口的上部的底面和侧壁表面；以及用所述第二导电层填充所述开口的上部的剩余空间。
在该方法中，所述合金层的所述第一金属元素是铜，且所述合金层的所述第二金属元素是锰(Mn)、镁(Mg)、铝(Al)、锆(Zr)、钼(Mo)、钛(Ti)、钽(Ta)或钨(W)。
该方法在填充所述第一导电层之前，还包括：在所述开口上方施加第一势垒层；以及从所述开口的上部和下部的底面去除所述第一势垒层的选择部分，同时保留所述开口的上部和下部的侧壁上的剩余部分。
在该方法中，通过自下而上的镀工艺或化学汽相沉积工艺填充所述开口的下部。
在该方法中，通过双镶嵌工艺形成所述开口。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该注意，根据工业中的标准实践，不用按比例绘制各种部件。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1A示出了根据一些实施例具有一个或多个导电互连层的衬底的截面图。
图1B示出了根据一些其他实施例具有一个或多个导电互连层的衬底的截面图。
图2示出了根据一些实施例填充用于互连件的间隙的方法的流程图。
图3示出了根据一些附加实施例填充用于互连件的间隙的方法的流程图。
图4A至图4E示出了根据一些附加实施例的导电互连层的截面图，其示出填充用于互连件的间隙的方法。
图5示出了根据一些其他实施例填充用于互连件的间隙的方法的流程图。
图6A至图6E示出了根据一些其他实施例的导电互连层的截面图，其示出填充用于互连件的间隙的方法。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现所提供主题的不同特征。下面描述了组件和布置的特定实例以简化本发明。当然，这些仅是实例而不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括以直接接触的方式形成第一部件和第二部件的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加部件，使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可以在多个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不表示所讨论的多个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在...之下”、“在...下面”、“下面的”、“在...之上”、以及“上面的”等的空间相对术语，以描述如图中所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除图中所示的方位之外，空间相对术语旨在包括使用或操作中的器件的不同方位。装置可以以其他方式进行定位(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地进行相应的解释。
由于不断地按比例缩小半导体器件，也减小了后道工序(BEOL)金属互连件的部件尺寸。BEOL金属互连件的减小的部件尺寸导致间隙(诸如沟槽和通孔)的纵横比较大，在金属互连件的形成期间用导电层填充间隙。在双镶嵌金属化工艺中的通孔和沟槽的较大纵横比使得电化学镀(ECP)工艺难以进行填充，从而导致在通孔和沟槽中形成空隙、或其中未形成导电材料的区域。由于空隙不具有导电材料，所以它们会导致不良连接并损害可靠性。
因此，本发明涉及一种使用通孔预填充工艺填充间隙以减少双镶嵌金属层内的空隙的方法及其相关联的装置。在一些实施例中，该方法包括去除介电层的所选择部分以形成包括上部(例如，沟槽)和下部(例如，通孔)的开口。实施预填充层的选择性沉积以填充开口的下部的一部分。然后在预填充层上方连续形成势垒层、晶种层和导电层。通过选择性沉积预填充层以填充开口的下部，在使用ECP工艺形成导电层之前，填充了开口的下部中的空隙，从而避免空隙的形成。
图1A示出了根据一些实施例具有一个或多个导电互连层的衬底的截面图100。介电层106设置在半导体衬底102的上方。向下延伸穿过介电层106的开口包括水平面101之上的上部110和水平面101之下的下部108。开口的最大纵向尺寸与最小横向尺寸的比率可以介于约4:1和约10:1之间。该比率称为纵横比。
用第一导电层114填充开口的下部108，并且用第二导电层118填充开口的上部110。在一些实施例中，开口可以是垂直延伸穿过介电层106的双镶嵌结构。在这样的实施例中，开口可以包括垂直延伸穿过介电层106的沟槽和下面的通孔。通孔的横向尺寸小于沟槽的横向尺寸。通孔的一部分(例如，通孔的一半、小于通孔的一半或大于通孔的一半)可以由第一导电层114填充。通孔的剩余部分连同沟槽一起可以由第二导电层118填充。
第一导电层114和第二导电层118可以是相同或不同的材料。例如，第一导电层114和第二导电层118均可以包括铜(Cu)，或第一导电层114可以包括钴(Co)、钌(Ru)、铝(Al)、钼(Mo)、钨(W)、CoW、或钴钨磷(CoWP)。上部势垒层116设置在第一导电层114和第二导电层118之间。上部势垒层116覆盖开口的上部110的底面和侧壁表面。上部势垒层116可以包括氮化钽(TaN)、氮化钛(TiN)、氮化锰(MnN)、碳化硅(SiC)、氮化硅(SiN)、碳氧化硅(SiOC)或氮氧化硅(SiON)。
在一些实施例中，金属氧化物势垒层112可以环绕第一导电层114的顶部区、底部区和侧壁区。侧壁区上的金属氧化物势垒层112的一部分可以具有的厚度在约1nm至约10nm的范围内。底部区上的金属氧化物势垒层112的另一部分的厚度可以比侧壁区上的厚度薄。在一些实施例中，金属氧化物势垒层112可以是氧化锰(MnOx)。在其他实施例中，金属氧化物势垒层112也可以包括具有镁(Mg)、铝(Al)、锆(Zr)、钼(Mo)、钛(Ti)、钽(Ta)、或钨(W)的氧化物。形成上部势垒层116和金属氧化物势垒层112以有助于防止第一导电层114和第二导电层118迁移至介电层106。
介电层106、填充在其中的金属氧化物势垒层112、上部势垒层116以及第一导电层114和第二导电层118可以是导电互连层130的一部分。在衬底102上方蚀刻停止层104形成的介电层106的下面。在导电互连层130之下或之上可以形成并连接有一个或多个附加导电互连层(例如，103)。在一些实施例中，第一导电层114可以电连接至下部导电互连层103。在一些其他实施例中，导电互连层130可以直接连接至半导体器件的有源区。
图1B示出了根据一些其他实施例的具有一个或多个导电互连层的衬底的截面图120。介电层106形成在半导体衬底102和蚀刻停止层104的上方。向下延伸穿过介电层106和蚀刻停止层104的开口包括由第一导电层124填充的下部108和由第二导电层128填充的上部210。沿着将第一导电层124和第二导电层128分隔开的水平面121设置上部势垒层126。晶种层127可以形成在上部势垒层126和第二导电层128之间。上部势垒层126覆盖开口的上部210的底面和侧壁表面。
下部势垒层122包括设置在开口的下部108的侧壁上的第一部分122a和设置在开口的上部210的侧壁上的第二部分122b。下部势垒层的第二部分122b夹置在介电层106和上部势垒层126之间。在一些实施例中，在下部108和上部210的底面上没有设置势垒层，使得第一导电层124与半导体器件的另一下部导电互连层103或有源区邻接。在一些实施例中，开口的下部108可以是通孔的一部分，并且上部210可以是沟槽。
图2示出了根据一些实施例填充间隙的方法的流程图200。
在步骤202中，去除介电层的所选择部分，以形成包括上部和下部的开口。
在步骤204中，用第一导电层填充开口的下部。在一些实施例中，可以通过第一镀工艺填充开口的下部。在其他实施例中，可以通过汽相沉积技术(例如，CVD、PVD等)填充开口的下部。
在步骤206中，在第一导电层上方形成上部势垒层，以覆盖开口的上部的底面和侧壁表面。
在步骤208中，用第二导电层填充开口的上部的剩余空间。在一些实施例中，可以通过第二镀工艺(例如，电镀工艺)填充开口的上部的剩余空间。
在用第二导电层填充开口的上部之前，通过用第一导电层填充开口的下部，方法200防止在开口的下部内形成空隙。
图3示出了根据一些附加实施例填充用于互连件的间隙的方法的流程图300。
尽管下面将所公开的方法(例如，方法200、300和500)示出和描述为一系列步骤或事件，但是应该理解，这些步骤或事件的示出顺序不应解释为限制意义。例如，一些步骤可以以不同的顺序发生和/或除在此示出和/或描述的步骤或事件之外，与其他步骤或事件同时发生。此外，实施在此描述的一个或多个方面或实施例不一定需要所有示出的步骤。而且，在一个或多个单独的步骤和/或阶段中可以实施在此所描述的一个或多个步骤。
在步骤302中，去除介电层的所选择部分以形成包括上部和下部的开口。可以通过镶嵌工艺形成开口。在一些实施例中，通过先通孔、先沟槽或自对准双镶嵌工艺可以形成开口。
在步骤304中，用包括第一金属元素和第二金属元素的合金层填充开口的下部。
在步骤306中，实施退火工艺以在合金层和介电层的界面处形成金属氧化物势垒层。金属氧化物势垒层包括从合金层迁移来的第二金属元素。
在步骤308中，在金属氧化物势垒层和介电层的上方形成上部势垒层。
在步骤310中，用第二导电层填充开口的上部。通过电化学镀(ECP)工艺可以形成第二导电材料。
图4A至图4E示出了根据一些实施例的半导体器件的截面图，其示出填充间隙的方法。尽管关于方法400描述了图4A至图4E，但是应该理解，图4A至图4E中所公开的结构并不限于这样一种方法。
如图4A所示，去除设置在衬底102的上方的介电层106的所选择部分，以形成包括上部110和下部108的开口。在一些实施例中，在介电层106的下方设置有蚀刻停止层104。在这样的实施例中，在相同的蚀刻工艺中也去除蚀刻停止层104的相应部分，使得露出了下面的导电互连层103。可以通过双镶嵌工艺形成开口，其中，通孔108可以形成在沟槽110的下方。在一些实施例中，通过先通孔、先沟槽或自对准双镶嵌工艺可以形成开口。
如图4B所示，用包括第一金属元素和第二金属元素的合金层413填充开口的下部108。在一些实施例中，第一金属元素可以包括铜，且第二金属元素可以包括锰。在一些其他实施例中，合金层的第二金属元素可以是锰(Mn)、镁(Mg)、铝(Al)、锆(Zr)、钼(Mo)、钛(Ti)、钽(Ta)或钨(W)。填充工艺可以是自下而上的镀工艺，其中，合金层生长开始于开口的下部108的底部并且向上发展至沿着平面101的开口的下部的表面。镀工艺可以是具有包括甲醛或乙醇酸的浴液作为还原剂的化学镀工艺。浴液还可以包括铜有机化合物溶剂。
如图4C所示，实施退火工艺以在合金层413和介电层106的界面处形成金属氧化物势垒层112。金属氧化物势垒层112包括从合金层迁移来的第二金属元素。同时，包括剩余第一金属元素的第一导电层114代替合金层413。金属氧化物势垒层112在下部的底部处的一部分可以比侧壁和顶面上的剩余部分薄。用于形成金属氧化物势垒层112的氧气可以来自邻接的介电层106或空气(合金层413暴露于该空气)。在约300℃(摄氏度)至约450℃的范围内的温度下，可以在处理室内实施退火工艺持续约10min(分钟)和约60min的范围内的时间段。
如图4D所示，上部势垒层416形成在金属氧化物势垒层112和介电层106的上方。上部势垒层416设置在上部110的底面和侧壁表面上。在一些实施例中，通过汽相沉积工艺(例如，CVD、PVD等)可以形成上部势垒层416。在各个实施例中，上部势垒层416可以包括氮化钽(TaN)、氮化钛(TiN)、氮化锰(MnN)、碳化硅(SiC)、氮化硅(SiN)、碳氧化硅(SiOC)或氮氧化硅(SiON)。上部势垒层416包括覆盖开口的上部的顶面、底面和侧壁表面的薄衬里层，该薄衬里层被配置为防止导电层迁移至介电层中。
如图4E所示，用第二导电层418填充开口的上部110。在一些实施例中，第二导电层418是铜。在形成第二导电层418之前，包括与第二导电层418相同或不同的材料的晶种层417可以形成在上部110内。通过物理汽相沉积(PVD)可以形成晶种层417。在沉积之后施加平坦化工艺(例如，化学机械抛光(CMP)工艺)以去除第二导电层的多余部分。
图5示出了根据一些其他实施例填充间隙的方法500的流程图。
在步骤502中，在向下延伸穿过介电层的开口的上方形成第一势垒层，其中，开口包括上部和下部。
在步骤504中，从上部和下部的底面去除第一势垒层的选择部分，同时保留开口的上部和下部的侧壁上的剩余部分。
在步骤506中，用第一导电层填充开口的下部。
在步骤508中，在开口的上部的上方形成上部势垒层，以覆盖第一导电层的上表面。
在步骤510中，用第二导电层填充开口的位于上部势垒层上方的上部。
图6A至图6E示出了根据一些实施例的半导体器件的截面图，其示出填充间隙的方法。尽管关于方法500描述了图6A至图6E，但是应该理解，图6A至图6E中公开的结构并不限于这种方法。
如图6A所示，第一势垒层122形成在向下延伸穿过介电层106的开口的上方，其中，开口包括上部110和下部108。
如图6B所示，从上部和下部的底面去除第一势垒层122的选择部分，同时保留开口的上部和下部的侧壁上的剩余部分。露出下面的导电层103。在一些实施例中，通过等离子体蚀刻工艺去除第一势垒层的选择部分。等离子体蚀刻工艺使用气流为约100sccm(每分钟标准毫升)至约1000sccm的氩(Ar)气或Ar和氢气(H2)的混合气体。在温度保持在约25℃和约300℃之间的范围内且气压保持在约1torr和约10torr的范围内的处理室内，通过介于约120W(瓦特)至约800W之间的功率施加等离子体蚀刻工艺维持一段时间(介于约30s(秒)至约240s之间)。
如图6C所示，用第一导电层124填充开口的下部108，其开始于开口的下部的沿着平面611的底部且向上发展至开口的下部的沿着平面121的表面。可以在下面的导电层103上直接生长第一导电层124。在一些实施例中，可以通过化学镀工艺填充下部108。化学镀工艺具有包括甲醛或乙醇酸的浴液作为还原剂。浴液还可以包括铜有机化合物溶剂。第一导电层124可以包括钴(Co)、钌(Ru)、铝(Al)、钼(Mo)、钨(W)、CoW、或钴钨磷(CoWP)。在一些其他实施例中，在约100℃和约300℃之间的范围内的温度和介于约1torr和约10torr之间的范围内的气压的条件下，可以通过化学汽相沉积(CVD)工艺填充下部108。第一导电层124还可以包括Co、Ru或Al。H2或NH3(氨)连同有机金属化合物一起可以用作前体。
如图6D所示，在开口的上部110上方形成上部势垒层126，以覆盖第一导电层124的上表面以及开口的上部110的底面和侧壁表面。
如图6E所示，用第二导电层128填充开口的位于上部势垒层上方的上部110。在形成第二导电层128之前，可以形成包括与第二导电层128相同或不同的材料的晶种层127。
本发明涉及一种优化的间隙填充技术，其通过一些选择性沉积方法预填充间隙的下部。结果，形成更好的导电互连层。
因此，应该理解，一些实施例涉及导电互连层。导电互连层包括在衬底上方形成的介电层。导电互连层还包括向下延伸穿过介电层的开口，其中，开口包括水平面以上的上部和水平面以下的下部。导电互连层还包括填充开口的下部的第一导电层、设置在第一导电层上方的上部势垒层以覆盖开口的上部的底面和侧壁表面、以及设置在上部势垒层上方的第二导电层，以填充开口的上部。
其他实施例涉及导电互连层。导电互连层包括在衬底上方形成的一个或多个介电层。导电互连层还包括垂直延伸穿过介电层的沟槽和下面的通孔。通孔的横向尺寸小于沟槽的横向尺寸。导电互连层还包括填充通孔的一部分的第一导电层。导电互连层还包括设置在第一导电层上方的上部势垒层以覆盖沟槽的底面和侧壁表面。导电互连层还包括设置在上部势垒层上方的第二导电层以填充沟槽。
其他实施例还涉及填充用于互连件的间隙的方法。在该方法中，去除介电层的选择部分以形成开口。开口包括上部和下部。然后，用第一导电层填充开口的下部。在第一导电层上方形成上部势垒层，以覆盖第一导电层的上表面以及开口的上部的底面和侧壁表面。然后，用第二导电层填充开口的上部的剩余空间。
上面概述了若干实施例的特征，使得本领域的普通技术人员可以更好地理解本发明的各个方面。本领域的普通技术人员应该理解，可以容易地使用本发明作为基础来设计或更改用于实施与在此所介绍实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域的普通技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此可以对其进行多种变化、替换以及改变。

Claims (10)

1.一种导电互连层，包括：
介电层，设置在衬底上方；
开口，向下延伸穿过所述介电层，所述开口包括水平面以上的上部和水平面以下的下部；
第一导电层，填充所述开口的下部；
上部势垒层，设置在所述第一导电层上方，所述上部势垒层覆盖所述开口的上部的底面和侧壁表面；以及
第二导电层，设置在所述上部势垒层上方，所述第二导电层填充所述开口的上部。
2.根据权利要求1所述的导电互连层，还包括下部势垒层，所述下部势垒层包括设置在所述开口的下部的侧壁上的第一部分和在所述介电层和所述上部势垒层之间设置在所述开口的上部的侧壁上的第二部分。
3.根据权利要求2所述的导电互连层，其中，所述第一导电层邻接下方的导电互连层。
4.根据权利要求2所述的导电互连层，其中，所述下部势垒层包括氮化钽(TaN)、氮化钛(TiN)、氮化锰(MnN)、碳化硅(SiC)、氮化硅(SiN)、碳氧化硅(SiOC)或氮氧化硅(SiON)。
5.根据权利要求1所述的导电互连层，还包括环绕所述第一导电层的顶部区、底部区和侧壁区的金属氧化物势垒层。
6.根据权利要求5所述的导电互连层，其中，所述金属氧化物势垒层包括氧化锰。
7.根据权利要求5所述的导电互连层，其中，所述金属氧化物势垒层包括锰(Mn)、镁(Mg)、铝(Al)、锆(Zr)、钼(Mo)、钛(Ti)、钽(Ta)或钨(W)的氧化物。
8.根据权利要求1所述的导电互连层，其中，所述开口的最大纵向尺寸与最小横向尺寸的比率介于约4:1和约10:1之间。
9.一种导电互连层，包括：
一个或多个介电层，形成在衬底的上方；
沟槽和下面的通孔，垂直延伸穿过所述介电层，其中，所述通孔的横向尺寸小于所述沟槽的横向尺寸；
第一导电层，填充所述通孔的一部分；
上部势垒层，设置在所述第一导电层上方，所述上部势垒层覆盖所述沟槽的底面和侧壁表面；以及
第二导电层，设置在所述上部势垒层上方且填充所述沟槽。
10.一种填充用于互连件的间隙的方法，所述方法包括：
去除介电层的所选择部分，以形成包括上部和下部的开口；
用第一导电层填充所述开口的下部；
在所述第一导电层上方施加上部势垒层，所述上部势垒层覆盖所述开口的上部的底面和侧壁表面；以及
用第二导电层填充所述开口的上部的剩余空间。
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