CN107665860A - 具有界面衬里的ic结构及其形成方法 - Google Patents

具有界面衬里的ic结构及其形成方法 Download PDF

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CN107665860A
CN107665860A CN201710627571.1A CN201710627571A CN107665860A CN 107665860 A CN107665860 A CN 107665860A CN 201710627571 A CN201710627571 A CN 201710627571A CN 107665860 A CN107665860 A CN 107665860A
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metal
ild materials
ild
doping metals
metals layer
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CN107665860B (zh
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张洵渊
M·M·蔡
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GlobalFoundries US Inc
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Abstract

本发明涉及具有界面衬里的IC结构及其形成方法，其实施例可提供一种形成集成电路(integrated circuit；IC)结构的方法，该方法包括：提供结构，该结构具有：导电区，以及位于该导电区上的层级间介电(inter‑level dielectric；ILD)材料，其中，该ILD材料包括至该导电区的接触开口；在该接触开口内形成掺杂金属层，以使该掺杂金属层位于该导电区上方，其中，该掺杂金属层包括用第二金属掺杂的第一金属；以及通过退火该掺杂金属层在该ILD材料的该接触开口内形成至该导电区的接触，以使该第二金属扩散进入该ILD材料中，从而直接在该退火掺杂金属层与该ILD材料之间形成界面衬里(interface liner)。

Description

具有界面衬里的IC结构及其形成方法
技术领域
本发明涉及具有与导电接触相邻的界面衬里的集成电路(integrated circuit；IC)，尤其涉及具有包括自掺杂金属接触扩散的金属化合物的界面衬里的IC结构及其形成方法。
背景技术
各IC可由位于半导体衬底材料的一个或多个芯片上的数十亿互连装置例如晶体管、电阻器、电容器以及二极管组成。包括IC的产品的质量及可行性可至少部分依赖于用以制造该IC以及其中各种组件的结构的技术。IC的制造可包括两个阶段：前端工艺(front-end-of-line；FEOL)制程以及后端工艺(back-end-of-line；BEOL)制程。FEOL通常包括执行于晶圆上直到并包括形成第一“金属层级”(也就是将数个半导体装置连接在一起的金属线)的制程。就晶体管而言，一组垂直延伸的导电接触可提供从电路的其它功能元件至该晶体管的电性连接。BEOL通常包括在形成该第一金属层级之后的制程，包括所有后续金属层级的形成。各金属层级可在其中包括金属线，通过被称为过孔的垂直取向的导线可将该些金属线与其它金属层级连接。在传统的BEOL制程中，形成过孔层以将IC结构中的装置与形成于该过孔顶部上的金属线层连接，在其上形成相继的过孔层，接着形成另一个金属线层等。为了使所制造的装置具有较大的可扩展性及复杂度，可改变金属层级的数目以适合特定的应用，例如提供四至六个金属层级，或者在另一个例子中提供多达16个或更多的金属层级。
延伸于层级之间的导电接触或类似结构例如过孔可经制造以包括额外的材料，从而在导电金属与该IC结构中的绝缘材料之间提供隔离。本文中总体使用术语“接触”、“金属接触”以及/或者“导电接触”来指接触及过孔。在传统制程中，此类结构可包括形成于开口的侧壁上的难熔金属衬里，在该开口中形成金属接触。难熔金属衬里可防止导电金属电迁移进入该IC结构的相邻部分中。尽管已证明难熔金属衬里满足此类目的，但传统形成此类材料可能需要在额外的制程步骤中形成额外的材料以及/或者移除其部分，从而可能增加制造产品的时间及成本。尽管有影响时间及成本的这些因素，但已证明自电路结构移除难熔金属衬里不利于保持通过传统技术所制造的IC结构的质量及所需功能。
发明内容
本发明的第一态样提供一种形成集成电路(integrated circuit；IC)结构的方法，该方法包括：提供结构，该结构包括：导电区，以及位于该导电区上的层级间介电(inter-level dielectric；ILD)材料，其中，该ILD材料包括至该导电区的接触开口；在该接触开口内形成掺杂金属层，以使该掺杂金属层位于该导电区上方，其中，该掺杂金属层包括用第二金属掺杂的第一金属；以及通过退火该掺杂金属层在该ILD材料的该接触开口内形成至该导电区的接触，以使该第二金属扩散进入该ILD材料中，从而直接在该退火掺杂金属层与该ILD材料之间形成界面衬里(interface liner)。
本发明的第二态样提供一种形成至集成电路(IC)中的晶体管结构的导电接触的方法，该方法包括：在位于该晶体管结构上方的ILD材料内形成接触开口，其中，形成该接触开口暴露该晶体管结构的源/漏区或栅极金属；在形成该接触开口以后，在该源/漏区上形成源/漏硅化物；在该接触开口内形成掺杂金属层，其中，该掺杂金属层包括用第二金属掺杂的第一金属；以及通过退火该掺杂金属层在该ILD材料的该接触开口内形成至该导电区的接触，以使该第二金属扩散进入该ILD材料中，从而直接在该退火掺杂金属层与该ILD材料之间形成界面衬里。
本发明的第三态样提供一种集成电路(IC)结构，其包括：晶体管结构，包括：包括源/漏区的衬底，位于该衬底的该源/漏区上的源/漏硅化物，以及位于该衬底上方的栅极金属；层级间介电(ILD)材料，位于该晶体管结构上，其中，该ILD材料包括至该晶体管结构的该源/漏硅化物或该栅极金属的其中之一的接触开口；导电接触，位于该接触开口内，以使该导电接触位于该源/漏硅化物或该栅极金属的其中之一的上方并与其电性耦接，其中，该导电接触的材料组成包括第一金属；以及包括第二金属的界面衬里，直接位于该导电接触与该ILD材料的侧壁之间。
附图说明
通过参照下面的附图来详细说明本发明的实施例，该些附图中类似的附图标记表示类似的元件，以及其中：
图1显示依据本发明的实施例具有接触开口的初始IC结构的剖视图。
图2显示依据本发明的实施例用氮等离子体处理该接触开口的剖视图。
图3显示依据本发明的实施例在该初始IC结构上形成掺杂金属的剖视图。
图4显示依据本发明的实施例通过退火该掺杂金属层形成至该导电区的接触的剖视图。
图5显示依据本发明的实施例的IC结构的剖视图。
应当注意，本发明的附图并非按比例绘制。该些附图意图仅显示本发明的典型态样，因此不应当被认为限制本发明的范围。该些附图中，类似的附图标记表示该些附图之间类似的元件。
具体实施方式
在下面的说明中参照附图，该些附图构成本说明的一部分，且其中示例显示可实施本发明的教导的特定示例实施例。这些实施例经充分详细说明以使本领域的技术人员能够实施本发明的教导，且应当理解，可使用其它实施例且可作变更而不背离本发明的教导的范围。因此，下面的说明仅为示例。
本发明涉及集成电路(IC)结构，其具有形成于接触开口中的至晶体管的导电接触，以及直接位于该导电接触与层级间介电(ILD)材料之间的界面衬里。该导电接触的材料组成可包括第一金属，而该界面衬里可在其中包括第二金属。该界面衬里可通过使该第二金属自该导电接触(经初始掺杂以包括该第二金属)扩散至该导电接触与该ILD材料之间的界面来形成。因此，本发明的实施例还提供形成本文中所述的各种结构的方法。在传统的IC结构中，难熔金属衬里(例如由铜或钨形成)可形成于开口的侧壁上以及电性绝缘材料上，以减少形成于该开口中的导电元件的漏电流、电迁移退化等。不过，对于减少相邻组件之间的隔离距离以及降低此类衬里材料的电阻率的不断增长的需求可能伴随各种技术挑战及/或限制。除其它优点外，本文中所述的各种实施例可改进或甚至替代在导电接触的侧壁上的难熔金属衬里的使用。在本发明的实施例中针对结构及方法应用金属掺杂物还可克服未明确说明的其它技术挑战。
请参照图1，其显示依据本发明将要被处理的结构10的剖视图。在结构10上实施本发明的方法之前，结构10可通过使用传统的技术形成以及/或者可以其初始状态提供。结构10可包括由半导体材料构成的衬底12。可将衬底12设为例如块体半导体衬底以及/或者下方具有绝缘材料的绝缘体上半导体(semiconductor on insulator；SOI)层。出于示例及简化目的，已自附图省略位于衬底12下方的其它材料及/或层。衬底12可包括例如硅、锗、硅锗、碳化硅，以及基本由具有由式AlX1GaX2InX3AsY1PY2NY3SbY4定义的组成的一种或多种III-V族化合物半导体组成的其它材料，其中，X1、X2、X3、Y1、Y2、Y3及Y4表示相对比例，分别大于或等于0且X1+X2+X3+Y1+Y2+Y3+Y4＝1(1是总的相对摩尔量)。适合用于衬底12的组成的其它材料可包括具有组成ZnA1CdA2SeB1TeB2的II-VI族化合物半导体，其中，A1、A2、B1及B2是相对比例，分别大于或等于零，且A1+A2+B1+B2＝1(1是总的摩尔量)。而且，可应变部分或全部衬底12。
本文中通常以由半导体材料组成的任意结构形式示例说明衬底12，且在一些实施例中，衬底12可形成为单个半导体材料层、用于finFET晶体管中的半导体鳍片，以及/或者通常用于IC产品的制造中的其它半导体材料形式。finFET是指通常自SOI衬底构建的晶体管，其中，位于埋置绝缘体层上的半导体材料被蚀刻成一个或多个鳍式结构，以充当沟道。应当理解，针对以硅层以外的形式实施的衬底12，本文中所述的各种制程步骤可以相同的方式以及/或者在进行稍微修改的情况下实施。另外，衬底12可为由结合并位于埋置绝缘体层上方的半导体材料层组成的单个绝缘体上半导体(SOI)衬底的剩余部分，如本文中其它地方所述。尽管在图1至5中将衬底12示例显示为一个结构或区域的形式，但应当理解，依据本发明的制程可使用任意可想到的数目的衬底12。
结构10可包括直接位于衬底12上或内的源/漏区14，其可包括与衬底12相同的半导体材料以及/或者本文中其它地方所述的不同的半导体材料。相对衬底12，源/漏区14还可在其中包括掺杂物材料，例如以相对衬底12的其余部分提供较大的电导率。通过“掺杂”引入的一种或多种“掺杂物”材料通常是指被添加至结构组件以改变其电性属性例如电阻率及/或电导率的外来材料。如本文中所指出，导电材料及/或半导体材料可包括通过用以将材料引入结构的组成的任意当前已知或以后开发的技术引入的掺杂物化合物。因此，图1至5中显示具有不同于衬底12的纹理的源/漏区14，以强调组成上的可选的差别，尽管衬底12与源/漏区14可能是衬底12的连续部分。
各源/漏区14可由衬底12的沟道区15横向隔开，且衬底12可包括位于其上的一种或多种栅极金属16。沟道区15上的栅极金属16可通过侧间隙壁18与源/漏区14及其它组件横向隔开。栅极金属16可由一种或多种导电材料组成，包括但不限于金属、多晶硅等，其通过应用沉积及/或其它的一种或多种当前已知或以后开发的材料形成制程设于衬底沟道区15上方(例如，直接位于衬底15上或通过衬底12上的薄栅极介电层(未显示)与该衬底隔开)。向栅极金属16施加电压偏置可影响沟道区15的电导率，从而可选地使能或禁能衬底的源/漏区14之间的电流流动。
侧间隙壁18可被设为例如通过沉积、热生长等横向邻近栅极金属16形成的一个或多个绝缘材料体，且可包括形成于栅极金属16上或与其相邻的材料及/或其它结构，以将栅极金属16与结构10的其它组件电性及物理绝缘。在一个示例实施例中，侧间隙壁18可被设为二氧化硅(SiO2)区，其中包括或不包括氮化物。在一些情况下，可使用具有较高介电常数的其它类型绝缘体(例如，包括氧化物及/或硅酸盐的基于铪(Hf)的介电质)来形成侧间隙壁18。一般来说，本文中所述的侧间隙壁18及/或其它电性绝缘材料可由任意绝缘材料组成，例如SiO2或具有高介电常数的介电质，该介电常数可例如高于3.9。适于侧间隙壁18的组成的材料可包括例如二氧化硅(SiO2)、氮化硅(SiN)、氧化铪(HfO2)、氧化铝(Al2O3)、氧化钇(Y2O3)、氧化钽(Ta2O5)、二氧化钛(TiO2)、氧化镨(Pr2O3)、氧化锆(ZrO2)、氧化铒(ErOx)以及具有类似属性的其它当前已知或以后开发的材料。在任何情况下，栅极金属16与侧间隙壁18可一起形成栅极堆叠结构(也就是“金属栅极堆叠”)，其中，栅极金属16通过侧间隙壁18与上方或相邻元件隔开。栅极金属16可充当自依据本发明的制程所生产的晶体管的栅极端子。
本发明的实施例中的结构10可包括或直接位于源/漏硅化物20区下方。源漏硅化物20可通过使用任意当前已知或以后开发的技术形成，例如，执行原位预清洗，并在源/漏区14上沉积金属例如钛(Ti)、镍(Ni)、钴(Co)、钼(Mo)等。接着，可退火该沉积金属，以使该金属与源/漏区14反应。该沉积金属的任意未反应部分可例如通过额外的蚀刻移除。与源/漏区14的其余部分相比，所得的源/漏硅化物20在该退火之后因其中具有导电金属而可具有较高的电导率。源/漏硅化物20可同时提供自形成于其上的接触至多个半导体元件(例如，衬底12、源/漏区14，以及/或者栅极金属16)的电性连接。栅极金属16与源/漏硅化物20可被共同标识为结构10的“导电区”。
在结构10上(例如在侧间隙壁18、源/漏硅化物20等的上表面上)可形成层级间介电(inter-level dielectric；ILD)材料22。ILD材料22可将源/漏区14、栅极金属16、侧间隙壁18以及/或者源漏硅化物20与形成于其上的材料例如在BEOL制程期间形成于IC结构10上的金属层级层物理及电性隔开。另外，ILD材料22可由与本文中关于侧间隙壁18所述相同或类似的绝缘材料的其中一种或多种组成，以及/或者可包括其它电性绝缘材料。更具体地说，ILD材料22可由例如氧化硅(SiO2)或非晶硅组成。用作ILD材料22的其它绝缘体材料可包括例如氮化硅(Si3N4)，氟化SiO2(FSG)，氢化碳氧化硅(SiCOH)，多孔SiCOH、硼-磷-硅酸盐玻璃(BPSG)，倍半硅氧烷，近无摩擦碳，包括硅、碳、氧及/或氢原子的碳(C)掺杂氧化物(也就是有机硅酸盐)，热固性聚芳醚，SiLK(可从陶氏化学公司获得的一种聚芳醚)，可从JSR公司获得的旋涂含硅碳聚合物材料，其它低介电常数(<3.9)材料，或其层。接着，可移除ILD材料22及其它材料的部分以形成接触开口24，可如本文中所述在其中形成一个或多个导电接触。各接触开口24可暴露源漏区14(例如在源/漏硅化物20处)及/或栅极金属16的上表面。
请参照图2，在各开口24内形成任意导电材料之前，本发明的实施例可选择性地包括用氮等离子体处理开口24中的一组暴露侧壁25。向暴露侧壁25施加氮等离子体可促进各开口24中所形成的颗粒扩散进入ILD材料22中，如本文中其它地方所述。例如，向暴露侧壁25施加氮等离子体可通过仅在其外表面处的极薄的ILD材料层22内形成氮及/或氮化物颗粒来改变暴露侧壁25处的ILD材料22的组成。在一个示例实施例中，经处理后，ILD材料22可包括自其外表面达到最多约5纳米厚的氮及/或氮化物化合物，而ILD材料22的其余部分未改变。用氮等离子体处理暴露侧壁25的示例制程可包括例如将结构10及ILD材料22浸于等离子体(也就是离子化气体)中，如图2中的虚箭头所示。本文中所使用的等离子体是指具有放电的离子化气体形式，其以约相等浓度的离子与电子为特征。在该浸入期间所实施的该等离子体可在功率源的帮助下产生，例如该等离子体中的氮离子与暴露侧壁25反应并处理该暴露侧壁。在一些实施例中，可省略用等离子体对暴露侧壁25的该处理。
请参照图3，本发明的实施例可包括在ILD材料22上及接触开口24内(图1至2)形成掺杂金属层(“掺杂层”)26。在形成以后，掺杂层26可接触及/或直接位于源/漏区14、栅极金属16及/或源/漏硅化物20上方。掺杂层26可包括一种或多种金属，其可例如通过沉积形成。本文中所使用的术语“沉积”通常指适于沉积掺杂层26或其它材料的任意当前已知或以后开发的技术，包括但不限于例如：化学气相沉积(chemical vapor deposition；CVD)、低压CVD(low-pressure CVD；LPCVD)、等离子体增强型CVD(plasma-enhanced CVD；PECVD)、半大气压CVD(semi-atmosphere CVD；SACVD)及高密度等离子体CVD(high density plasmaCVD；HDPCVD)、快速加热CVD(rapid thermal CVD；RTCVD)、超高真空CVD(ultra-highvacuum CVD；UHVCVD)、限制反应处理CVD(limited reaction processing CVD；LRPCVD)、金属有机CVD(metalorganic CVD；MOCVD)、溅镀沉积、离子束沉积、电子束沉积、激光辅助沉积、热氧化、热氮化、旋涂方法、物理气相沉积(physical vapor deposition；PVD)、原子层沉积(atomic layer deposition；ALD)、化学氧化、分子束外延(molecular beam epitaxy；MBE)、镀覆，以及/或者蒸镀。
掺杂层26可在其中包括一种或多种金属化合物，且在各种实施例中可包括用第二金属化合物(“第二金属”)掺杂的第一金属化合物(“第一金属”)。在形成于ILD材料22上以后，掺杂层26可经掺杂以原位地在其中包括该第一及第二金属，或者替代地，在结构10上设置该掺杂材料之前，可在独立的制程中掺杂掺杂层26。例如，掺杂层26可通过使用其中包括两种金属化合物的单一前驱体材料(例如脒基材料)形成，其可在单个制程中沉积于结构10上。在一个示例实施中，掺杂层26可主要包括原子浓度为例如掺杂层26的总质量的至少约百分之九十五的钴(Co)。掺杂层26的该第二金属可包括例如锰(Mn)以及/或者在施热的情况下可自掺杂层26扩散至其它材料(例如，绝缘体如氧化物)的其它金属。该第二金属可以相对该第一金属显著较低的浓度设于掺杂层26中，且可代表掺杂层26的总质量的最多约百分之五。因此，掺杂层26的该第二金属相对该第一金属可充当掺杂物。作为替代例子，掺杂层26可包括具有类似属性及/或能力以扩散进入或与ILD材料22反应的两种不同金属，例如钛掺杂铝，以及/或者具有类似物理属性的其它金属。一般来说，掺杂物26中的该第一与第二金属可彼此不同。若掺杂层26包括钴，则用氮等离子体处理ILD材料22(如图2中所示)可使钴更容易地形成于ILD材料22上。若不用氮等离子体处理ILD材料22，则可替代地在ILD材料22上形成一个或多个阻挡层(未显示)，以使钴形成于其上。在任何情况下，例如通过沉积以及/或者其它当前已知或以后开发的在结构上形成金属化合物的制程，在ILD材料22上及/或开口24内可形成掺杂层26。掺杂层26可充当用以形成如本文中所述的至源/漏区14、栅极金属16及/或源/漏硅化物20的导电接触的初始金属材料。
请一并参照图3及4，本发明的实施例可包括处理掺杂层26以改变其电性属性并形成新的材料。尤其，掺杂层26可经退火(例如在约300与600摄氏度之间的温度下)以使掺杂层26中的该第二金属扩散进入ILD材料22中。在该退火以后，掺杂层26的未扩散部分(包括例如该退火后的第一金属)可成为至下方导电区例如源/漏区14、栅极金属16、源/漏硅化物20等的接触28。该第二金属向ILD材料22中的该扩散还可在ILD材料22的外表面上以及直接在ILD材料22的其余部分与接触28之间形成界面衬里30。掺杂层26内的该第二金属可能不显著扩散进入一些材料中，例如因为它们的材料组成不包括能够与该第二金属化学反应的物质(例如氧化物)。如本文中所述使用并处理掺杂层26的技术优点可包括例如仅在ILD材料22上形成界面衬里30，而不在暴露导电表面(例如，源/漏区14、栅极金属16、源/漏硅化物20)上形成界面衬里30。若ILD材料22包括二氧化硅，则该退火可使该第二金属扩散进入ILD材料22中，其中，该第二金属与该二氧化硅反应形成硅酸盐化合物。在该第二金属包括锰的实施例中，在该退火之后，界面材料30可包括硅酸锰，而ILD材料22的其余部分在其中包括氧化硅。在掺杂层26中包括锰可进一步促进界面衬里30的形成，例如因为锰的扩散可由氧化合物(例如ILD材料22内的氧化硅)驱动。
请参照图5，其显示依据本发明的实施例的IC结构32。在退火掺杂层26(图3)以形成接触28及界面衬里30以后，可移除ILD材料22、接触28及/或界面衬里30的部分，以获得其中具有物理隔开的接触28与界面衬里30的IC结构32。一个这样的移除制程可包括例如化学机械抛光(chemical mechanical polishing；CMP)，以使IC结构32的上表面大体位于单个水平面上。本文中要注意，接触28可在其中包括该第一金属，而界面衬里30可在其中包括该第二金属。该第一金属可包括钴(Co)，而该第二金属可包括锰(Mn)，不过本文中其它地方考虑并讨论替代金属。若ILD材料22包括二氧化硅，则界面衬里30可由硅酸锰组成。如图所示，源/漏区14、栅极金属16及源/漏硅化物20的表面可完全或者几乎完全没有界面衬里30，从而使接触28的下表面与晶体管结构34的部分之间的任意交界处都没有界面衬里30。
依据本发明的处理使IC结构32可包括晶体管结构34，其包括如本文中所述的衬底12、源/漏区14、沟道区15以及栅极金属16，包括源/漏硅化物20以在接触28与源/漏区14之间提供进一步的电导率。接触28可位于接触开口24(图1、2)的原始位置内，以使接触28位于源/漏硅化物20及栅极金属28上方，与其电性耦接且/或接触。界面衬里30(其中具有该第二金属)可直接位于接触28与ILD材料22的侧壁25(图2)之间。如本文中所述，在各种IC应用及/或产品中，IC结构32的界面衬里30可替代难熔金属衬里。
上述方法用于集成电路芯片的制造。所得的集成电路芯片可由制造者以原始晶圆形式(也就是说，作为具有多个未封装芯片的单个晶圆)、作为裸芯片，或者以封装形式分配。在后一种情况中，该芯片设于单芯片封装件中(例如塑料承载件，其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如陶瓷承载件，其具有单面或双面互连或嵌埋互连)。在任何情况下，接着将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成，作为(a)中间产品例如母板的部分，或者作为(b)最终产品的部分。
本文中所使用的术语仅是出于说明特定实施例的目的，并非意图限制本发明。除非上下文中另外明确指出，否则本文中所使用的单数形式“一个”以及“该”也意图包括复数形式。另外，应当理解，术语“包括”用于本说明书中时表明所述特征、整体、步骤、操作、元件和/或组件的存在，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件，和/或其群组。“可选的”或“可选地”是指后续所述事件或情况可能发生或者可能不发生，且该说明包括事件发生的情况以及其不发生的情况。
这里在说明书及权利要求书各处所使用的近似语言可用以修饰任意量化表达，可允许该量化表达变动而不会导致与其相关的基本功能的改变。因此，由一个或多个术语例如“约”及“大体”修饰的值不限于所指定的精确值。在至少一些情况下，该近似语言可对应用以测量该值的仪器的精度。在这里以及说明书及权利要求书各处，范围限制可组合和/或互换，此类范围被识别并包括包含于其中的所有子范围，除非上下文或语言另外指出。应用于一范围的特定值的“约”适用于两个值，且除非依赖于测量该值的仪器的精度，否则可表示所述值的+/-10％。
权利要求中的所有手段或步骤加功能元素的相应结构、材料、动作及等同物意图包括结合具体请求保护的其它请求保护的元素执行该功能的任意结构、材料或动作。本发明的说明用于示例及说明目的，而非意图详尽无遗或限于所揭露形式的揭露。许多修改及变更将对于本领域的普通技术人员显而易见，而不背离本发明的范围及精神。实施例经选择及说明以最佳解释本发明的原理及实际应用，并使本领域的普通技术人员能够理解本发明针对各种实施例具有适合所考虑的特定应用的各种变更。

Claims (20)

1.一种形成集成电路(IC)结构的方法，该方法包括：
提供结构，该结构包括：
导电区，以及
层级间介电(ILD)材料，位于该导电区上，其中，该ILD材料包括至该导电区的接触开口；
在该接触开口内形成掺杂金属层，以使该掺杂金属层位于该导电区上方，其中，该掺杂金属层包括用第二金属掺杂的第一金属；以及通过退火该掺杂金属层在该ILD材料的该接触开口内形成至该导电区的接触，以使该第二金属扩散进入该ILD材料中，从而直接在该退火掺杂金属层与该ILD材料之间形成界面衬里。
2.如权利要求1所述的方法，其中，该导电区包括晶体管栅极金属或源/漏硅化物的其中之一。
3.如权利要求1所述的方法，其中，退火该第二金属包括使该第二金属自该掺杂金属层扩散进入该ILD材料中以形成该界面衬里，而不扩散进入该导电区中。
4.如权利要求1所述的方法，其中，该第一金属包括钴(Co)。
5.如权利要求4所述的方法，其中，该第二金属包括锰(Mn)。
6.如权利要求1所述的方法，其中，该ILD材料包括氧化硅，以及其中，退火使该氧化硅与该第二金属反应以产生硅酸盐化合物。
7.如权利要求6所述的方法，其中，该硅酸盐化合物包括硅酸锰。
8.如权利要求1所述的方法，还包括在形成该掺杂金属层之前，用氮等离子体处理该接触开口的侧壁。
9.如权利要求1所述的方法，还包括在该退火以后，平坦化该掺杂金属层及该ILD材料的上表面。
10.如权利要求1所述的方法，其中，退火发生于约300与600摄氏度之间的温度下。
11.一种形成集成电路(IC)的晶体管结构的方法，该方法包括：
在位于该晶体管结构上方的ILD材料内形成接触开口，其中，形成该接触开口暴露该晶体管结构的源/漏区或栅极金属；
在形成该接触开口以后，在该源/漏区上形成源/漏硅化物；
在该接触开口内形成掺杂金属层，其中，该掺杂金属层包括用第二金属掺杂的第一金属；以及
通过退火该掺杂金属层在该ILD材料的该接触开口内形成至该导电区的接触，以使该第二金属扩散进入该ILD材料中，从而直接在该退火掺杂金属层与该ILD材料之间形成界面衬里。
12.如权利要求11所述的方法，其中，该第一金属包括钴(Co)，以及其中，该第二金属包括锰(Mn)。
13.如权利要求12所述的方法，其中，该ILD材料包括氧化硅，且该退火使该氧化硅化合物与该锰反应以产生硅酸锰。
14.如权利要求11所述的方法，其中，退火该第二金属包括使该第二金属自该掺杂金属层扩散进入该ILD材料中以形成该界面衬里，而该第二金属不扩散进入该晶体管的该栅区及该源/漏硅化物中。
15.如权利要求11所述的方法，还包括在该接触开口中形成该掺杂金属层之前，用氮等离子体处理该接触开口的侧壁。
16.一种集成电路(IC)结构，包括：
晶体管结构，包括：包括源/漏区的衬底，位于该衬底的该源/漏区上的源/漏硅化物，以及位于该衬底上方的栅极金属；
层级间介电(ILD)材料，位于该晶体管结构上，其中，该ILD材料包括至该晶体管结构的该源/漏硅化物或该栅极金属的其中之一的接触开口；
导电接触，位于该接触开口内，以使该导电接触位于该源/漏硅化物或该栅极金属的其中之一的上方并与其电性耦接，其中，该导电接触的材料组成包括第一金属；以及
包括第二金属的界面衬里，直接位于该导电接触与该ILD材料的侧壁之间。
17.如权利要求16所述的IC结构，其中，该第一金属包括钴(Co)。
18.如权利要求17所述的IC结构，其中，该第二金属包括锰(Mn)。
19.如权利要求16所述的IC结构，其中，该ILD材料包括氧化硅，以及其中，该界面衬里包括硅酸锰。
20.如权利要求16所述的IC结构，其中，该导电接触直接位于该源/漏硅化物或该栅极金属的上表面上，从而在该导电接触的下表面与该晶体管结构之间的交界处没有该界面衬里。
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US20180033728A1 (en) 2018-02-01
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