TW201926558A - 半導體裝置的形成方法 - Google Patents

半導體裝置的形成方法 Download PDF

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Publication number
TW201926558A
TW201926558A TW107124087A TW107124087A TW201926558A TW 201926558 A TW201926558 A TW 201926558A TW 107124087 A TW107124087 A TW 107124087A TW 107124087 A TW107124087 A TW 107124087A TW 201926558 A TW201926558 A TW 201926558A
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Taiwan
Prior art keywords
layer
dielectric layer
deposition
gate
opening
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TW107124087A
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English (en)
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周典霈
鄭宇彣
林鈺庭
王俊傑
張根育
白岳青
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台灣積體電路製造股份有限公司
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Publication of TW201926558A publication Critical patent/TW201926558A/zh

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Abstract

本發明實施例一般關於形成連續的黏著層以用於接點插塞的技術。方法包括形成開口,其穿過介電層至基板上的主動區。方法包括沿著開口側壁進行第一電漿處理。方法包括進行原子層沉積製程,以沿著開口側壁形成金屬氮化物層。原子層沉積製程包括多個循環。每一循環包括使前驅物流入,以沿著開口側壁形成金屬單層,以及進行第二電漿處理,以氮處理金屬單層。方法包括沉積導電材料於開口中的金屬氮化物層上,以形成導電結構。

Description

半導體裝置的形成方法
本發明實施例關於半導體裝置,更特別關於導電結構與其形成方法。
半導體積體電路產業已經歷指數成長。積體電路材料與設計中的技術演進,使每一代的積體電路都比前一代的積體電路具有更小且更複雜的電路。在積體電路演進中,功能密度(比如單位晶片面積所含的內連線裝置數目)通常隨著幾何尺寸(比如製程所能產生的最小構件或線路)縮小而增加。製程尺寸縮小有利於增加產能並降低相關成本。不過尺寸縮小亦可能出現較大尺寸的前幾代製程中不存在的挑戰。
本發明一實施例提供之半導體裝置的形成方法,包括:形成開口,穿過介電層至基板上的主動區;沿著開口的側壁進行第一電漿處理;進行原子層沉積製程,以沿著開口的側壁形成金屬氮化物層,其中原子層沉積製程包括多個循環,且每一循環包括:使前驅物流入以沿著開口的側壁形成金屬單層;以及進行第二電漿處理,以氮處理金屬單層;以及沉積導電材料於開口中的金屬氮化物層上,以形成導電結構。
A-A、B-B‧‧‧剖面
D1‧‧‧頂部尺寸
D2‧‧‧底部尺寸
40‧‧‧鰭狀場效電晶體
42‧‧‧基板
44、78‧‧‧隔離區
46a、46b、74‧‧‧鰭狀物
48a、48b、122‧‧‧閘極介電層
50a、50b、126‧‧‧閘極
52a、52b、52c、52d、52e、52f‧‧‧源極/汲極區
70‧‧‧半導體基板
72、84、128‧‧‧遮罩
76‧‧‧溝槽
80、120‧‧‧界面介電層
82‧‧‧虛置閘極
86‧‧‧閘極間隔物
90‧‧‧凹陷
92‧‧‧磊晶源極/汲極區
96‧‧‧接點蝕刻停止層
100‧‧‧第一層間介電層
102、132‧‧‧開口
106‧‧‧預處理區
108‧‧‧氮化鈦層
110‧‧‧導電材料
112‧‧‧介電層
114‧‧‧導電結構
124‧‧‧順應層
130‧‧‧第二層間介電層
1400‧‧‧系統
1405‧‧‧加熱器
1406‧‧‧外側區
1407‧‧‧內側區
1410‧‧‧噴灑頭
1415‧‧‧遠端電漿源
1420‧‧‧氣體源
1602‧‧‧第一圖表
1604‧‧‧第二圖表
1606‧‧‧第三圖表
1612、1622、1632‧‧‧第一濃度輪廓
1614、1624、1634‧‧‧第二濃度輪廓
1616、1626、1636‧‧‧第三濃度輪廓
第1圖係一些實施例中,簡化的鰭狀場效電晶體之一例的三維圖。
第2A、2B、3A、3B、4A、4B、5A、5B、6A、6B、7A、7B、8A、8B、9A、9B、10A、10B、11A、11B、12A、12B、13A、與13B圖係一些實施例中,形成一或多個鰭狀場效電晶體的例示性製程中的中間階段其剖視圖。
第14A圖係一些實施例中,形成一或多個鰭狀場效電晶體的例示性製程的中間階段中,用以形成預處理區與氮化鈦層於接點孔中的例示性系統。
第14B圖係一些實施例中,用於第14A圖所示的系統之雙區加熱器的例子。
第15A、15B、16A、16B、17A、與17B圖係一些實施例中,形成一或多個鰭狀場效電晶體的例示性製程之中間階段的剖視圖。
第16C圖係一些實施例中,不同結構中的元素濃度圖。
第18A、18B、19A、19B、20A、20B、21A、與21B圖係一些實施例中,形成半導體裝置的另一例示性製程之中間階段的剖視圖。
下述揭露內容提供許多不同實施例或實例以實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸,或兩者之間隔有其他額外構件而非直接接觸。此外,本發明的多個實例可採用重複標號及/或 符號使說明簡化及明確,但這些重複不代表多種實施例中相同標號的元件之間具有相同的對應關係。
此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。元件亦可轉動90°或其他角度,因此方向性用語僅用以說明圖示中的方向。
一般而言,本發明提供的實施例關於導電結構如金屬接點,以及導電結構的形成方法。在一些例子中,形成導電插塞。一些例子中用以形成接點插塞的製程關於進行預處理,且預處理包含氮電漿;形成順應性(如連續性)的黏著層如氮化鈦黏著層;以及沉積接點插塞充填材料,比如具有少量鈷空洞缺陷與低接點電阻的鈷。
用以形成連續氮化鈦黏著層與接點插塞的例示性技術,在此處將以鰭狀場效電晶體進行說明。然而本發明實施例形成接點插塞的方法亦可實施於平面電晶體及/或其他半導體裝置。一些例子為用於N5或N7節點中14nm的接點孔。此外亦說明鰭狀場效電晶體其形成方法的中間階段。此處所述的一些實施例中,鰭狀場效電晶體的形成方法採用置換閘極製程。在其他例子中,可採用閘極優先製程。下述說明例示性方法與結構的一些變化。本技術領域中具有通常知識者應理解,其他調整可屬於其他實施例的範疇。雖然實施例的方法以特定順序說明,但多種其他實施例的方法可由任何邏輯性的順序進行, 並可包含較少或較多的下述步驟。
此處所述的例示性實施例說明在前端製程及/或中段製程中,形成導電結構以用於電晶體的方法。本發明一些實施例的實施方法可用於其他製程如末端製程及/或其他裝置。下述內容將說明例示性方法與結構的一些變化。本技術領域中具有通常知識者應理解,其他變化屬於其他實施例的範疇。在一些圖式中,省略構件或結構的一些標號,可避免遮住圖式中的其他構件以利繪圖。
第1圖係一例中,簡化的鰭狀場效電晶體40其三維圖。第1圖未圖示或說明的其他實施例,可由下述圖式或說明得知。舉例來說,第1圖中的結構可電性連接或耦接,以操作如單一電晶體或多個電晶體(比如四個電晶體)。
鰭狀場效電晶體40包含鰭狀物46a與46b於基板42上。基板42包含隔離區44,且鰭狀物46a與46b各自由相鄰的隔離區44之間向上凸起。閘極介電層48a與48b沿著鰭狀物46a與46b的側壁,並位於鰭狀物46a與46b的上表面上。閘極50a與50b分別位於閘極介電層48a與48b上。源極/汲極區52a至52f位於鰭狀物46a與46b的個別區域中。源極/汲極區52a與52b相對於閘極介電層48a與閘極50a,位於鰭狀物46a的兩側區域中。源極/汲極區52b與52c相對於閘極介電層48b與閘極50b,位於鰭狀物46a的兩側區域中。源極/汲極區52d與52e相對於閘極介電層48a與閘極50a,位於鰭狀物46b的兩側區域中。源極/汲極區52e與52f相對於閘極介電層48b與閘極50b,位於鰭狀物46b的兩側區域中。
第1圖係顯示用於後續圖式的參考剖面。剖面A-A為沿著鰭狀物46a中源極/汲極區52a-c之間的通道區之平面。剖面B-B為垂直於剖面A-A的平面,並橫越鰭狀物46a中的源極/汲極區52a及鰭狀物46b中的源極/汲極區52d。後續圖式依據這些參考剖面以清楚說明。
第2A與2B圖至第13A與13B圖以及第15A與15B圖至第21A與21B圖為一些實施例中,形成一或多個鰭狀場效電晶體的例示性製程中的中間階段其剖視圖。在第2A與2B至第13A與13B圖以及第15A與15B圖至第21A與21B圖中,圖式末尾為「A」的剖視圖沿著與第1圖中剖面A-A類似的剖面,而圖式末尾為「B」的剖視圖沿著與第1圖中剖面B-B類似的剖面。
第2A與2B圖至第13A與13B圖以及第15A與15B圖至第17A與17B圖係一些實施例中,形成半導體裝置的例示性製程的中間階段中,個別中間結構的剖視圖。第2A與2B圖至第9A與9B圖可實施此處所述的閘極優先製程與置換閘極製程。第10A與10B圖至第13A與13B圖以及第15A與15B圖至第17A與17B圖為此處所述的閘極優先製程之其他實施例。第18A與18B圖至第21A與21B圖係此處所述的置換閘極製程之其他實施例。
第2A與2B圖顯示半導體基板70。半導體基板70可為或可包含基體半導體基板、絕緣層上半導體基板、或類似物,其可未摻雜或摻雜有p型或n型摻質。一般而言,絕緣層上半導體基板包含半導體材料層形成於絕緣層上。舉例來說,絕緣層可為埋置氧化物層、氧化矽層、或類似物。絕緣層提供於 基板上,而基板通常為矽基板或玻璃基板。亦可採用其他基板如多層基板或組成漸變基板。在一些實施例中,半導體基板的半導體材料可包含矽、鍺、半導體化合物(如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、或銻化銦)、半導體合金(如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、或磷砷化鎵銦)、或上述之組合。
如第3A與3B圖所示,形成鰭狀物74於半導體基板70中。在例示性的例子中,遮罩72(如硬遮罩)可用以形成鰭狀物74。舉例來說,沉積一或多個遮罩層於半導體基板70上,接著將一或多個遮罩層圖案化成遮罩72。在一些例子中,一或多個遮罩層可包含或可為氮化矽、氮氧化矽、碳化矽、氮碳化矽、類似物、或上述之組合,且其沉積方法可為化學氣相沉積、物理氣相沉積、原子層沉積、或另一沉積技術。一或多個遮罩層的圖案化方法可採用光微影。舉例來說,可形成光阻於一或多個遮罩層上,其形成方法可為旋轉塗佈。接著採用適當光罩與光源曝光光阻以圖案化光阻。接著移除光阻的曝光部份或未曝光部份,端視採用的光阻為正型或負型。接著可將光阻圖案轉移至一或多個遮罩層以形成遮罩72,且轉移方法可採用合適的蝕刻製程。蝕刻製程可包含反應性離子蝕刻、中性束蝕刻、類似方法、或上述之組合。蝕刻可為非等向。舉例來說,接著可採用灰化製程或濕式剝除製程移除光阻。
採用遮罩72並蝕刻半導體基板70,可形成溝槽76於相鄰一對的鰭狀物74之間,因此鰭狀物74可自半導體基板70凸起。蝕刻製程可包含反應性離子蝕刻、中性束蝕刻、類似方 法、或上述之組合。蝕刻可為非等向。
如第4A與4B圖所示,形成每一隔離區78於對應的溝槽76中。隔離區78可包含或可為絕緣材料如氧化物(如氧化矽)、氮化物、類似物、或上述之組合,且絕緣材料的形成方法可為高密度電漿化學氣相沉積、可流動的化學氣相沉積(比如在遠端電漿系統中沉積化學氣相沉積為主的材料,之後烘烤材料使其轉變為另一材料如氧化物)、類似方法、或上述之組合。此外亦可採用任何可接受的製程形成的其他絕緣材料。在例示的實施例中,隔離區78包含氧化矽,且其形成方法為可流動的化學氣相沉積製程。平坦化製程如化學機械研磨可移除任何多餘的絕緣材料與任何殘留的遮罩72,使絕緣材料的上表面與鰭狀物74的上表面共平面。接著可使絕緣材料凹陷以形成隔離區78。絕緣材料凹陷後,鰭狀物74可自相鄰的隔離區78之間凸起,其可至少部份地將鰭狀物74定義為半導體基板70上的主動區。絕緣材料的凹陷方法可採用可接受的蝕刻製程,比如對絕緣材料具有選擇性的蝕刻製程。舉例來說,可採用濕蝕刻或乾蝕刻。此外,隔離區78的上表面可如圖示的平坦表面、凸面表面、凹面表面(如碟狀)、或上述之組合,且其可來自於蝕刻製程。
本技術領域中具有通常知識者應理解,第2A與2B圖至第4A與4B圖所述製程,僅為如何形成鰭狀物74的例子之一。在其他實施例中,可形成介電層於半導體基板70的上表面上;蝕刻介電層以形成穿過介電層的溝槽;可磊晶成長同質磊晶結構於溝槽中;以及可使介電層凹陷,讓同質磊晶結構自介 電層凸起以形成鰭狀物。在其他實施例中,異質磊晶結構可用於鰭狀物。舉例來說,可使鰭狀物74凹陷(比如在平坦化隔離區78的絕緣材料之後,以及使絕緣層凹陷之前),並磊晶成長不同於鰭狀物74的材料至凹陷處。在其他實施例中,可形成介電層於半導體基板70的上表面上;蝕刻介電層以形成穿過介電層的溝槽;可磊晶成長不同於半導體基板70的異質磊晶結構於凹陷中;以及使介電層凹陷,讓異質磊晶結構自介電層凸起以形成鰭狀物。在一些實施例中,磊晶成長單質磊晶或異質磊晶結構,且可在成長時原位摻雜成長的材料,其可省略先佈植鰭狀物的步驟,不過原位摻雜與佈植摻雜亦可一起使用。同樣地,用於n型裝置與用於p型裝置的磊晶成長材料不同可具有優勢。在多種實施例中,鰭狀物74可包含矽、矽鍺(SixGe1-x,其中x可介於約0至1之間)、碳化矽、純鍺或實質上純鍺、III-V族半導體化合物、II-VI族半導體化合物、或類似物。舉例來說,用於形成III-V族半導體化合物的材料包含砷化銦、砷化鋁、砷化鎵、磷化銦、氮化鎵、砷化銦鎵、砷化銦鋁、銻化鎵、銻化鋁、磷化鋁、磷化鎵、或類似物。
如第5A與5B圖所示,形成虛置閘極堆疊於鰭狀物74上。每一虛置閘極堆疊包含界面介電層80、虛置閘極82、與遮罩84。界面介電層80、虛置閘極82、與遮罩84的形成方法可為依序沉積個別的層狀物,並圖案化這些層狀物。舉例來說,用於界面介電層80的層狀物可包含或可為氧化矽、氮化矽、類似物、或上述之多層,且其形成方法可為熱成長或沉積(如電漿增強化學氣相沉積、原子層沉積、或另一沉積技術)。用於 虛置閘極82的層狀物可包含或可為矽(如多晶矽)或另一材料,且其沉積方法可為化學氣相沉積、物理氣相沉積、或另一沉積技術。用於遮罩84的層狀物可包含或可為氮化矽、氮氧化矽、氮碳化矽、類似物、或上述之組合,且其沉積方法可為化學氣相沉積、物理氣相沉積、原子層沉積、或另一沉積技術。舉例來說,接著可圖案化用於遮罩84、虛置閘極82、與界面介電層80的層狀物,以形成用於每一閘極堆疊的遮罩84、虛置閘極82、與界面介電層80,且圖案化的方法可採用前述第3A與3B圖所述的光微影或一或多道蝕刻製程。
在例示性的例子中,可實施虛置閘極堆疊以用於置換閘極製程。在其他例子中,可實施閘極優先製程,其採用的閘極堆疊可包含閘極介電層以取代界面介電層80,並採用閘極取代虛置閘極82。在一些閘極優先製程中,形成閘極堆疊的製程與材料與前述形成虛置閘極堆疊的製程與材料類似,不過其他實施例可實施其他製程或材料。舉例來說,閘極介電層可包含或可為高介電常數介電材料,比如介電常數大於約7.0的介電材料,其可包含鉿、鋁、鋯、鑭、鎂、鋇、鈦、或鉛的金屬氧化物或矽酸鹽、上述之多層、或上述之組合。閘極介電層的沉積方法亦可為分子束沉積、原子層沉積、電漿增強化學氣相沉積、或另一沉積技術。閘極亦可包含或可為含金屬材料如氮化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、上述之多層、或上述之組合。
如第6A與6B圖所示,形成閘極間隔物86。閘極間隔物86沿著虛置閘極堆疊的側壁(如界面介電層80、虛置閘極 82、與遮罩84的側壁)。舉例來說,閘極間隔物86的形成方法可為順應性地沉積用於閘極間隔物86的一或多個層狀物,並非等向蝕刻一或多個層狀物。用於閘極間隔物86的一或多個閘極間隔物86可包含或可為氮化矽、氮氧化矽、氮碳化矽、類似物、上述之多層、或上述之組合,且蝕刻製程包含反應性離子蝕刻、中性束蝕刻、或另一蝕刻製程。
如第7A與7B圖所示,形成凹陷90以用於源極/汲極區。如圖所示,凹陷90形成於鰭狀物74中且位於虛置閘極堆疊的兩側上。凹陷步驟可為蝕刻製程。蝕刻製程可為等向或非等向,且亦可對半導體基板70的一或多個結晶平面具有選擇性。因此凹陷90可具有多種剖面輪廓,端視實施的蝕刻製程而定。蝕刻製程可為乾蝕刻如反應性離子蝕刻、中子束蝕刻、或類似方法,或者濕蝕刻如採用氫氧化四甲基銨、氫氧化銨、或另一蝕刻劑的蝕刻方法。
如第8A與8B圖所示,形成磊晶源極/汲極區92於凹陷90中。磊晶源極/汲極區92可包含或可為矽鍺(如SixGe1-x,其中可介於約0至1之間),碳化矽、磷化矽、純鍺或實質上純鍺、III-V族半導體化合物、II-VI族半導體化合物、或類似物。舉例來說,用於形成III-V族半導體化合物的材料包含砷化銦、砷化鋁、砷化鎵、磷化銦、氮化鎵、砷化銦鎵、砷化銦鋁、銻化鎵、銻化鋁、磷化鎵、或類似物。磊晶源極/汲極區92形成於凹陷90中的方法可為磊晶成長材料於凹陷90中,且磊晶成長的方法可為有機金屬化學氣相沉積、分子束磊晶、液相磊晶、氣相磊晶、選擇性磊晶成長、類似方法、或上述之組合。如第8A 與8B圖所示,由於隔離區78的阻擋效果,磊晶源極/汲極區92先垂直地成長於凹陷中,而不會水平地成長。在完全填滿凹陷90之後,磊晶源極/汲極區92可垂直地與水平地成長以形成晶面,且晶面可對應半導體基板70的結晶平面。在一些例子中,p型裝置與n型裝置所用的磊晶源極/汲極區可採用不同材料。 在凹陷化或磊晶成長時,可採用合適遮罩以形成用於不同裝置的不同材料。
本技術領域中具有通常知識者亦應理解,可省略第7A與7B圖至第8A與8B圖的凹陷製程與磊晶成長,而源極/汲極區的形成方法可為佈植摻質到鰭狀物74中。一些例子實施磊晶源極/汲極區92,亦仍可摻雜磊晶源極/汲極區92,比如在磊晶成長時原位摻雜及/或在磊晶成長後佈植摻質到磊晶源極/汲極區92中。舉例來說,摻質的例子可包含或可為用於p型裝置的硼,以及用於n型裝置的磷或砷,但亦可採用其他摻質。磊晶源極/汲極區92(或其他源極/汲極區)的摻質濃度可介於約1019cm-3至約1021cm-3之間。因此,可由摻雜(如佈植及/或磊晶成長時的原位摻雜,若合適的話)及/或磊晶成長定義源極/汲極區(若合適的話),其可進一步定義主動區於源極/汲極區定義處。
如第9A與9B圖所示,形成接點蝕刻停止層96。一般而言,蝕刻停止層在形成接點或通孔時,可提供停止蝕刻製程的機制。蝕刻停止層之組成可為介電材料,且其蝕刻選擇性不同於相鄰的層狀物或構件的蝕刻選擇率。順應性地沉積接點蝕刻停止層96於磊晶源極/汲極區92的上表面、閘極間隔物的 側壁與上表面、遮罩84的上表面、與隔離區78的上表面上。接點蝕刻停止層96可包含或可為氮化矽、氮碳化矽、碳氧化矽、氮化碳、類似物、或上述之組合,且其沉積方法可為化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、或另一沉積技術。
如第10A與10B圖所示,形成第一層間介電層100於接點蝕刻停止層96上。第一層間介電層100可包含或可為氧化矽、低介電常數介電材料(如介電常數低於氧化矽的材料)、氮氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、有機矽酸鹽玻璃、碳氧化矽、旋轉塗佈玻璃、旋轉塗佈聚合物、矽碳材料、上述之化合物、上述之複合物、類似物、或上述之組合。層間介電層的沉積方法可為旋轉塗佈、化學氣相沉積、可流動的化學氣相沉積、電漿增強化學氣相沉積、或另一沉積技術。
在沉積第一層間介電層100後,可採用平坦化製程如化學機械研磨以平坦化第一層間介電層100。在閘極優先製程中,第一層間介電層100的上表面可高於接點蝕刻停止層96與閘極堆疊的上側部份。因此接點蝕刻停止層96的上側部份可保留於閘極堆疊上。
如第11A與11B圖所示的例子,形成開口102穿過第一層間介電層100與接點蝕刻停止層96至源極/汲極區92並露出至少部份的源極/汲極區92。舉例來說,圖案化第一層間介電層100與接點蝕刻停止層96以形成開口102的方法,可採用光微影及一或多道蝕刻製程。
如第11A圖所示的一些例子中,開口102的底部尺 寸D2可小於14nm,而其頂部尺寸D1可小於17nm。開口102的深度可小於60nm。開口102的深寬比(比如深度對頂部尺寸的比例)可大於3。
在一些實施例中,導電結構可形成於磊晶源極/汲極區92上的開口102中。導電結構可稱作接點、插塞、接點插塞、或類似物。接點插塞的形成方法可包括形成導電材料、阻障層、黏著層、矽化物區、或類似物。一些實施例將詳述於下,其提供製程與結構以用於形成接點插塞。製程可包含形成連續氮化鈦層以用於鈷插塞。製程可關於進行氮化物電漿預處理,以及沉積氮化鈦的原子層沉積。
如第12A與12B圖所示,係第一層間介電層100與磊晶源極/汲極區92的氮預處理,其可用於後續形成的黏著層如連續的金屬氮化物層(如氮化鈦)。依據一些實施例,在進行原子層沉積以沉積金屬氮化物層之前,可以處理氣體預處理開口102的側壁表面與下表面。在一些例子中,可進行氮化物電漿預處理。預處理可置換甚至移除開口102中表面的損傷。舉例來說,預處理製程可移除氧化物以清潔開口102中的表面。在一些例子中,預處理氣體可為或可包含氦、氬、或另一合適氣體。預處理可形成氮的預處理區106。在一些例子中,預處理的自由基(如氮自由基)穿過開口102的表面以形成氮的預處理區106,其位於開口102之底部下及/或超出開口102的側壁之深度或厚度,可介於約1Å至約50Å之間。預處理可為等向。預處理可為遠端電漿處理。在一些例子中,預處理所用的遠端電漿功率可介於約1000W至約4000W之間。在一些例子中,處理時 間可介於約60秒至約150秒之間。在一些例子中,處理壓力可介於約0.1Torr至約1Torr之間。在一些例子中,處理氣體的流速可介於約1000sccm至約3000sccm之間。
氮預處理將氮併入開口102的側壁(包含第一層間介電層100如含氧化矽的介電層)中,並將氮併入開口102的下表面(包含磊晶源極/汲極區92)中。如此一來,在進行氮化鈦的原子層沉積時,由於半導體基板70與連續的氮化鈦層108均具有氮元素,處理至基板中的氮有助於橋接至原子層沉積的氮化鈦中的氮,因此可作為強大的黏著層。在此例中,氮化鈦層可更有效地黏著至開口102中的側壁(如第一層間介電層100)與下表面,以形成更連續的氮化鈦層。
如第13A與13B圖所示,形成連續金屬氮化物層(如氮化鈦層108)於開口102中的預處理區106上。連續的氮化鈦層108可形成於預處理區106上,且其形成方法可採用此處提供的技術以進行原子層沉積,可確保連續且順應性地沉積金屬的氮化物層如氮化鈦層108,以減少填充接點時導致接點插塞中缺陷的空洞。在一些例子中,在原子層沉積製程時可形成金屬如鈦於開口102中的磊晶源極/汲極區92上,且金屬如鈦可與磊晶源極/汲極區92反應形成矽化物區,比如磊晶源極/汲極區92上的鈦矽化物。
連續的氮化鈦層108其形成方法可採用原子層沉積技術。氮化鈦層的原子層沉積製程可包含多個循環。每一循環包含沉積鈦膜與氮處理,以形成氮化鈦層108。舉例來說,每一循環可沉積2Å至5Å的氮化鈦膜於開口102中。如此一來, 在3至15個循環之後可形成約15Å至約20Å厚的氮化鈦層108。原子層沉積製程採用前驅物以沉積鈦單層。在一些實施例中,四(二甲基胺基)鈦前驅物可用於形成鈦單層。在一些例子中,鈦單層可與磊晶源極/汲極區92反應形成矽化物區(如鈦矽化物)於磊晶源極/汲極區92上。鈦單層可經氮(如氮化物)處理以形成氮化鈦。氮處理可採用前述的遠端電漿處理。
在一些例子中,遠端電漿功率可介於約1000W至約4000W之間。在一些例子中,氮處理時間與鈦沉積時間之間的比例可介於約0.3至約1.5之間。在一些例子中,原子層沉積製程腔室中進行沉積時的壓力,可介於約3Torr至約6Torr之間,而半導體基板70上的背側壓力可介於約0.2Torr至約2Torr之間。在一些例子中,連續的氮化鈦層108的階梯覆蓋率(開口102中的側壁上的氮化鈦層108其厚度,與上表面上的氮化鈦層108其厚度之間的比例)可介於約0.7至約1之間。
第14A圖係用於進行預處理製程以形成預處理區106,以及用於進行氮化鈦的原子層沉積製程以形成連續的氮化鈦層108之例示性的系統1400。如第14A圖所示,系統1400包含加熱器1405、噴灑頭1410、遠端電漿源1415、與氣體源1420。加熱器1405的上側表面可支撐半導體基板70。在加熱器1405與噴灑頭1410之間可具有空間。在一些例子中,上述空間可介於約250密耳(mil)至450密耳之間。遠端電漿源1415可用於使等向性的氮電漿流入並處理半導體基板70上的表面,以預處理及/或沉積連續的氮化鈦層108。氣體源1420可用於進行沉積。在一些例子中,氣體源1420可使前驅物(如四(二甲基胺基) 鈦)流入以形成用於連續的氮化鈦層108之鈦單層。在一些例子中,氣體源1420可採用氦承載氣體以輸送前驅物。氦氣流速可介於300sccm至900sccm之間。在一些例子中,前驅物為四(二甲基胺基)鈦。在每一循環結束時可清除前驅物。在原子層沉積結束時,可將原子層沉積腔室抽空至基礎壓力。
在一些實施例中,在預處理及/或氮化鈦的原子層沉積製程時可採用加熱器1405。如第14B圖所示,加熱器1405可為雙區加熱器,其具有外側區1406與內側區1407。外側區1406與內側區1407之間的功率比例可介於約0.7至約1之間。可分開控制外側區1406與內側區1407。在一些例子中,在預處理及/或氮化鈦的原子層沉積製程中,加熱器1405的溫度介於約300℃至約380℃之間。加熱器1405可用於控制氮化鈦層的厚度與階梯覆蓋率。舉例來說,較高溫度可增加沉積速率,而較低溫度可降低沉積速率。在一些例子中,加熱半導體基板70的時間可為約15秒或更多。在原子層沉積循環之前,可另外進行加熱步驟(而非原子層沉積循環的一部份)。在一些實施例中,不同深寬比可採用不同的參數範圍,比如處理功率、壓力、流速、或類似參數的範圍。
如第15A與15B圖所示,形成導電材料110以填入開口102。導電材料110可沉積於連續的氮化鈦層108上並填入開口102。導電材料110可為鈷或其他合適物質如鎢、銅、鋁、金、銀、上述之合金、類似物、或上述之組合,且其沉積方法可為化學氣相沉積、原子層沉積、物理氣相沉積、物理氣相沉積與化學氣相沉積之組合、或另一沉積技術。在一些例子中,導電 材料110的頂部尺寸與底部尺寸之間的比例,介於約0.78至約0.88之間。在一些例子中,物理氣相沉積可用於沉積導電材料110至第一深度(比如高達約70Å至約100Å之間),而化學氣相沉積可用於沉積導電材料110於側壁上並填入剩餘的開口102(比如高達約180Å)。
在一些實施例中,在沉積導電材料110之後,可進行退火製程如快速熱退火。
如第16A與16B圖所示,在導電材料110上進行化學機械平坦製程。舉例來說,在退火之後可採用平坦化製程如化學機械研磨,以移除多餘材料。平坦化製程可自第一層間介電層100的上表面上移除多餘的導電材料110、氮化鈦層108、及/或預處理區106。因此,導電材料110、氮化鈦層108、預處理區106、及/或第一層間介電層100的上表面可共平面。
綜上所述,可形成含有導電材料110、連續的氮化鈦層108、及/或矽化物區如鈦矽化物的導電結構至磊晶源極/汲極區92。含有導電材料110、連續的氮化鈦層108、及/或矽化物區的導電結構,可稱作接點、插塞、接點插塞、或類似物。
雖然沉積的導電結構具有圖式中的設置,但導電結構可具有任何設置。舉例來說,可形成分開的導電結構以分開磊晶源極/汲極區92。本技術領域中具有通常知識者應理解,調整此處所述的製程步驟可達不同設置。
如第16A圖所示,氮預處理可形成具有氮濃度的預處理區106,其位於氮化鈦層108下或鄰接氮化鈦層108。若未進行預處理製程,則不存在預處理區106,且氮化鈦層108下不 具有氮濃度。第16C圖所示的第一圖表1602係未進行預處理製程的濃度輪廓,第二圖表1604係進行預處理製程時的導電結構其側壁的濃度輪廓,而第三圖表1606係進行預處理製程時的導電結構其底部的濃度輪廓。第一圖表1602、第二圖表1604、與第三圖表1606,係第16A圖之結構或未進行預處理製程的類似結構中多種位置的濃度。
第一圖表1602顯示與第16A圖的結構類似的結構中,多種位置的氮之第一濃度輪廓1612,且此結構未經氮預處理。第一圖表1602亦分別顯示結構中多種位置之鈦的第二濃度輪廓1614與矽的第三濃度輪廓1616。如第一圖表1602所示,對應氮化鈦層108的位置存在氮濃度,然而第一層間介電層100的位置中無氮或氮濃度不足,因為來自氮化鈦層108的氮擴散有限且未進行氮預處理。
第二圖表1604顯示第16A圖的結構側壁中,多種位置的氮之第一濃度輪廓1622,且此結構經過氮預處理。第二圖表1604亦分別顯示結構中多種位置之鈦的第二濃度輪廓1624與矽的第三濃度輪廓1626。第三圖表1606分別顯示第16A圖的結構底部中,多種位置的氮之第一濃度輪廓1632,且此結構經過氮預處理。第三圖表1606亦分別顯示結構中多種位置之鈦的第二濃度輪廓1634與矽的第三濃度輪廓1636。
如第二圖表1604所示,在進行氮預處理製程時,第一濃度輪廓1622在沿著第一層間介電層100的側壁之第一層間介電層100中(比如預處理區106中)的氮濃度,高於第一圖表1602中的第一濃度輪廓1612在對應位置中的氮濃度。如第三圖 表1606所示,在進行氮預處理製程時,第一濃度輪廓1632沿著氮化鈦層108下的磊晶源極/汲極區92的導電結構之下表面,具有氮濃度於磊晶源極/汲極區92中(比如預處理區106中)。第二圖表1604與第三圖表1606中的預處理區106,其深度或厚度可介於約1Å至約50Å之間。
如第17A與17B圖所示,形成一或多個介電層112,並形成導電結構114於一或多個介電層112中。舉例來說,一或多個介電層112可包含蝕刻停止層與層間介電層(或金屬間介電層)。蝕刻停止層可沉積於第一層間介電層100、導電材料110、氮化鈦層108、預處理區106、與類似物中至少一者上,且層間介電層或金屬間介電層可沉積於蝕刻停止層上。蝕刻停止層可包括或可為氮化矽、氮碳化矽、碳氧化矽、氮化碳、類似物、或上述之組合,且其沉積方法可為化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、或另一沉積技術。層間介電層或金屬間介電層可包含或可為氧化矽、低介電常數介電材料如氮氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、有機矽酸鹽玻璃、碳氧化矽、旋轉塗佈玻璃、旋轉塗佈聚合物、矽碳材料、上述之化合物、上述之複合物、類似物、或上述之組合。層間介電層或金屬間介電層的沉積方法可為旋轉塗佈、化學氣相沉積、可流動的化學氣相沉積、電漿增強化學氣相沉積、物理氣相沉積、或另一沉積技術。
凹陷及/或開口形成於一或多個介電層112中,及/或穿過一或多個介電層112,且凹陷及/或開口位於即將形成導電結構114的位置。可圖案化一或多個介電層112以形成凹陷及 /或開口,且圖案化方法可採用光微影與一或多道蝕刻製程。接著可形成導電結構114於凹陷及/或開口中。舉例來說,導電結構114可包含阻障層,與形成於阻障層上的導電材料。阻障層可順應性地沉積於凹陷及/或開口中與一或多個介電層112上。阻障層可為或可包含氮化鈦、氧化鈦、氮化鉭、氧化鉭、類似物、或上述之組合,且其沉積方法可為原子層沉積、化學氣相沉積、或另一沉積技術。導電材料可為或可包含鎢、銅、鋁、金、銀、上述之合金、類似物、或上述之組合,且其沉積方法可為化學氣相沉積、原子層沉積、物理氣相沉積、或另一沉積技術。舉例來說,在沉積導電結構114的材料之後,可採用平坦化製程如化學機械研磨移除多餘材料。平坦化製程可自一或多個介電層的上表面移除導電結構114的多餘材料。因此導電結構114與一或多個介電層112的上表面可共平面。導電結構114可為或可稱作接點、通孔、導電線路、或類似物。
第18A與18B圖至第21A與21B圖係一些實施例中,形成半導體裝置的另一例示性製程的中間階段中,個別中間結構的剖視圖。第18A與18B圖至第21A與21B圖係此處所述的置換閘極製程的其他實施例。先進行第2A與2B圖至第10A與10B圖所示的製程。
如第18A與18B圖所示,將閘極堆疊置換為置換閘極結構。第一層間介電層100與接點蝕刻停止層96的上表面可與虛置閘極82的上表面共平面。可進行平坦化製程如化學機械研磨,使第一層間介電層100與接點蝕刻停止層96的上表面與虛置閘極82的上表面齊平。化學機械研磨亦可移除虛置閘極82 上的遮罩84(以及一些例子中的閘極間隔物86其上側部份)。綜上所述,虛置閘極82的上表面自第一層間介電層100與接點蝕刻停止層96露出。
可移除自第一層間介電層100與接點蝕刻停止層96露出的虛置閘極82,且移除方法可為一或多道蝕刻製程。虛置閘極82的移除方法可為對虛置閘極82具有選擇性的蝕刻製程,其中界面介電層80作為蝕刻停止層。接著可視情況移除界面介電層80,其移除方法可為對界面介電層80具有選擇性的不同蝕刻製程。舉例來說,蝕刻製程可為反應性離子蝕刻、中性束蝕刻、濕蝕刻、或另一蝕刻製程。凹陷形成於閘極間隔物86之間(即移除閘極堆疊處),以露出鰭狀物74的通道區。
置換閘極結構形成於凹陷(即移除閘極堆疊處)中。如圖所示,置換閘極結構各自包含界面介電層120、閘極介電層122、一或多個視情況形成的順應層124、與閘極126。界面介電層120沿著通道區形成於鰭狀物74的側壁與上表面上。舉例來說,界面介電層120可為界面介電層80(若未移除)、熱氧化或化學氧化鰭狀物74而成的氧化物(如氧化矽)、及/或化學氣相沉積、原子層沉積、分子束沉積、或另一沉積技術形成的氧化物(如氧化矽)、氮化物(如氮化矽)、及/或另一介電層。
閘極介電層122可順應性地沉積於凹陷中,即閘極堆疊被移除處(比如沉積於隔離區78的上表面上、界面介電層120上、與閘極間隔物86的側壁上)。閘極介電層122亦可順應性地沉積於第一層間介電層100、接點蝕刻停止層96、與閘極間隔物86的上表面上。閘極介電層122可為或可包含氧化矽、 氮化矽、高介電常數介電材料、上述之多層、或其他介電材料。高介電常數介電材料的介電常數可大於約7.0,且可包含鉿、鋁、鋯、鑭、鎂、鋇、鈦、或鉛的金屬氧化物或金屬矽酸鹽、上述之多層、或上述之組合。閘極介電層122的沉積方法可為原子層沉積、電漿增強化學氣相沉積、分子束沉積、或另一沉積技術。
一或多個視情況形成的順應層124可包含一或多個阻障及/或蓋層,與一或多個功函數調整層。一或多個阻障及/或蓋層可包含氮化鉭、氮化鈦、類似物、或上述之組合,且其沉積方法可為原子層沉積、電漿增強化學氣相沉積、分子束沉積、或另一沉積技術。一或多個功函數調整層可包含或可為碳化鋁鈦、氧化鋁鈦、氮化鋁鈦、類似物、或上述之組合,且其沉積方法可為原子層沉積、電漿增強化學氣相沉積、分子束沉積、或另一沉積技術。在一些例子中,蓋層如氮化鈦層可順應性地形成於閘極介電層122上,第一阻障層如氮化鉭層可順應性地形成於蓋層上,一或多個功函數調整層順應性地依序形成於第一阻障層上,且第二阻障層如氮化鈦層形成於一或多個功函數調整層上。
用於閘極126的層狀物形成於一或多個順應層124(若實施)上,及/或閘極介電層122上。用於閘極126的層狀物可填入其餘凹陷(即移除閘極堆疊處)。用於閘極126的層狀物可為或可包括含金屬材料如鎢、鈷、鋁、釕、銅、上述之多層、上述之組合、或類似物。用於閘極126的層狀物其沉積方法可為原子層沉積、電漿增強化學氣相沉積、分子束沉積、物理氣相 沉積、或另一沉積技術。可移除用於閘極126、一或多個順應層124、與閘極介電層122高於第一層間介電層100、接點蝕刻停止層96、與閘極間隔物86的部份。舉例來說,平坦化製程如化學機械研磨可移除用於閘極126、一或多個順應層124、與閘極介電層122高於第一層間介電層100、接點蝕刻停止層96、與閘極間隔物86的部份。接著可回蝕刻閘極126、一或多個順應層124、與閘極介電層122的上表面,使其凹陷至低於第一層間介電層100、接點蝕刻停止層96、與閘極間隔物86的上表面。舉例來說,回蝕刻可為反應性離子蝕刻、濕蝕刻、或另一蝕刻製程。因此可形成包含閘極126、一或多個順應層124、閘極介電層122、與界面介電層120的置換閘極結構,如第12A圖所示。
用於遮罩128的層狀物可形成於閘極126、一或多個順應層124、與閘極介電層122上(比如閘極126、一或多個順應層124、與閘極介電層122被回蝕刻處),以及第一層間介電層100、接點蝕刻停止層96、與閘極間隔物86上。用於遮罩128的層狀物可包含或可為氮氧化矽、氮化矽、碳化矽、氮碳化矽、類似物、或上述之組合,且其沉積方法可為化學氣相沉積、物理氣相沉積、原子層沉積、或另一沉積技術。可移除高於第一層間介電層100、接點蝕刻停止層96、與閘極間隔物86的上表面之用於遮罩128的層狀物其部份。舉例來說,平坦化製程如化學機械研磨,可移除高於第一層間介電層100、接點蝕刻停止層96、與閘極間隔物86的上表面之用於遮罩128的層狀物其部份,且遮罩128的上表面可與第一層間介電層100、接點蝕刻停止層、與閘極間隔物86的上表面共平面。
如第19A與19B圖所示,形成第二層間介電層130於第一層間介電層100、遮罩128、閘極間隔物86、與接點蝕刻停止層96上。雖然未圖示,一些例子中的蝕刻停止層可沉積於第一層間介電層100與其他層上,且第二層間介電層130可沉積於蝕刻停止層上。若形成蝕刻停止層,其材料可包含或可為氮化矽、氮碳化矽、碳氧化矽、氮化碳、類似物、或上述之組合,且其沉積方法可為化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、或另一沉積技術。第二層間介電層130可包含或可為氧化矽、低介電常數介電材料如氮氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、有機矽酸鹽玻璃、碳氧化矽、旋轉塗佈玻璃、矽碳材料、上述之化合物、上述之複合物、類似物、或上述之組合。第二層間介電層130的沉積方法可為旋轉塗佈、化學氣相沉積、可流動的化學氣相沉積、電漿增強化學氣相沉積、物理氣相沉積、或另一沉積技術。
如第20A與20B圖所示的例子中,形成開口132穿過第二層間介電層130、第一層間介電層100、與接點蝕刻停止層96至磊晶源極/汲極區92,並露出磊晶源極/汲極區92的至少部份。舉例來說,圖案化第二層間介電層130、第一層間介電層100、與接點蝕刻停止層96以形成開口132的方法,可採用光微影與一或多道蝕刻製程。
如第21A與21B圖所示,形成導電結構於開口132中,至磊晶源極/汲極區92。如圖所示,每一導電結構包含預處理區106、預處理區106上的金屬氮化物層(如氮化鈦層108)、 與氮化鈦層108上的導電材料110(如鈷)填入開口132中。在一些例子中,每一導電結構亦可包含矽化物區於磊晶源極/汲極區92上。
本發明實施例可提供優點。此處所述的技術可用於連續的氮化鈦阻障層以形成接點插塞,其可改善半導體裝置的效能,比如在高深寬比孔洞中減少空洞並改善填隙能力。
在一實施例中,提供半導體裝置的形成方法。方法一般包括形成開口,穿過介電層至基板上的主動區。方法包括沿著開口的側壁進行第一電漿處理。方法包括進行原子層沉積製程,以沿著開口的側壁形成金屬氮化物層。原子層沉積製程包括多個循環。每一循環包括:使前驅物流入以沿著開口的側壁形成金屬單層;以及進行第二電漿處理,以氮處理金屬單層。方法包括沉積導電材料於開口中的金屬氮化物層上,以形成導電結構。
在一些實施例中,上述方法的介電層包括層間介電層,且開口形成至主動區的源極/汲極區。
在一些實施例中,上述方法更包括經由開口形成矽化物區於主動區的源極/汲極區上,其中矽化物包括鈦矽材料。
在一些實施例中,上述方法的開口其深寬比大於3。
在一些實施例中,上述方法更包括在導電材料上進行快速熱退火。
在一些實施例中,上述方法的導電材料包括鈷材 料,且導電結構包括接點插塞。
在一些實施例中,上述方法在進行原子層沉積製程之前,更包括採用雙區加熱器加熱基板,且雙區加熱器設置以不同溫度加熱基板的不同區域;以及在原子層沉積與電漿處理製程中至少一者動態調整基板的不同區域之溫度。
在一些實施例中,上述方法的第一電漿處理為等向,其中第一電漿處理採用遠端電漿源,且第一電漿處理的氣體包括氮、氦、與氬中至少一者。
在一些實施例中,上述方法的前驅物包括四(二甲基胺基)鈦前驅物。
在另一實施例中,提供半導體結構。半導體結構通常包括主動區於基板上。主動區包括源極/汲極區。半導體結構包括層間介電層於主動區上。半導體結構包括沿著層間介電層其側壁的氮處理區。層間介電層的側壁延伸至主動區。半導體結構包括沿著氮處理區的金屬氮化物層。半導體結構包括導電材料形成於金屬氮化物層上。
在一些實施例中,上述半導體結構中沿著層間介電層的側壁之氮處理區,其厚度介於1Å至50Å之間。
在一些實施例中,上述半導體結構中的導電材料包括鈷。
在一些實施例中,上述半導體結構中的層間介電層包括低介電常數介電材料。
在一些實施例中,上述半導體結構更包括矽化物區於主動區的源極/汲極區上,層間介電層的側壁延伸至矽化 物區,且矽化物包括鈦矽。
在一些實施例中,上述半導體結構的層間介電層其側壁至對向的側壁之間具有寬度,層間介電層其側壁具有高度,且高度對寬度的比例大於3。
在另一實施例中,提供另一半導體裝置的形成方法。方法一般包括形成鰭狀物於基板上。方法包括形成閘極結構於鰭狀物上。方法包括形成介電層於鰭狀物上。方法包括形成開口穿過介電層至與閘極結構相鄰之鰭狀物的源極/汲極區。方法包括形成導電結構於開口中。形成導電結構的步驟包括沿著開口的側表面進行第一電漿處理。形成導電結構的步驟包括沿著處理後的側表面形成黏著層。黏著層的形成方法為原子層沉積製程,其包括多個循環。每一循環包括使前驅物流入,以沿著處理後的側表面形成金屬單層;以及進行第二電漿處理,以氮處理金屬單層。形成導電結構的步驟包括沉積導電材料於黏著層上以填滿開口。
在一些實施例中,上述方法的側表面包括層間介電材料。
在一些實施例中,上述方法的導電材料包括鈷材料,且導電結構包括接點插塞。
在一實施例中,上述方法更包括在進行原子層沉積製程之前,採用區域加熱器加熱基板,且區域加熱器設置以不同溫度加熱基板的不同區域;以及在原子層沉積製程與電漿處理製程中至少一者動態調整基板其不同區域的溫度。
在一實施例中,上述方法的第一電漿處理為等 向,其中第一電漿處理採用遠端電漿源,且第一電漿處理的氣體包含氮、氦、與氬中至少一者。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明實施例作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明精神與範疇,並可在未脫離本發明之申請專利範圍的精神與範疇的前提下進行改變、替換、或更動。

Claims (1)

  1. 一種半導體裝置的形成方法,包括:形成一開口,穿過一介電層至一基板上的一主動區;沿著該開口的側壁進行一第一電漿處理;進行一原子層沉積製程,以沿著該開口的側壁形成一金屬氮化物層,其中該原子層沉積製程包括多個循環,且每一該些循環包括:使一前驅物流入以沿著該開口的側壁形成一金屬單層;以及進行一第二電漿處理,以氮處理該金屬單層;以及沉積一導電材料於該開口中的該金屬氮化物層上,以形成一導電結構。
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